4 * Copyright (c) 2005-2006 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
30 #define DPRINTF(fmt, args...) \
31 do { printf("ESP: " fmt , ##args); } while (0)
32 #define pic_set_irq(irq, level) \
33 do { printf("ESP: set_irq(%d): %d\n", (irq), (level)); pic_set_irq((irq),(level));} while (0)
35 #define DPRINTF(fmt, args...)
39 #define ESPDMA_MAXADDR (ESPDMA_REGS * 4 - 1)
40 #define ESP_MAXREG 0x3f
42 #define DMA_VER 0xa0000000
44 #define DMA_INTREN 0x10
45 #define DMA_WRITE_MEM 0x100
46 #define DMA_LOADED 0x04000000
47 typedef struct ESPState ESPState;
50 BlockDriverState **bd;
51 uint8_t rregs[ESP_MAXREG];
52 uint8_t wregs[ESP_MAXREG];
54 uint32_t espdmaregs[ESPDMA_REGS];
56 uint32_t ti_rptr, ti_wptr;
57 uint8_t ti_buf[TI_BUFSZ];
60 SCSIDevice *scsi_dev[MAX_DISKS];
61 SCSIDevice *current_dev;
62 uint8_t cmdbuf[TI_BUFSZ];
85 static int get_cmd(ESPState *s, uint8_t *buf)
87 uint32_t dmaptr, dmalen;
90 dmalen = s->wregs[0] | (s->wregs[1] << 8);
91 target = s->wregs[4] & 7;
92 DPRINTF("get_cmd: len %d target %d\n", dmalen, target);
94 dmaptr = iommu_translate(s->espdmaregs[1]);
95 DPRINTF("DMA Direction: %c, addr 0x%8.8x\n",
96 s->espdmaregs[0] & DMA_WRITE_MEM ? 'w': 'r', dmaptr);
97 cpu_physical_memory_read(dmaptr, buf, dmalen);
100 memcpy(&buf[1], s->ti_buf, dmalen);
108 if (target >= 4 || !s->scsi_dev[target]) {
110 s->rregs[4] = STAT_IN;
111 s->rregs[5] = INTR_DC;
113 s->espdmaregs[0] |= DMA_INTR;
114 pic_set_irq(s->irq, 1);
117 s->current_dev = s->scsi_dev[target];
121 static void do_cmd(ESPState *s, uint8_t *buf)
126 DPRINTF("do_cmd: busid 0x%x\n", buf[0]);
128 datalen = scsi_send_command(s->current_dev, 0, &buf[1], lun);
132 s->rregs[4] = STAT_IN | STAT_TC;
134 s->rregs[4] |= STAT_DI;
135 s->ti_size = datalen;
137 s->rregs[4] |= STAT_DO;
138 s->ti_size = -datalen;
141 s->rregs[5] = INTR_BS | INTR_FC;
142 s->rregs[6] = SEQ_CD;
143 s->espdmaregs[0] |= DMA_INTR;
144 pic_set_irq(s->irq, 1);
147 static void handle_satn(ESPState *s)
152 len = get_cmd(s, buf);
157 static void handle_satn_stop(ESPState *s)
159 s->cmdlen = get_cmd(s, s->cmdbuf);
161 DPRINTF("Set ATN & Stop: cmdlen %d\n", s->cmdlen);
163 s->espdmaregs[1] += s->cmdlen;
164 s->rregs[4] = STAT_IN | STAT_TC | STAT_CD;
165 s->rregs[5] = INTR_BS | INTR_FC;
166 s->rregs[6] = SEQ_CD;
167 s->espdmaregs[0] |= DMA_INTR;
168 pic_set_irq(s->irq, 1);
172 static void write_response(ESPState *s)
176 DPRINTF("Transfer status (sense=%d)\n", s->sense);
177 s->ti_buf[0] = s->sense;
180 dmaptr = iommu_translate(s->espdmaregs[1]);
181 DPRINTF("DMA Direction: %c\n",
182 s->espdmaregs[0] & DMA_WRITE_MEM ? 'w': 'r');
183 cpu_physical_memory_write(dmaptr, s->ti_buf, 2);
184 s->rregs[4] = STAT_IN | STAT_TC | STAT_ST;
185 s->rregs[5] = INTR_BS | INTR_FC;
186 s->rregs[6] = SEQ_CD;
193 s->espdmaregs[0] |= DMA_INTR;
194 pic_set_irq(s->irq, 1);
198 static void esp_command_complete(void *opaque, uint32_t tag, int sense)
200 ESPState *s = (ESPState *)opaque;
202 DPRINTF("SCSI Command complete\n");
204 DPRINTF("SCSI command completed unexpectedly\n");
207 DPRINTF("Command failed\n");
209 s->rregs[4] = STAT_IN | STAT_TC | STAT_ST;
212 static void handle_ti(ESPState *s)
214 uint32_t dmaptr, dmalen, minlen, len, from, to;
217 uint8_t buf[TARGET_PAGE_SIZE];
219 dmalen = s->wregs[0] | (s->wregs[1] << 8);
225 minlen = (dmalen < 32) ? dmalen : 32;
227 minlen = (dmalen < s->ti_size) ? dmalen : s->ti_size;
228 DPRINTF("Transfer Information len %d\n", minlen);
230 dmaptr = iommu_translate(s->espdmaregs[1]);
231 /* Check if the transfer writes to to reads from the device. */
232 to_device = (s->espdmaregs[0] & DMA_WRITE_MEM) == 0;
233 DPRINTF("DMA Direction: %c, addr 0x%8.8x %08x\n",
234 to_device ? 'r': 'w', dmaptr, s->ti_size);
235 from = s->espdmaregs[1];
237 for (i = 0; i < minlen; i += len, from += len) {
238 dmaptr = iommu_translate(s->espdmaregs[1] + i);
239 if ((from & TARGET_PAGE_MASK) != (to & TARGET_PAGE_MASK)) {
240 len = TARGET_PAGE_SIZE - (from & ~TARGET_PAGE_MASK);
244 DPRINTF("DMA address p %08x v %08x len %08x, from %08x, to %08x\n", dmaptr, s->espdmaregs[1] + i, len, from, to);
247 DPRINTF("command len %d + %d\n", s->cmdlen, len);
248 cpu_physical_memory_read(dmaptr, &s->cmdbuf[s->cmdlen], len);
252 do_cmd(s, s->cmdbuf);
256 cpu_physical_memory_read(dmaptr, buf, len);
257 scsi_write_data(s->current_dev, buf, len);
259 scsi_read_data(s->current_dev, buf, len);
260 cpu_physical_memory_write(dmaptr, buf, len);
265 s->rregs[4] = STAT_IN | STAT_TC | (to_device ? STAT_DO : STAT_DI);
267 s->rregs[5] = INTR_BS;
270 s->espdmaregs[0] |= DMA_INTR;
271 } else if (s->do_cmd) {
272 DPRINTF("command len %d\n", s->cmdlen);
276 do_cmd(s, s->cmdbuf);
279 pic_set_irq(s->irq, 1);
282 static void esp_reset(void *opaque)
284 ESPState *s = opaque;
285 memset(s->rregs, 0, ESP_MAXREG);
286 memset(s->wregs, 0, ESP_MAXREG);
287 s->rregs[0x0e] = 0x4; // Indicate fas100a
288 memset(s->espdmaregs, 0, ESPDMA_REGS * 4);
296 static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
298 ESPState *s = opaque;
301 saddr = (addr & ESP_MAXREG) >> 2;
302 DPRINTF("read reg[%d]: 0x%2.2x\n", saddr, s->rregs[saddr]);
306 if (s->ti_size > 0) {
308 if ((s->rregs[4] & 6) == 0) {
310 scsi_read_data(s->current_dev, &s->rregs[2], 0);
312 s->rregs[2] = s->ti_buf[s->ti_rptr++];
314 pic_set_irq(s->irq, 1);
316 if (s->ti_size == 0) {
323 // Clear status bits except TC
324 s->rregs[4] &= STAT_TC;
325 pic_set_irq(s->irq, 0);
326 s->espdmaregs[0] &= ~DMA_INTR;
331 return s->rregs[saddr];
334 static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
336 ESPState *s = opaque;
339 saddr = (addr & ESP_MAXREG) >> 2;
340 DPRINTF("write reg[%d]: 0x%2.2x -> 0x%2.2x\n", saddr, s->wregs[saddr], val);
344 s->rregs[saddr] = val;
349 s->cmdbuf[s->cmdlen++] = val & 0xff;
350 } else if ((s->rregs[4] & 6) == 0) {
354 scsi_write_data(s->current_dev, &buf, 0);
357 s->ti_buf[s->ti_wptr++] = val & 0xff;
361 s->rregs[saddr] = val;
370 DPRINTF("NOP (%2.2x)\n", val);
373 DPRINTF("Flush FIFO (%2.2x)\n", val);
375 s->rregs[5] = INTR_FC;
379 DPRINTF("Chip reset (%2.2x)\n", val);
383 DPRINTF("Bus reset (%2.2x)\n", val);
384 s->rregs[5] = INTR_RST;
385 if (!(s->wregs[8] & 0x40)) {
386 s->espdmaregs[0] |= DMA_INTR;
387 pic_set_irq(s->irq, 1);
394 DPRINTF("Initiator Command Complete Sequence (%2.2x)\n", val);
398 DPRINTF("Message Accepted (%2.2x)\n", val);
400 s->rregs[5] = INTR_DC;
404 DPRINTF("Set ATN (%2.2x)\n", val);
407 DPRINTF("Set ATN (%2.2x)\n", val);
411 DPRINTF("Set ATN & stop (%2.2x)\n", val);
415 DPRINTF("Unhandled ESP command (%2.2x)\n", val);
422 s->rregs[saddr] = val;
427 s->rregs[saddr] = val & 0x15;
430 s->rregs[saddr] = val;
435 s->wregs[saddr] = val;
438 static CPUReadMemoryFunc *esp_mem_read[3] = {
444 static CPUWriteMemoryFunc *esp_mem_write[3] = {
450 static uint32_t espdma_mem_readl(void *opaque, target_phys_addr_t addr)
452 ESPState *s = opaque;
455 saddr = (addr & ESPDMA_MAXADDR) >> 2;
456 DPRINTF("read dmareg[%d]: 0x%8.8x\n", saddr, s->espdmaregs[saddr]);
458 return s->espdmaregs[saddr];
461 static void espdma_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
463 ESPState *s = opaque;
466 saddr = (addr & ESPDMA_MAXADDR) >> 2;
467 DPRINTF("write dmareg[%d]: 0x%8.8x -> 0x%8.8x\n", saddr, s->espdmaregs[saddr], val);
470 if (!(val & DMA_INTREN))
471 pic_set_irq(s->irq, 0);
474 } else if (val & 0x40) {
482 s->espdmaregs[0] |= DMA_LOADED;
487 s->espdmaregs[saddr] = val;
490 static CPUReadMemoryFunc *espdma_mem_read[3] = {
496 static CPUWriteMemoryFunc *espdma_mem_write[3] = {
502 static void esp_save(QEMUFile *f, void *opaque)
504 ESPState *s = opaque;
507 qemu_put_buffer(f, s->rregs, ESP_MAXREG);
508 qemu_put_buffer(f, s->wregs, ESP_MAXREG);
509 qemu_put_be32s(f, &s->irq);
510 for (i = 0; i < ESPDMA_REGS; i++)
511 qemu_put_be32s(f, &s->espdmaregs[i]);
512 qemu_put_be32s(f, &s->ti_size);
513 qemu_put_be32s(f, &s->ti_rptr);
514 qemu_put_be32s(f, &s->ti_wptr);
515 qemu_put_buffer(f, s->ti_buf, TI_BUFSZ);
516 qemu_put_be32s(f, &s->dma);
519 static int esp_load(QEMUFile *f, void *opaque, int version_id)
521 ESPState *s = opaque;
527 qemu_get_buffer(f, s->rregs, ESP_MAXREG);
528 qemu_get_buffer(f, s->wregs, ESP_MAXREG);
529 qemu_get_be32s(f, &s->irq);
530 for (i = 0; i < ESPDMA_REGS; i++)
531 qemu_get_be32s(f, &s->espdmaregs[i]);
532 qemu_get_be32s(f, &s->ti_size);
533 qemu_get_be32s(f, &s->ti_rptr);
534 qemu_get_be32s(f, &s->ti_wptr);
535 qemu_get_buffer(f, s->ti_buf, TI_BUFSZ);
536 qemu_get_be32s(f, &s->dma);
541 void esp_init(BlockDriverState **bd, int irq, uint32_t espaddr, uint32_t espdaddr)
544 int esp_io_memory, espdma_io_memory;
547 s = qemu_mallocz(sizeof(ESPState));
554 esp_io_memory = cpu_register_io_memory(0, esp_mem_read, esp_mem_write, s);
555 cpu_register_physical_memory(espaddr, ESP_MAXREG*4, esp_io_memory);
557 espdma_io_memory = cpu_register_io_memory(0, espdma_mem_read, espdma_mem_write, s);
558 cpu_register_physical_memory(espdaddr, 16, espdma_io_memory);
562 register_savevm("esp", espaddr, 1, esp_save, esp_load, s);
563 qemu_register_reset(esp_reset, s);
564 for (i = 0; i < MAX_DISKS; i++) {
567 scsi_disk_init(bs_table[i], esp_command_complete, s);