2 * QEMU ES1370 emulation
4 * Copyright (c) 2005 Vassili Karpov (malc)
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 /* #define DEBUG_ES1370 */
26 /* #define VERBOSE_ES1370 */
32 SCTRL_P[12](END|ST)INC
42 Following macros and samplerate array were copied verbatim from
43 Linux kernel 2.4.30: drivers/sound/es1370.c
45 Copyright (C) 1998-2001, 2003 Thomas Sailer (t.sailer@alumni.ethz.ch)
48 /* Start blatant GPL violation */
50 #define ES1370_REG_CONTROL 0x00
51 #define ES1370_REG_STATUS 0x04
52 #define ES1370_REG_UART_DATA 0x08
53 #define ES1370_REG_UART_STATUS 0x09
54 #define ES1370_REG_UART_CONTROL 0x09
55 #define ES1370_REG_UART_TEST 0x0a
56 #define ES1370_REG_MEMPAGE 0x0c
57 #define ES1370_REG_CODEC 0x10
58 #define ES1370_REG_SERIAL_CONTROL 0x20
59 #define ES1370_REG_DAC1_SCOUNT 0x24
60 #define ES1370_REG_DAC2_SCOUNT 0x28
61 #define ES1370_REG_ADC_SCOUNT 0x2c
63 #define ES1370_REG_DAC1_FRAMEADR 0xc30
64 #define ES1370_REG_DAC1_FRAMECNT 0xc34
65 #define ES1370_REG_DAC2_FRAMEADR 0xc38
66 #define ES1370_REG_DAC2_FRAMECNT 0xc3c
67 #define ES1370_REG_ADC_FRAMEADR 0xd30
68 #define ES1370_REG_ADC_FRAMECNT 0xd34
69 #define ES1370_REG_PHANTOM_FRAMEADR 0xd38
70 #define ES1370_REG_PHANTOM_FRAMECNT 0xd3c
72 static const unsigned dac1_samplerate[] = { 5512, 11025, 22050, 44100 };
74 #define DAC2_SRTODIV(x) (((1411200+(x)/2)/(x))-2)
75 #define DAC2_DIVTOSR(x) (1411200/((x)+2))
77 #define CTRL_ADC_STOP 0x80000000 /* 1 = ADC stopped */
78 #define CTRL_XCTL1 0x40000000 /* electret mic bias */
79 #define CTRL_OPEN 0x20000000 /* no function, can be read and written */
80 #define CTRL_PCLKDIV 0x1fff0000 /* ADC/DAC2 clock divider */
81 #define CTRL_SH_PCLKDIV 16
82 #define CTRL_MSFMTSEL 0x00008000 /* MPEG serial data fmt: 0 = Sony, 1 = I2S */
83 #define CTRL_M_SBB 0x00004000 /* DAC2 clock: 0 = PCLKDIV, 1 = MPEG */
84 #define CTRL_WTSRSEL 0x00003000 /* DAC1 clock freq: 0=5512, 1=11025, 2=22050, 3=44100 */
85 #define CTRL_SH_WTSRSEL 12
86 #define CTRL_DAC_SYNC 0x00000800 /* 1 = DAC2 runs off DAC1 clock */
87 #define CTRL_CCB_INTRM 0x00000400 /* 1 = CCB "voice" ints enabled */
88 #define CTRL_M_CB 0x00000200 /* recording source: 0 = ADC, 1 = MPEG */
89 #define CTRL_XCTL0 0x00000100 /* 0 = Line in, 1 = Line out */
90 #define CTRL_BREQ 0x00000080 /* 1 = test mode (internal mem test) */
91 #define CTRL_DAC1_EN 0x00000040 /* enable DAC1 */
92 #define CTRL_DAC2_EN 0x00000020 /* enable DAC2 */
93 #define CTRL_ADC_EN 0x00000010 /* enable ADC */
94 #define CTRL_UART_EN 0x00000008 /* enable MIDI uart */
95 #define CTRL_JYSTK_EN 0x00000004 /* enable Joystick port (presumably at address 0x200) */
96 #define CTRL_CDC_EN 0x00000002 /* enable serial (CODEC) interface */
97 #define CTRL_SERR_DIS 0x00000001 /* 1 = disable PCI SERR signal */
99 #define STAT_INTR 0x80000000 /* wired or of all interrupt bits */
100 #define STAT_CSTAT 0x00000400 /* 1 = codec busy or codec write in progress */
101 #define STAT_CBUSY 0x00000200 /* 1 = codec busy */
102 #define STAT_CWRIP 0x00000100 /* 1 = codec write in progress */
103 #define STAT_VC 0x00000060 /* CCB int source, 0=DAC1, 1=DAC2, 2=ADC, 3=undef */
105 #define STAT_MCCB 0x00000010 /* CCB int pending */
106 #define STAT_UART 0x00000008 /* UART int pending */
107 #define STAT_DAC1 0x00000004 /* DAC1 int pending */
108 #define STAT_DAC2 0x00000002 /* DAC2 int pending */
109 #define STAT_ADC 0x00000001 /* ADC int pending */
111 #define USTAT_RXINT 0x80 /* UART rx int pending */
112 #define USTAT_TXINT 0x04 /* UART tx int pending */
113 #define USTAT_TXRDY 0x02 /* UART tx ready */
114 #define USTAT_RXRDY 0x01 /* UART rx ready */
116 #define UCTRL_RXINTEN 0x80 /* 1 = enable RX ints */
117 #define UCTRL_TXINTEN 0x60 /* TX int enable field mask */
118 #define UCTRL_ENA_TXINT 0x20 /* enable TX int */
119 #define UCTRL_CNTRL 0x03 /* control field */
120 #define UCTRL_CNTRL_SWR 0x03 /* software reset command */
122 #define SCTRL_P2ENDINC 0x00380000 /* */
123 #define SCTRL_SH_P2ENDINC 19
124 #define SCTRL_P2STINC 0x00070000 /* */
125 #define SCTRL_SH_P2STINC 16
126 #define SCTRL_R1LOOPSEL 0x00008000 /* 0 = loop mode */
127 #define SCTRL_P2LOOPSEL 0x00004000 /* 0 = loop mode */
128 #define SCTRL_P1LOOPSEL 0x00002000 /* 0 = loop mode */
129 #define SCTRL_P2PAUSE 0x00001000 /* 1 = pause mode */
130 #define SCTRL_P1PAUSE 0x00000800 /* 1 = pause mode */
131 #define SCTRL_R1INTEN 0x00000400 /* enable interrupt */
132 #define SCTRL_P2INTEN 0x00000200 /* enable interrupt */
133 #define SCTRL_P1INTEN 0x00000100 /* enable interrupt */
134 #define SCTRL_P1SCTRLD 0x00000080 /* reload sample count register for DAC1 */
135 #define SCTRL_P2DACSEN 0x00000040 /* 1 = DAC2 play back last sample when disabled */
136 #define SCTRL_R1SEB 0x00000020 /* 1 = 16bit */
137 #define SCTRL_R1SMB 0x00000010 /* 1 = stereo */
138 #define SCTRL_R1FMT 0x00000030 /* format mask */
139 #define SCTRL_SH_R1FMT 4
140 #define SCTRL_P2SEB 0x00000008 /* 1 = 16bit */
141 #define SCTRL_P2SMB 0x00000004 /* 1 = stereo */
142 #define SCTRL_P2FMT 0x0000000c /* format mask */
143 #define SCTRL_SH_P2FMT 2
144 #define SCTRL_P1SEB 0x00000002 /* 1 = 16bit */
145 #define SCTRL_P1SMB 0x00000001 /* 1 = stereo */
146 #define SCTRL_P1FMT 0x00000003 /* format mask */
147 #define SCTRL_SH_P1FMT 0
149 /* End blatant GPL violation */
151 #define NB_CHANNELS 3
152 #define DAC1_CHANNEL 0
153 #define DAC2_CHANNEL 1
154 #define ADC_CHANNEL 2
156 #define IO_READ_PROTO(n) \
157 static uint32_t n (void *opaque, uint32_t addr)
158 #define IO_WRITE_PROTO(n) \
159 static void n (void *opaque, uint32_t addr, uint32_t val)
161 static void es1370_dac1_callback (void *opaque, int free);
162 static void es1370_dac2_callback (void *opaque, int free);
163 static void es1370_adc_callback (void *opaque, int avail);
167 #define ldebug(...) AUD_log ("es1370", __VA_ARGS__)
169 static void print_ctl (uint32_t val)
174 #define a(n) if (val & CTRL_##n) strcat (buf, " "#n)
193 AUD_log ("es1370", "ctl - PCLKDIV %d(DAC2 freq %d), freq %d,%s\n",
194 (val & CTRL_PCLKDIV) >> CTRL_SH_PCLKDIV,
195 DAC2_DIVTOSR ((val & CTRL_PCLKDIV) >> CTRL_SH_PCLKDIV),
196 dac1_samplerate[(val & CTRL_WTSRSEL) >> CTRL_SH_WTSRSEL],
200 static void print_sctl (uint32_t val)
202 static const char *fmt_names[] = {"8M", "8S", "16M", "16S"};
207 #define a(n) if (val & SCTRL_##n) strcat (buf, " "#n)
208 #define b(n) if (!(val & SCTRL_##n)) strcat (buf, " "#n)
230 "p2_end_inc %d, p2_st_inc %d, r1_fmt %s, p2_fmt %s, p1_fmt %s\n",
232 (val & SCTRL_P2ENDINC) >> SCTRL_SH_P2ENDINC,
233 (val & SCTRL_P2STINC) >> SCTRL_SH_P2STINC,
234 fmt_names [(val >> SCTRL_SH_R1FMT) & 3],
235 fmt_names [(val >> SCTRL_SH_P2FMT) & 3],
236 fmt_names [(val >> SCTRL_SH_P1FMT) & 3]
241 #define print_ctl(...)
242 #define print_sctl(...)
245 #ifdef VERBOSE_ES1370
246 #define dolog(...) AUD_log ("es1370", __VA_ARGS__)
251 #ifndef SILENT_ES1370
252 #define lwarn(...) AUD_log ("es1370: warning:", __VA_ARGS__)
265 typedef struct ES1370State {
269 struct chan chan[NB_CHANNELS];
270 SWVoiceOut *dac_voice[2];
271 SWVoiceIn *adc_voice;
280 typedef struct PCIES1370State {
291 uint32_t sctl_sh_fmt;
292 uint32_t sctl_loopsel;
293 void (*calc_freq) (ES1370State *s, uint32_t ctl,
294 uint32_t *old_freq, uint32_t *new_freq);
297 static void es1370_dac1_calc_freq (ES1370State *s, uint32_t ctl,
298 uint32_t *old_freq, uint32_t *new_freq);
299 static void es1370_dac2_and_adc_calc_freq (ES1370State *s, uint32_t ctl,
303 static const struct chan_bits es1370_chan_bits[] = {
304 {CTRL_DAC1_EN, STAT_DAC1, SCTRL_P1PAUSE, SCTRL_P1INTEN,
305 SCTRL_P1FMT, SCTRL_SH_P1FMT, SCTRL_P1LOOPSEL,
306 es1370_dac1_calc_freq},
308 {CTRL_DAC2_EN, STAT_DAC2, SCTRL_P2PAUSE, SCTRL_P2INTEN,
309 SCTRL_P2FMT, SCTRL_SH_P2FMT, SCTRL_P2LOOPSEL,
310 es1370_dac2_and_adc_calc_freq},
312 {CTRL_ADC_EN, STAT_ADC, 0, SCTRL_R1INTEN,
313 SCTRL_R1FMT, SCTRL_SH_R1FMT, SCTRL_R1LOOPSEL,
314 es1370_dac2_and_adc_calc_freq}
317 static void es1370_update_status (ES1370State *s, uint32_t new_status)
319 uint32_t level = new_status & (STAT_DAC1 | STAT_DAC2 | STAT_ADC);
322 s->status = new_status | STAT_INTR;
325 s->status = new_status & ~STAT_INTR;
327 pci_set_irq (s->pci_dev, 0, !!level);
330 static void es1370_reset (ES1370State *s)
340 for (i = 0; i < NB_CHANNELS; ++i) {
341 struct chan *d = &s->chan[i];
344 if (i == ADC_CHANNEL) {
345 AUD_close_in (&s->card, s->adc_voice);
349 AUD_close_out (&s->card, s->dac_voice[i]);
350 s->dac_voice[i] = NULL;
353 pci_set_irq (s->pci_dev, 0, 0);
356 static void es1370_maybe_lower_irq (ES1370State *s, uint32_t sctl)
358 uint32_t new_status = s->status;
360 if (!(sctl & SCTRL_P1INTEN) && (s->sctl & SCTRL_P1INTEN)) {
361 new_status &= ~STAT_DAC1;
364 if (!(sctl & SCTRL_P2INTEN) && (s->sctl & SCTRL_P2INTEN)) {
365 new_status &= ~STAT_DAC2;
368 if (!(sctl & SCTRL_R1INTEN) && (s->sctl & SCTRL_R1INTEN)) {
369 new_status &= ~STAT_ADC;
372 if (new_status != s->status) {
373 es1370_update_status (s, new_status);
377 static void es1370_dac1_calc_freq (ES1370State *s, uint32_t ctl,
378 uint32_t *old_freq, uint32_t *new_freq)
381 *old_freq = dac1_samplerate[(s->ctl & CTRL_WTSRSEL) >> CTRL_SH_WTSRSEL];
382 *new_freq = dac1_samplerate[(ctl & CTRL_WTSRSEL) >> CTRL_SH_WTSRSEL];
385 static void es1370_dac2_and_adc_calc_freq (ES1370State *s, uint32_t ctl,
390 uint32_t old_pclkdiv, new_pclkdiv;
392 new_pclkdiv = (ctl & CTRL_PCLKDIV) >> CTRL_SH_PCLKDIV;
393 old_pclkdiv = (s->ctl & CTRL_PCLKDIV) >> CTRL_SH_PCLKDIV;
394 *new_freq = DAC2_DIVTOSR (new_pclkdiv);
395 *old_freq = DAC2_DIVTOSR (old_pclkdiv);
398 static void es1370_update_voices (ES1370State *s, uint32_t ctl, uint32_t sctl)
401 uint32_t old_freq, new_freq, old_fmt, new_fmt;
403 for (i = 0; i < NB_CHANNELS; ++i) {
404 struct chan *d = &s->chan[i];
405 const struct chan_bits *b = &es1370_chan_bits[i];
407 new_fmt = (sctl & b->sctl_fmt) >> b->sctl_sh_fmt;
408 old_fmt = (s->sctl & b->sctl_fmt) >> b->sctl_sh_fmt;
410 b->calc_freq (s, ctl, &old_freq, &new_freq);
412 if ((old_fmt != new_fmt) || (old_freq != new_freq)) {
413 d->shift = (new_fmt & 1) + (new_fmt >> 1);
414 ldebug ("channel %d, freq = %d, nchannels %d, fmt %d, shift %d\n",
418 (new_fmt & 2) ? AUD_FMT_S16 : AUD_FMT_U8,
424 as.nchannels = 1 << (new_fmt & 1);
425 as.fmt = (new_fmt & 2) ? AUD_FMT_S16 : AUD_FMT_U8;
427 if (i == ADC_CHANNEL) {
443 i ? "es1370.dac2" : "es1370.dac1",
445 i ? es1370_dac2_callback : es1370_dac1_callback,
452 if (((ctl ^ s->ctl) & b->ctl_en)
453 || ((sctl ^ s->sctl) & b->sctl_pause)) {
454 int on = (ctl & b->ctl_en) && !(sctl & b->sctl_pause);
456 if (i == ADC_CHANNEL) {
457 AUD_set_active_in (s->adc_voice, on);
460 AUD_set_active_out (s->dac_voice[i], on);
469 static inline uint32_t es1370_fixup (ES1370State *s, uint32_t addr)
472 if (addr >= 0x30 && addr <= 0x3f)
473 addr |= s->mempage << 8;
477 IO_WRITE_PROTO (es1370_writeb)
479 ES1370State *s = opaque;
480 addr = es1370_fixup (s, addr);
481 uint32_t shift, mask;
484 case ES1370_REG_CONTROL:
485 case ES1370_REG_CONTROL + 1:
486 case ES1370_REG_CONTROL + 2:
487 case ES1370_REG_CONTROL + 3:
488 shift = (addr - ES1370_REG_CONTROL) << 3;
489 mask = 0xff << shift;
490 val = (s->ctl & ~mask) | ((val & 0xff) << shift);
491 es1370_update_voices (s, val, s->sctl);
494 case ES1370_REG_MEMPAGE:
497 case ES1370_REG_SERIAL_CONTROL:
498 case ES1370_REG_SERIAL_CONTROL + 1:
499 case ES1370_REG_SERIAL_CONTROL + 2:
500 case ES1370_REG_SERIAL_CONTROL + 3:
501 shift = (addr - ES1370_REG_SERIAL_CONTROL) << 3;
502 mask = 0xff << shift;
503 val = (s->sctl & ~mask) | ((val & 0xff) << shift);
504 es1370_maybe_lower_irq (s, val);
505 es1370_update_voices (s, s->ctl, val);
509 lwarn ("writeb %#x <- %#x\n", addr, val);
514 IO_WRITE_PROTO (es1370_writew)
516 ES1370State *s = opaque;
517 addr = es1370_fixup (s, addr);
518 uint32_t shift, mask;
519 struct chan *d = &s->chan[0];
522 case ES1370_REG_CODEC:
523 dolog ("ignored codec write address %#x, data %#x\n",
524 (val >> 8) & 0xff, val & 0xff);
528 case ES1370_REG_CONTROL:
529 case ES1370_REG_CONTROL + 2:
530 shift = (addr != ES1370_REG_CONTROL) << 4;
531 mask = 0xffff << shift;
532 val = (s->ctl & ~mask) | ((val & 0xffff) << shift);
533 es1370_update_voices (s, val, s->sctl);
537 case ES1370_REG_ADC_SCOUNT:
539 case ES1370_REG_DAC2_SCOUNT:
541 case ES1370_REG_DAC1_SCOUNT:
542 d->scount = (d->scount & ~0xffff) | (val & 0xffff);
546 lwarn ("writew %#x <- %#x\n", addr, val);
551 IO_WRITE_PROTO (es1370_writel)
553 ES1370State *s = opaque;
554 struct chan *d = &s->chan[0];
556 addr = es1370_fixup (s, addr);
559 case ES1370_REG_CONTROL:
560 es1370_update_voices (s, val, s->sctl);
564 case ES1370_REG_MEMPAGE:
565 s->mempage = val & 0xf;
568 case ES1370_REG_SERIAL_CONTROL:
569 es1370_maybe_lower_irq (s, val);
570 es1370_update_voices (s, s->ctl, val);
574 case ES1370_REG_ADC_SCOUNT:
576 case ES1370_REG_DAC2_SCOUNT:
578 case ES1370_REG_DAC1_SCOUNT:
579 d->scount = (val & 0xffff) | (d->scount & ~0xffff);
580 ldebug ("chan %d CURR_SAMP_CT %d, SAMP_CT %d\n",
581 d - &s->chan[0], val >> 16, (val & 0xffff));
584 case ES1370_REG_ADC_FRAMEADR:
586 case ES1370_REG_DAC2_FRAMEADR:
588 case ES1370_REG_DAC1_FRAMEADR:
590 ldebug ("chan %d frame address %#x\n", d - &s->chan[0], val);
593 case ES1370_REG_ADC_FRAMECNT:
595 case ES1370_REG_DAC2_FRAMECNT:
597 case ES1370_REG_DAC1_FRAMECNT:
600 ldebug ("chan %d frame count %d, buffer size %d\n",
601 d - &s->chan[0], val >> 16, val & 0xffff);
605 lwarn ("writel %#x <- %#x\n", addr, val);
610 IO_READ_PROTO (es1370_readb)
612 ES1370State *s = opaque;
615 addr = es1370_fixup (s, addr);
618 case 0x1b: /* Legacy */
619 lwarn ("Attempt to read from legacy register\n");
622 case ES1370_REG_MEMPAGE:
625 case ES1370_REG_CONTROL + 0:
626 case ES1370_REG_CONTROL + 1:
627 case ES1370_REG_CONTROL + 2:
628 case ES1370_REG_CONTROL + 3:
629 val = s->ctl >> ((addr - ES1370_REG_CONTROL) << 3);
631 case ES1370_REG_STATUS + 0:
632 case ES1370_REG_STATUS + 1:
633 case ES1370_REG_STATUS + 2:
634 case ES1370_REG_STATUS + 3:
635 val = s->status >> ((addr - ES1370_REG_STATUS) << 3);
639 lwarn ("readb %#x -> %#x\n", addr, val);
645 IO_READ_PROTO (es1370_readw)
647 ES1370State *s = opaque;
648 struct chan *d = &s->chan[0];
651 addr = es1370_fixup (s, addr);
654 case ES1370_REG_ADC_SCOUNT + 2:
656 case ES1370_REG_DAC2_SCOUNT + 2:
658 case ES1370_REG_DAC1_SCOUNT + 2:
659 val = d->scount >> 16;
664 lwarn ("readw %#x -> %#x\n", addr, val);
671 IO_READ_PROTO (es1370_readl)
673 ES1370State *s = opaque;
675 struct chan *d = &s->chan[0];
677 addr = es1370_fixup (s, addr);
680 case ES1370_REG_CONTROL:
683 case ES1370_REG_STATUS:
686 case ES1370_REG_MEMPAGE:
689 case ES1370_REG_CODEC:
692 case ES1370_REG_SERIAL_CONTROL:
696 case ES1370_REG_ADC_SCOUNT:
698 case ES1370_REG_DAC2_SCOUNT:
700 case ES1370_REG_DAC1_SCOUNT:
704 uint32_t curr_count = d->scount >> 16;
705 uint32_t count = d->scount & 0xffff;
707 curr_count <<= d->shift;
709 dolog ("read scount curr %d, total %d\n", curr_count, count);
714 case ES1370_REG_ADC_FRAMECNT:
716 case ES1370_REG_DAC2_FRAMECNT:
718 case ES1370_REG_DAC1_FRAMECNT:
722 uint32_t size = ((d->frame_cnt & 0xffff) + 1) << 2;
723 uint32_t curr = ((d->frame_cnt >> 16) + 1) << 2;
725 dolog ("read framecnt curr %d, size %d %d\n", curr, size,
731 case ES1370_REG_ADC_FRAMEADR:
733 case ES1370_REG_DAC2_FRAMEADR:
735 case ES1370_REG_DAC1_FRAMEADR:
741 lwarn ("readl %#x -> %#x\n", addr, val);
748 static void es1370_transfer_audio (ES1370State *s, struct chan *d, int loop_sel,
751 uint8_t tmpbuf[4096];
752 uint32_t addr = d->frame_addr;
753 int sc = d->scount & 0xffff;
754 int csc = d->scount >> 16;
755 int csc_bytes = (csc + 1) << d->shift;
756 int cnt = d->frame_cnt >> 16;
757 int size = d->frame_cnt & 0xffff;
758 int left = ((size - cnt + 1) << 2) + d->leftover;
760 int temp = audio_MIN (max, audio_MIN (left, csc_bytes));
761 int index = d - &s->chan[0];
763 addr += (cnt << 2) + d->leftover;
765 if (index == ADC_CHANNEL) {
767 int acquired, to_copy;
769 to_copy = audio_MIN ((size_t) temp, sizeof (tmpbuf));
770 acquired = AUD_read (s->adc_voice, tmpbuf, to_copy);
774 cpu_physical_memory_write (addr, tmpbuf, acquired);
778 transfered += acquired;
782 SWVoiceOut *voice = s->dac_voice[index];
787 to_copy = audio_MIN ((size_t) temp, sizeof (tmpbuf));
788 cpu_physical_memory_read (addr, tmpbuf, to_copy);
789 copied = AUD_write (voice, tmpbuf, to_copy);
794 transfered += copied;
798 if (csc_bytes == transfered) {
800 d->scount = sc | (sc << 16);
801 ldebug ("sc = %d, rate = %f\n",
802 (sc + 1) << d->shift,
803 (sc + 1) / (double) 44100);
807 d->scount = sc | (((csc_bytes - transfered - 1) >> d->shift) << 16);
810 cnt += (transfered + d->leftover) >> 2;
812 if (s->sctl & loop_sel) {
813 /* Bah, how stupid is that having a 0 represent true value?
814 i just spent few hours on this shit */
815 lwarn ("whoops non looping mode\n");
820 if ((uint32_t) cnt <= d->frame_cnt)
821 d->frame_cnt |= cnt << 16;
824 d->leftover = (transfered + d->leftover) & 3;
827 static void es1370_run_channel (ES1370State *s, size_t chan, int free_or_avail)
829 uint32_t new_status = s->status;
831 struct chan *d = &s->chan[chan];
832 const struct chan_bits *b = &es1370_chan_bits[chan];
834 if (!(s->ctl & b->ctl_en) || (s->sctl & b->sctl_pause)) {
838 max_bytes = free_or_avail;
839 max_bytes &= ~((1 << d->shift) - 1);
844 es1370_transfer_audio (s, d, b->sctl_loopsel, max_bytes, &irq);
847 if (s->sctl & b->sctl_inten) {
848 new_status |= b->stat_int;
852 if (new_status != s->status) {
853 es1370_update_status (s, new_status);
857 static void es1370_dac1_callback (void *opaque, int free)
859 ES1370State *s = opaque;
861 es1370_run_channel (s, DAC1_CHANNEL, free);
864 static void es1370_dac2_callback (void *opaque, int free)
866 ES1370State *s = opaque;
868 es1370_run_channel (s, DAC2_CHANNEL, free);
871 static void es1370_adc_callback (void *opaque, int avail)
873 ES1370State *s = opaque;
875 es1370_run_channel (s, ADC_CHANNEL, avail);
878 static void es1370_map (PCIDevice *pci_dev, int region_num,
879 uint32_t addr, uint32_t size, int type)
881 PCIES1370State *d = (PCIES1370State *) pci_dev;
882 ES1370State *s = &d->es1370;
888 register_ioport_write (addr, 0x40 * 4, 1, es1370_writeb, s);
889 register_ioport_write (addr, 0x40 * 2, 2, es1370_writew, s);
890 register_ioport_write (addr, 0x40, 4, es1370_writel, s);
892 register_ioport_read (addr, 0x40 * 4, 1, es1370_readb, s);
893 register_ioport_read (addr, 0x40 * 2, 2, es1370_readw, s);
894 register_ioport_read (addr, 0x40, 4, es1370_readl, s);
897 static void es1370_save (QEMUFile *f, void *opaque)
899 ES1370State *s = opaque;
902 for (i = 0; i < NB_CHANNELS; ++i) {
903 struct chan *d = &s->chan[i];
904 qemu_put_be32s (f, &d->shift);
905 qemu_put_be32s (f, &d->leftover);
906 qemu_put_be32s (f, &d->scount);
907 qemu_put_be32s (f, &d->frame_addr);
908 qemu_put_be32s (f, &d->frame_cnt);
910 qemu_put_be32s (f, &s->ctl);
911 qemu_put_be32s (f, &s->status);
912 qemu_put_be32s (f, &s->mempage);
913 qemu_put_be32s (f, &s->codec);
914 qemu_put_be32s (f, &s->sctl);
917 static int es1370_load (QEMUFile *f, void *opaque, int version_id)
920 ES1370State *s = opaque;
926 for (i = 0; i < NB_CHANNELS; ++i) {
927 struct chan *d = &s->chan[i];
928 qemu_get_be32s (f, &d->shift);
929 qemu_get_be32s (f, &d->leftover);
930 qemu_get_be32s (f, &d->scount);
931 qemu_get_be32s (f, &d->frame_addr);
932 qemu_get_be32s (f, &d->frame_cnt);
933 if (i == ADC_CHANNEL) {
935 AUD_close_in (&s->card, s->adc_voice);
940 if (s->dac_voice[i]) {
941 AUD_close_out (&s->card, s->dac_voice[i]);
942 s->dac_voice[i] = NULL;
947 qemu_get_be32s (f, &ctl);
948 qemu_get_be32s (f, &s->status);
949 qemu_get_be32s (f, &s->mempage);
950 qemu_get_be32s (f, &s->codec);
951 qemu_get_be32s (f, &sctl);
955 es1370_update_voices (s, ctl, sctl);
959 static void es1370_on_reset (void *opaque)
961 ES1370State *s = opaque;
965 int es1370_init (PCIBus *bus, AudioState *audio)
972 dolog ("No PCI bus\n");
977 dolog ("No audio state\n");
981 d = (PCIES1370State *) pci_register_device (bus, "ES1370",
982 sizeof (PCIES1370State),
986 fprintf (stderr, "Failed to register PCI device for ES1370\n");
1019 s->pci_dev = &d->dev;
1021 pci_register_io_region (&d->dev, 0, 256, PCI_ADDRESS_SPACE_IO, es1370_map);
1022 register_savevm ("es1370", 0, 1, es1370_save, es1370_load, s);
1023 qemu_register_reset (es1370_on_reset, s);
1025 AUD_register_card (audio, "es1370", &s->card);