2 * QEMU i8255x (PRO100) emulation
4 * Copyright (c) 2006-2007 Stefan Weil
6 * Portions of the code are copies from grub / etherboot eepro100.c
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
23 * Tested features (i82559):
24 * PXE boot (i386) no valid link
25 * Linux networking (i386) ok
33 * Intel 8255x 10/100 Mbps Ethernet Controller Family
34 * Open Source Software Developer Manual
37 #if defined(TARGET_I386)
38 # warning "PXE boot still not working!"
42 #include <stddef.h> /* offsetof */
44 #include "eeprom93xx.h"
46 /* Common declarations for all PCI devices. */
48 #define PCI_VENDOR_ID 0x00 /* 16 bits */
49 #define PCI_DEVICE_ID 0x02 /* 16 bits */
50 #define PCI_COMMAND 0x04 /* 16 bits */
51 #define PCI_STATUS 0x06 /* 16 bits */
53 #define PCI_REVISION_ID 0x08 /* 8 bits */
54 #define PCI_CLASS_CODE 0x0b /* 8 bits */
55 #define PCI_SUBCLASS_CODE 0x0a /* 8 bits */
56 #define PCI_HEADER_TYPE 0x0e /* 8 bits */
58 #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
59 #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits */
60 #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits */
61 #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
62 #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
63 #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
65 #define PCI_CONFIG_8(offset, value) \
66 (pci_conf[offset] = (value))
67 #define PCI_CONFIG_16(offset, value) \
68 (*(uint16_t *)&pci_conf[offset] = cpu_to_le16(value))
69 #define PCI_CONFIG_32(offset, value) \
70 (*(uint32_t *)&pci_conf[offset] = cpu_to_le32(value))
74 /* debug EEPRO100 card */
75 //~ #define DEBUG_EEPRO100
78 #define logout(fmt, args...) fprintf(stderr, "EE100\t%-24s" fmt, __func__, ##args)
80 #define logout(fmt, args...) ((void)0)
83 /* Set flags to 0 to disable debug output. */
86 #define TRACE(flag, command) ((flag) ? (command) : (void)0)
88 #define missing(text) assert(!"feature is missing in this emulation: " text)
90 #define MAX_ETH_FRAME_SIZE 1514
92 /* This driver supports several different devices which are declared here. */
93 #define i82551 0x82551
94 #define i82557B 0x82557b
95 #define i82557C 0x82557c
96 #define i82558B 0x82558b
97 #define i82559C 0x82559c
98 #define i82559ER 0x82559e
99 #define i82562 0x82562
101 #define EEPROM_SIZE 64
103 #define PCI_MEM_SIZE (4 * KiB)
104 #define PCI_IO_SIZE 64
105 #define PCI_FLASH_SIZE (128 * KiB)
107 #define BIT(n) (1 << (n))
108 #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
110 /* The SCB accepts the following controls for the Tx and Rx units: */
111 #define CU_NOP 0x0000 /* No operation. */
112 #define CU_START 0x0010 /* CU start. */
113 #define CU_RESUME 0x0020 /* CU resume. */
114 #define CU_STATSADDR 0x0040 /* Load dump counters address. */
115 #define CU_SHOWSTATS 0x0050 /* Dump statistical counters. */
116 #define CU_CMD_BASE 0x0060 /* Load CU base address. */
117 #define CU_DUMPSTATS 0x0070 /* Dump and reset statistical counters. */
118 #define CU_SRESUME 0x00a0 /* CU static resume. */
120 #define RU_NOP 0x0000
121 #define RX_START 0x0001
122 #define RX_RESUME 0x0002
123 #define RX_ABORT 0x0004
124 #define RX_ADDR_LOAD 0x0006
125 #define RX_RESUMENR 0x0007
126 #define INT_MASK 0x0100
127 #define DRVR_INT 0x0200 /* Driver generated interrupt. */
129 typedef unsigned char bool;
131 /* Offsets to the various registers.
132 All accesses need not be longword aligned. */
133 enum speedo_offsets {
136 SCBCmd = 2, /* Rx/Command Unit command and status. */
138 SCBPointer = 4, /* General purpose pointer. */
139 SCBPort = 8, /* Misc. commands and operands. */
140 SCBflash = 12, SCBeeprom = 14, /* EEPROM and flash memory control. */
141 SCBCtrlMDI = 16, /* MDI interface control. */
142 SCBEarlyRx = 20, /* Early receive byte count. */
145 /* A speedo3 transmit buffer descriptor with two buffers... */
149 uint32_t link; /* void * */
150 uint32_t tx_desc_addr; /* transmit buffer decsriptor array address. */
151 uint16_t tcb_bytes; /* transmit command block byte count (in lower 14 bits */
152 uint8_t tx_threshold; /* transmit threshold */
153 uint8_t tbd_count; /* TBD number */
154 //~ /* This constitutes two "TBD" entries: hdr and data */
155 //~ uint32_t tx_buf_addr0; /* void *, header of frame to be transmitted. */
156 //~ int32_t tx_buf_size0; /* Length of Tx hdr. */
157 //~ uint32_t tx_buf_addr1; /* void *, data to be transmitted. */
158 //~ int32_t tx_buf_size1; /* Length of Tx data. */
161 /* Receive frame descriptor. */
165 uint32_t link; /* struct RxFD * */
166 uint32_t rx_buf_addr; /* void * */
169 char packet[MAX_ETH_FRAME_SIZE + 4];
173 uint32_t tx_good_frames, tx_max_collisions, tx_late_collisions,
174 tx_underruns, tx_lost_crs, tx_deferred, tx_single_collisions,
175 tx_multiple_collisions, tx_total_collisions;
176 uint32_t rx_good_frames, rx_crc_errors, rx_alignment_errors,
177 rx_resource_errors, rx_overrun_errors, rx_cdt_errors,
178 rx_short_frame_errors;
179 uint32_t fc_xmt_pause, fc_rcv_pause, fc_rcv_unsupported;
180 uint16_t xmt_tco_frames, rcv_tco_frames;
199 #if defined(__BIG_ENDIAN_BITFIELD)
221 uint8_t phys[6]; /* mac address */
223 uint8_t mult[8]; /* multicast mask array */
228 uint8_t scb_stat; /* SCB stat/ack byte */
229 uint8_t int_stat; /* PCI interrupt status */
230 uint32_t region[3]; /* PCI region addresses */
232 uint32_t statcounter[19];
235 uint32_t device; /* device variant */
237 /* (cu_base + cu_offset) address the next command block in the command block list. */
238 uint32_t cu_base; /* CU base address */
239 uint32_t cu_offset; /* CU address offset */
240 /* (ru_base + ru_offset) address the RFD in the Receive Frame Area. */
241 uint32_t ru_base; /* RU base address */
242 uint32_t ru_offset; /* RU address offset */
243 uint32_t statsaddr; /* pointer to eepro100_stats_t */
244 eepro100_stats_t statistics; /* statistical counters */
249 /* Configuration bytes. */
250 uint8_t configuration[22];
252 /* Data in mem is always in the byte order of the controller (le). */
253 uint8_t mem[PCI_MEM_SIZE];
256 /* Default values for MDI (PHY) registers */
257 static const uint16_t eepro100_mdi_default[] = {
258 /* MDI Registers 0 - 6, 7 */
259 0x3000, 0x780d, 0x02a8, 0x0154, 0x05e1, 0x0000, 0x0000, 0x0000,
260 /* MDI Registers 8 - 15 */
261 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
262 /* MDI Registers 16 - 31 */
263 0x0003, 0x0000, 0x0001, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
264 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
267 /* Readonly mask for MDI (PHY) registers */
268 static const uint16_t eepro100_mdi_mask[] = {
269 0x0000, 0xffff, 0xffff, 0xffff, 0xc01f, 0xffff, 0xffff, 0x0000,
270 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
271 0x0fff, 0x0000, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff, 0xffff,
272 0xffff, 0xffff, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
275 #define POLYNOMIAL 0x04c11db6
279 static int compute_mcast_idx(const uint8_t * ep)
286 for (i = 0; i < 6; i++) {
288 for (j = 0; j < 8; j++) {
289 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
293 crc = ((crc ^ POLYNOMIAL) | carry);
299 #if defined(DEBUG_EEPRO100)
300 static const char *nic_dump(const uint8_t * buf, unsigned size)
302 static char dump[3 * 16 + 1];
307 p += sprintf(p, " %02x", *buf++);
311 #endif /* DEBUG_EEPRO100 */
314 stat_ack_not_ours = 0x00,
315 stat_ack_sw_gen = 0x04,
317 stat_ack_cu_idle = 0x20,
318 stat_ack_frame_rx = 0x40,
319 stat_ack_cu_cmd_done = 0x80,
320 stat_ack_not_present = 0xFF,
321 stat_ack_rx = (stat_ack_sw_gen | stat_ack_rnr | stat_ack_frame_rx),
322 stat_ack_tx = (stat_ack_cu_idle | stat_ack_cu_cmd_done),
325 static void disable_interrupt(EEPRO100State * s)
328 logout("interrupt disabled\n");
329 qemu_irq_lower(s->pci_dev->irq[0]);
334 static void enable_interrupt(EEPRO100State * s)
337 logout("interrupt enabled\n");
338 qemu_irq_raise(s->pci_dev->irq[0]);
343 static void eepro100_acknowledge(EEPRO100State * s)
345 s->scb_stat &= ~s->mem[SCBAck];
346 s->mem[SCBAck] = s->scb_stat;
347 if (s->scb_stat == 0) {
348 disable_interrupt(s);
352 static void eepro100_interrupt(EEPRO100State * s, uint8_t stat)
354 uint8_t mask = ~s->mem[SCBIntmask];
355 s->mem[SCBAck] |= stat;
356 stat = s->scb_stat = s->mem[SCBAck];
357 stat &= (mask | 0x0f);
358 //~ stat &= (~s->mem[SCBIntmask] | 0x0xf);
359 if (stat && (mask & 0x01)) {
360 /* SCB mask and SCB Bit M do not disable interrupt. */
362 } else if (s->int_stat) {
363 disable_interrupt(s);
367 static void eepro100_cx_interrupt(EEPRO100State * s)
369 /* CU completed action command. */
370 /* Transmit not ok (82557 only, not in emulation). */
371 eepro100_interrupt(s, 0x80);
374 static void eepro100_cna_interrupt(EEPRO100State * s)
376 /* CU left the active state. */
377 eepro100_interrupt(s, 0x20);
380 static void eepro100_fr_interrupt(EEPRO100State * s)
382 /* RU received a complete frame. */
383 eepro100_interrupt(s, 0x40);
387 static void eepro100_rnr_interrupt(EEPRO100State * s)
389 /* RU is not ready. */
390 eepro100_interrupt(s, 0x10);
394 static void eepro100_mdi_interrupt(EEPRO100State * s)
396 /* MDI completed read or write cycle. */
397 eepro100_interrupt(s, 0x08);
400 static void eepro100_swi_interrupt(EEPRO100State * s)
402 /* Software has requested an interrupt. */
403 eepro100_interrupt(s, 0x04);
407 static void eepro100_fcp_interrupt(EEPRO100State * s)
409 /* Flow control pause interrupt (82558 and later). */
410 eepro100_interrupt(s, 0x01);
414 static void pci_reset(EEPRO100State * s)
416 uint32_t device = s->device;
417 uint8_t *pci_conf = s->pci_dev->config;
422 PCI_CONFIG_16(PCI_VENDOR_ID, 0x8086);
424 PCI_CONFIG_16(PCI_DEVICE_ID, 0x1209);
426 PCI_CONFIG_16(PCI_COMMAND, 0x0000);
428 PCI_CONFIG_16(PCI_STATUS, 0x2800);
429 /* PCI Revision ID */
430 PCI_CONFIG_8(PCI_REVISION_ID, 0x08);
432 PCI_CONFIG_8(0x09, 0x00);
433 PCI_CONFIG_8(PCI_SUBCLASS_CODE, 0x00); // ethernet network controller
434 PCI_CONFIG_8(PCI_CLASS_CODE, 0x02); // network controller
435 /* PCI Cache Line Size */
436 /* check cache line size!!! */
437 //~ PCI_CONFIG_8(0x0c, 0x00);
438 /* PCI Latency Timer */
439 PCI_CONFIG_8(0x0d, 0x20); // latency timer = 32 clocks
440 /* PCI Header Type */
441 /* BIST (built-in self test) */
442 #if defined(TARGET_I386)
443 // !!! workaround for buggy bios
444 //~ #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0
447 /* PCI Base Address Registers */
448 /* CSR Memory Mapped Base Address */
449 PCI_CONFIG_32(PCI_BASE_ADDRESS_0,
450 PCI_ADDRESS_SPACE_MEM | PCI_ADDRESS_SPACE_MEM_PREFETCH);
451 /* CSR I/O Mapped Base Address */
452 PCI_CONFIG_32(PCI_BASE_ADDRESS_1, PCI_ADDRESS_SPACE_IO);
454 /* Flash Memory Mapped Base Address */
455 PCI_CONFIG_32(PCI_BASE_ADDRESS_2, 0xfffe0000 | PCI_ADDRESS_SPACE_MEM);
458 /* Expansion ROM Base Address (depends on boot disable!!!) */
459 PCI_CONFIG_32(0x30, 0x00000000);
460 /* Capability Pointer */
461 PCI_CONFIG_8(0x34, 0xdc);
463 PCI_CONFIG_8(0x3d, 1); // interrupt pin 0
465 PCI_CONFIG_8(0x3e, 0x08);
466 /* Maximum Latency */
467 PCI_CONFIG_8(0x3f, 0x18);
468 /* Power Management Capabilities / Next Item Pointer / Capability ID */
469 PCI_CONFIG_32(0xdc, 0x7e210001);
473 //~ PCI_CONFIG_16(PCI_DEVICE_ID, 0x1209);
474 PCI_CONFIG_8(PCI_REVISION_ID, 0x0f);
477 PCI_CONFIG_16(PCI_DEVICE_ID, 0x1229);
478 PCI_CONFIG_8(PCI_REVISION_ID, 0x02);
481 PCI_CONFIG_16(PCI_DEVICE_ID, 0x1229);
482 PCI_CONFIG_8(PCI_REVISION_ID, 0x03);
485 PCI_CONFIG_16(PCI_DEVICE_ID, 0x1229);
486 PCI_CONFIG_16(PCI_STATUS, 0x2810);
487 PCI_CONFIG_8(PCI_REVISION_ID, 0x05);
490 PCI_CONFIG_16(PCI_DEVICE_ID, 0x1229);
491 PCI_CONFIG_16(PCI_STATUS, 0x2810);
492 //~ PCI_CONFIG_8(PCI_REVISION_ID, 0x08);
495 //~ PCI_CONFIG_16(PCI_DEVICE_ID, 0x1209);
496 PCI_CONFIG_16(PCI_STATUS, 0x2810);
497 PCI_CONFIG_8(PCI_REVISION_ID, 0x09);
499 //~ PCI_CONFIG_16(PCI_DEVICE_ID, 0x1029);
500 //~ PCI_CONFIG_16(PCI_DEVICE_ID, 0x1030); /* 82559 InBusiness 10/100 */
502 logout("Device %X is undefined!\n", device);
505 if (device == i82557C || device == i82558B || device == i82559C) {
506 logout("Get device id and revision from EEPROM!!!\n");
510 static void nic_selective_reset(EEPRO100State * s)
513 uint16_t *eeprom_contents = eeprom93xx_data(s->eeprom);
514 //~ eeprom93xx_reset(s->eeprom);
515 memcpy(eeprom_contents, s->macaddr, 6);
516 eeprom_contents[0xa] = 0x4000;
518 for (i = 0; i < EEPROM_SIZE - 1; i++) {
519 sum += eeprom_contents[i];
521 eeprom_contents[EEPROM_SIZE - 1] = 0xbaba - sum;
523 memset(s->mem, 0, sizeof(s->mem));
524 uint32_t val = BIT(21);
525 memcpy(&s->mem[SCBCtrlMDI], &val, sizeof(val));
527 assert(sizeof(s->mdimem) == sizeof(eepro100_mdi_default));
528 memcpy(&s->mdimem[0], &eepro100_mdi_default[0], sizeof(s->mdimem));
531 static void nic_reset(void *opaque)
533 EEPRO100State *s = (EEPRO100State *) opaque;
539 nic_selective_reset(s);
542 #if defined(DEBUG_EEPRO100)
543 static const char *reg[PCI_IO_SIZE / 4] = {
547 "EEPROM/Flash Control",
549 "Receive DMA Byte Count",
550 "Flow control register",
551 "General Status/Control"
554 static char *regname(uint32_t addr)
557 if (addr < PCI_IO_SIZE) {
558 const char *r = reg[addr / 4];
560 sprintf(buf, "%s+%u", r, addr % 4);
562 sprintf(buf, "0x%02x", addr);
565 sprintf(buf, "??? 0x%08x", addr);
569 #endif /* DEBUG_EEPRO100 */
572 static uint16_t eepro100_read_status(EEPRO100State * s)
574 uint16_t val = s->status;
575 logout("val=0x%04x\n", val);
579 static void eepro100_write_status(EEPRO100State * s, uint16_t val)
581 logout("val=0x%04x\n", val);
586 /*****************************************************************************
590 ****************************************************************************/
593 static uint16_t eepro100_read_command(EEPRO100State * s)
595 uint16_t val = 0xffff;
596 //~ logout("val=0x%04x\n", val);
601 /* Commands that can be put in a command list entry. */
606 CmdMulticastList = 3,
608 CmdTDR = 5, /* load microcode */
612 /* And some extra flags: */
613 CmdSuspend = 0x4000, /* Suspend after completion. */
614 CmdIntr = 0x2000, /* Interrupt after completion. */
615 CmdTxFlex = 0x0008, /* Use "Flexible mode" for CmdTx command. */
618 static cu_state_t get_cu_state(EEPRO100State * s)
620 return ((s->mem[SCBStatus] >> 6) & 0x03);
623 static void set_cu_state(EEPRO100State * s, cu_state_t state)
625 s->mem[SCBStatus] = (s->mem[SCBStatus] & 0x3f) + (state << 6);
628 static ru_state_t get_ru_state(EEPRO100State * s)
630 return ((s->mem[SCBStatus] >> 2) & 0x0f);
633 static void set_ru_state(EEPRO100State * s, ru_state_t state)
635 s->mem[SCBStatus] = (s->mem[SCBStatus] & 0xc3) + (state << 2);
638 static void dump_statistics(EEPRO100State * s)
640 /* Dump statistical data. Most data is never changed by the emulation
641 * and always 0, so we first just copy the whole block and then those
642 * values which really matter.
643 * Number of data should check configuration!!!
645 cpu_physical_memory_write(s->statsaddr, (uint8_t *) & s->statistics, 64);
646 stl_phys(s->statsaddr + 0, s->statistics.tx_good_frames);
647 stl_phys(s->statsaddr + 36, s->statistics.rx_good_frames);
648 stl_phys(s->statsaddr + 48, s->statistics.rx_resource_errors);
649 stl_phys(s->statsaddr + 60, s->statistics.rx_short_frame_errors);
650 //~ stw_phys(s->statsaddr + 76, s->statistics.xmt_tco_frames);
651 //~ stw_phys(s->statsaddr + 78, s->statistics.rcv_tco_frames);
652 //~ missing("CU dump statistical counters");
655 static void eepro100_cu_command(EEPRO100State * s, uint8_t val)
664 if (get_cu_state(s) != cu_idle) {
665 /* Intel documentation says that CU must be idle for the CU
666 * start command. Intel driver for Linux also starts the CU
667 * from suspended state. */
668 logout("CU state is %u, should be %u\n", get_cu_state(s), cu_idle);
669 //~ assert(!"wrong CU state");
671 set_cu_state(s, cu_active);
672 s->cu_offset = s->pointer;
674 cb_address = s->cu_base + s->cu_offset;
675 cpu_physical_memory_read(cb_address, (uint8_t *) & tx, sizeof(tx));
676 uint16_t status = le16_to_cpu(tx.status);
677 uint16_t command = le16_to_cpu(tx.command);
679 ("val=0x%02x (cu start), status=0x%04x, command=0x%04x, link=0x%08x\n",
680 val, status, command, tx.link);
681 bool bit_el = ((command & 0x8000) != 0);
682 bool bit_s = ((command & 0x4000) != 0);
683 bool bit_i = ((command & 0x2000) != 0);
684 bool bit_nc = ((command & 0x0010) != 0);
685 //~ bool bit_sf = ((command & 0x0008) != 0);
686 uint16_t cmd = command & 0x0007;
687 s->cu_offset = le32_to_cpu(tx.link);
693 cpu_physical_memory_read(cb_address + 8, &s->macaddr[0], 6);
694 logout("macaddr: %s\n", nic_dump(&s->macaddr[0], 6));
697 cpu_physical_memory_read(cb_address + 8, &s->configuration[0],
698 sizeof(s->configuration));
699 logout("configuration: %s\n", nic_dump(&s->configuration[0], 16));
701 case CmdMulticastList:
702 //~ missing("multicast list");
706 uint32_t tbd_array = le32_to_cpu(tx.tx_desc_addr);
707 uint16_t tcb_bytes = (le16_to_cpu(tx.tcb_bytes) & 0x3fff);
709 ("transmit, TBD array address 0x%08x, TCB byte count 0x%04x, TBD count %u\n",
710 tbd_array, tcb_bytes, tx.tbd_count);
713 assert(tcb_bytes <= 2600);
714 /* Next assertion fails for local configuration. */
715 //~ assert((tcb_bytes > 0) || (tbd_array != 0xffffffff));
716 if (!((tcb_bytes > 0) || (tbd_array != 0xffffffff))) {
718 ("illegal values of TBD array address and TCB byte count!\n");
720 uint8_t buf[MAX_ETH_FRAME_SIZE + 4];
722 uint32_t tbd_address = cb_address + 0x10;
723 assert(tcb_bytes <= sizeof(buf));
724 while (size < tcb_bytes) {
725 uint32_t tx_buffer_address = ldl_phys(tbd_address);
726 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
727 //~ uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
730 ("TBD (simplified mode): buffer address 0x%08x, size 0x%04x\n",
731 tx_buffer_address, tx_buffer_size);
732 cpu_physical_memory_read(tx_buffer_address, &buf[size],
734 size += tx_buffer_size;
736 if (tbd_array == 0xffffffff) {
737 /* Simplified mode. Was already handled by code above. */
740 uint8_t tbd_count = 0;
741 if (!(s->configuration[6] & BIT(4))) {
743 assert(tcb_bytes == 0);
744 for (; tbd_count < 2; tbd_count++) {
745 uint32_t tx_buffer_address = ldl_phys(tbd_address);
746 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
747 uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
750 ("TBD (extended mode): buffer address 0x%08x, size 0x%04x\n",
751 tx_buffer_address, tx_buffer_size);
752 cpu_physical_memory_read(tx_buffer_address, &buf[size],
754 size += tx_buffer_size;
755 if (tx_buffer_el & 1) {
760 tbd_address = tbd_array;
761 for (; tbd_count < tx.tbd_count; tbd_count++) {
762 uint32_t tx_buffer_address = ldl_phys(tbd_address);
763 uint16_t tx_buffer_size = lduw_phys(tbd_address + 4);
764 uint16_t tx_buffer_el = lduw_phys(tbd_address + 6);
767 ("TBD (flexible mode): buffer address 0x%08x, size 0x%04x\n",
768 tx_buffer_address, tx_buffer_size);
769 cpu_physical_memory_read(tx_buffer_address, &buf[size],
771 size += tx_buffer_size;
772 if (tx_buffer_el & 1) {
777 qemu_send_packet(s->vc, buf, size);
778 s->statistics.tx_good_frames++;
779 /* Transmit with bad status would raise an CX/TNO interrupt.
780 * (82557 only). Emulation never has bad status. */
781 //~ eepro100_cx_interrupt(s);
784 logout("load microcode\n");
785 /* Starting with offset 8, the command contains
786 * 64 dwords microcode which we just ignore here. */
789 missing("undefined command");
791 /* Write new status (success). */
792 stw_phys(cb_address, status | 0x8000 | 0x2000);
794 /* CU completed action. */
795 eepro100_cx_interrupt(s);
798 /* CU becomes idle. */
799 set_cu_state(s, cu_idle);
800 eepro100_cna_interrupt(s);
802 /* CU becomes suspended. */
803 set_cu_state(s, cu_suspended);
804 eepro100_cna_interrupt(s);
806 /* More entries in list. */
807 logout("CU list with at least one more entry\n");
810 logout("CU list empty\n");
811 /* List is empty. Now CU is idle or suspended. */
814 if (get_cu_state(s) != cu_suspended) {
815 logout("bad CU resume from CU state %u\n", get_cu_state(s));
816 /* Workaround for bad Linux eepro100 driver which resumes
817 * from idle state. */
818 //~ missing("cu resume");
819 set_cu_state(s, cu_suspended);
821 if (get_cu_state(s) == cu_suspended) {
822 logout("CU resuming\n");
823 set_cu_state(s, cu_active);
828 /* Load dump counters address. */
829 s->statsaddr = s->pointer;
830 logout("val=0x%02x (status address)\n", val);
833 /* Dump statistical counters. */
838 logout("val=0x%02x (CU base address)\n", val);
839 s->cu_base = s->pointer;
842 /* Dump and reset statistical counters. */
844 memset(&s->statistics, 0, sizeof(s->statistics));
847 /* CU static resume. */
848 missing("CU static resume");
851 missing("Undefined CU command");
855 static void eepro100_ru_command(EEPRO100State * s, uint8_t val)
863 if (get_ru_state(s) != ru_idle) {
864 logout("RU state is %u, should be %u\n", get_ru_state(s), ru_idle);
865 //~ assert(!"wrong RU state");
867 set_ru_state(s, ru_ready);
868 s->ru_offset = s->pointer;
869 logout("val=0x%02x (rx start)\n", val);
873 if (get_ru_state(s) != ru_suspended) {
874 logout("RU state is %u, should be %u\n", get_ru_state(s),
876 //~ assert(!"wrong RU state");
878 set_ru_state(s, ru_ready);
882 logout("val=0x%02x (RU base address)\n", val);
883 s->ru_base = s->pointer;
886 logout("val=0x%02x (undefined RU command)\n", val);
887 missing("Undefined SU command");
891 static void eepro100_write_command(EEPRO100State * s, uint8_t val)
893 eepro100_ru_command(s, val & 0x0f);
894 eepro100_cu_command(s, val & 0xf0);
896 logout("val=0x%02x\n", val);
898 /* Clear command byte after command was accepted. */
902 /*****************************************************************************
906 ****************************************************************************/
908 #define EEPROM_CS 0x02
909 #define EEPROM_SK 0x01
910 #define EEPROM_DI 0x04
911 #define EEPROM_DO 0x08
913 static uint16_t eepro100_read_eeprom(EEPRO100State * s)
916 memcpy(&val, &s->mem[SCBeeprom], sizeof(val));
917 if (eeprom93xx_read(s->eeprom)) {
925 static void eepro100_write_eeprom(eeprom_t * eeprom, uint8_t val)
927 logout("write val=0x%02x\n", val);
929 /* mask unwriteable bits */
930 //~ val = SET_MASKED(val, 0x31, eeprom->value);
932 int eecs = ((val & EEPROM_CS) != 0);
933 int eesk = ((val & EEPROM_SK) != 0);
934 int eedi = ((val & EEPROM_DI) != 0);
935 eeprom93xx_write(eeprom, eecs, eesk, eedi);
938 static void eepro100_write_pointer(EEPRO100State * s, uint32_t val)
940 s->pointer = le32_to_cpu(val);
941 logout("val=0x%08x\n", val);
944 /*****************************************************************************
948 ****************************************************************************/
950 #if defined(DEBUG_EEPRO100)
951 static const char *mdi_op_name[] = {
958 static const char *mdi_reg_name[] = {
961 "PHY Identification (Word 1)",
962 "PHY Identification (Word 2)",
963 "Auto-Negotiation Advertisement",
964 "Auto-Negotiation Link Partner Ability",
965 "Auto-Negotiation Expansion"
967 #endif /* DEBUG_EEPRO100 */
969 static uint32_t eepro100_read_mdi(EEPRO100State * s)
972 memcpy(&val, &s->mem[0x10], sizeof(val));
974 #ifdef DEBUG_EEPRO100
975 uint8_t raiseint = (val & BIT(29)) >> 29;
976 uint8_t opcode = (val & BITS(27, 26)) >> 26;
977 uint8_t phy = (val & BITS(25, 21)) >> 21;
978 uint8_t reg = (val & BITS(20, 16)) >> 16;
979 uint16_t data = (val & BITS(15, 0));
981 /* Emulation takes no time to finish MDI transaction. */
983 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
984 val, raiseint, mdi_op_name[opcode], phy,
985 mdi_reg_name[reg], data));
989 //~ #define BITS(val, upper, lower) (val & ???)
990 static void eepro100_write_mdi(EEPRO100State * s, uint32_t val)
992 uint8_t raiseint = (val & BIT(29)) >> 29;
993 uint8_t opcode = (val & BITS(27, 26)) >> 26;
994 uint8_t phy = (val & BITS(25, 21)) >> 21;
995 uint8_t reg = (val & BITS(20, 16)) >> 16;
996 uint16_t data = (val & BITS(15, 0));
998 /* Unsupported PHY address. */
999 //~ logout("phy must be 1 but is %u\n", phy);
1001 } else if (opcode != 1 && opcode != 2) {
1002 /* Unsupported opcode. */
1003 logout("opcode must be 1 or 2 but is %u\n", opcode);
1005 } else if (reg > 6) {
1006 /* Unsupported register. */
1007 logout("register must be 0...6 but is %u\n", reg);
1010 TRACE(MDI, logout("val=0x%08x (int=%u, %s, phy=%u, %s, data=0x%04x\n",
1011 val, raiseint, mdi_op_name[opcode], phy,
1012 mdi_reg_name[reg], data));
1016 case 0: /* Control Register */
1017 if (data & 0x8000) {
1018 /* Reset status and control registers to default. */
1019 s->mdimem[0] = eepro100_mdi_default[0];
1020 s->mdimem[1] = eepro100_mdi_default[1];
1021 data = s->mdimem[reg];
1023 /* Restart Auto Configuration = Normal Operation */
1027 case 1: /* Status Register */
1028 missing("not writable");
1029 data = s->mdimem[reg];
1031 case 2: /* PHY Identification Register (Word 1) */
1032 case 3: /* PHY Identification Register (Word 2) */
1033 missing("not implemented");
1035 case 4: /* Auto-Negotiation Advertisement Register */
1036 case 5: /* Auto-Negotiation Link Partner Ability Register */
1038 case 6: /* Auto-Negotiation Expansion Register */
1040 missing("not implemented");
1042 s->mdimem[reg] = data;
1043 } else if (opcode == 2) {
1046 case 0: /* Control Register */
1047 if (data & 0x8000) {
1048 /* Reset status and control registers to default. */
1049 s->mdimem[0] = eepro100_mdi_default[0];
1050 s->mdimem[1] = eepro100_mdi_default[1];
1053 case 1: /* Status Register */
1054 s->mdimem[reg] |= 0x0020;
1056 case 2: /* PHY Identification Register (Word 1) */
1057 case 3: /* PHY Identification Register (Word 2) */
1058 case 4: /* Auto-Negotiation Advertisement Register */
1060 case 5: /* Auto-Negotiation Link Partner Ability Register */
1061 s->mdimem[reg] = 0x41fe;
1063 case 6: /* Auto-Negotiation Expansion Register */
1064 s->mdimem[reg] = 0x0001;
1067 data = s->mdimem[reg];
1069 /* Emulation takes no time to finish MDI transaction.
1070 * Set MDI bit in SCB status register. */
1071 s->mem[SCBAck] |= 0x08;
1074 eepro100_mdi_interrupt(s);
1077 val = (val & 0xffff0000) + data;
1078 memcpy(&s->mem[0x10], &val, sizeof(val));
1081 /*****************************************************************************
1085 ****************************************************************************/
1087 #define PORT_SOFTWARE_RESET 0
1088 #define PORT_SELFTEST 1
1089 #define PORT_SELECTIVE_RESET 2
1091 #define PORT_SELECTION_MASK 3
1094 uint32_t st_sign; /* Self Test Signature */
1095 uint32_t st_result; /* Self Test Results */
1096 } eepro100_selftest_t;
1098 static uint32_t eepro100_read_port(EEPRO100State * s)
1103 static void eepro100_write_port(EEPRO100State * s, uint32_t val)
1105 val = le32_to_cpu(val);
1106 uint32_t address = (val & ~PORT_SELECTION_MASK);
1107 uint8_t selection = (val & PORT_SELECTION_MASK);
1108 switch (selection) {
1109 case PORT_SOFTWARE_RESET:
1113 logout("selftest address=0x%08x\n", address);
1114 eepro100_selftest_t data;
1115 cpu_physical_memory_read(address, (uint8_t *) & data, sizeof(data));
1116 data.st_sign = 0xffffffff;
1118 cpu_physical_memory_write(address, (uint8_t *) & data, sizeof(data));
1120 case PORT_SELECTIVE_RESET:
1121 logout("selective reset, selftest address=0x%08x\n", address);
1122 nic_selective_reset(s);
1125 logout("val=0x%08x\n", val);
1126 missing("unknown port selection");
1130 /*****************************************************************************
1132 * General hardware emulation.
1134 ****************************************************************************/
1136 static uint8_t eepro100_read1(EEPRO100State * s, uint32_t addr)
1139 if (addr <= sizeof(s->mem) - sizeof(val)) {
1140 memcpy(&val, &s->mem[addr], sizeof(val));
1145 //~ val = eepro100_read_status(s);
1146 logout("addr=%s val=0x%02x\n", regname(addr), val);
1149 //~ val = eepro100_read_status(s);
1150 logout("addr=%s val=0x%02x\n", regname(addr), val);
1153 logout("addr=%s val=0x%02x\n", regname(addr), val);
1154 //~ val = eepro100_read_command(s);
1157 logout("addr=%s val=0x%02x\n", regname(addr), val);
1160 logout("addr=%s val=0x%02x\n", regname(addr), val);
1163 val = eepro100_read_eeprom(s);
1165 case 0x1b: /* PMDR (power management driver register) */
1167 logout("addr=%s val=0x%02x\n", regname(addr), val);
1169 case 0x1d: /* general status register */
1170 /* 100 Mbps full duplex, valid link */
1172 logout("addr=General Status val=%02x\n", val);
1175 logout("addr=%s val=0x%02x\n", regname(addr), val);
1176 missing("unknown byte read");
1181 static uint16_t eepro100_read2(EEPRO100State * s, uint32_t addr)
1184 if (addr <= sizeof(s->mem) - sizeof(val)) {
1185 memcpy(&val, &s->mem[addr], sizeof(val));
1188 logout("addr=%s val=0x%04x\n", regname(addr), val);
1192 //~ val = eepro100_read_status(s);
1195 val = eepro100_read_eeprom(s);
1198 logout("addr=%s val=0x%04x\n", regname(addr), val);
1199 missing("unknown word read");
1204 static uint32_t eepro100_read4(EEPRO100State * s, uint32_t addr)
1207 if (addr <= sizeof(s->mem) - sizeof(val)) {
1208 memcpy(&val, &s->mem[addr], sizeof(val));
1213 //~ val = eepro100_read_status(s);
1214 logout("addr=%s val=0x%08x\n", regname(addr), val);
1217 //~ val = eepro100_read_pointer(s);
1218 logout("addr=%s val=0x%08x\n", regname(addr), val);
1221 val = eepro100_read_port(s);
1222 logout("addr=%s val=0x%08x\n", regname(addr), val);
1225 val = eepro100_read_mdi(s);
1228 logout("addr=%s val=0x%08x\n", regname(addr), val);
1229 missing("unknown longword read");
1234 static void eepro100_write1(EEPRO100State * s, uint32_t addr, uint8_t val)
1236 if (addr <= sizeof(s->mem) - sizeof(val)) {
1237 memcpy(&s->mem[addr], &val, sizeof(val));
1240 logout("addr=%s val=0x%02x\n", regname(addr), val);
1244 //~ eepro100_write_status(s, val);
1247 eepro100_acknowledge(s);
1250 eepro100_write_command(s, val);
1254 eepro100_swi_interrupt(s);
1256 eepro100_interrupt(s, 0);
1259 logout("addr=%s val=0x%02x\n", regname(addr), val);
1262 eepro100_write_eeprom(s->eeprom, val);
1265 logout("addr=%s val=0x%02x\n", regname(addr), val);
1266 missing("unknown byte write");
1270 static void eepro100_write2(EEPRO100State * s, uint32_t addr, uint16_t val)
1272 if (addr <= sizeof(s->mem) - sizeof(val)) {
1273 memcpy(&s->mem[addr], &val, sizeof(val));
1276 logout("addr=%s val=0x%04x\n", regname(addr), val);
1280 //~ eepro100_write_status(s, val);
1281 eepro100_acknowledge(s);
1284 eepro100_write_command(s, val);
1285 eepro100_write1(s, SCBIntmask, val >> 8);
1288 eepro100_write_eeprom(s->eeprom, val);
1291 logout("addr=%s val=0x%04x\n", regname(addr), val);
1292 missing("unknown word write");
1296 static void eepro100_write4(EEPRO100State * s, uint32_t addr, uint32_t val)
1298 if (addr <= sizeof(s->mem) - sizeof(val)) {
1299 memcpy(&s->mem[addr], &val, sizeof(val));
1304 eepro100_write_pointer(s, val);
1307 logout("addr=%s val=0x%08x\n", regname(addr), val);
1308 eepro100_write_port(s, val);
1311 eepro100_write_mdi(s, val);
1314 logout("addr=%s val=0x%08x\n", regname(addr), val);
1315 missing("unknown longword write");
1319 static uint32_t ioport_read1(void *opaque, uint32_t addr)
1321 EEPRO100State *s = opaque;
1322 //~ logout("addr=%s\n", regname(addr));
1323 return eepro100_read1(s, addr - s->region[1]);
1326 static uint32_t ioport_read2(void *opaque, uint32_t addr)
1328 EEPRO100State *s = opaque;
1329 return eepro100_read2(s, addr - s->region[1]);
1332 static uint32_t ioport_read4(void *opaque, uint32_t addr)
1334 EEPRO100State *s = opaque;
1335 return eepro100_read4(s, addr - s->region[1]);
1338 static void ioport_write1(void *opaque, uint32_t addr, uint32_t val)
1340 EEPRO100State *s = opaque;
1341 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1342 eepro100_write1(s, addr - s->region[1], val);
1345 static void ioport_write2(void *opaque, uint32_t addr, uint32_t val)
1347 EEPRO100State *s = opaque;
1348 eepro100_write2(s, addr - s->region[1], val);
1351 static void ioport_write4(void *opaque, uint32_t addr, uint32_t val)
1353 EEPRO100State *s = opaque;
1354 eepro100_write4(s, addr - s->region[1], val);
1357 /***********************************************************/
1358 /* PCI EEPRO100 definitions */
1360 typedef struct PCIEEPRO100State {
1362 EEPRO100State eepro100;
1365 static void pci_map(PCIDevice * pci_dev, int region_num,
1366 uint32_t addr, uint32_t size, int type)
1368 PCIEEPRO100State *d = (PCIEEPRO100State *) pci_dev;
1369 EEPRO100State *s = &d->eepro100;
1371 logout("region %d, addr=0x%08x, size=0x%08x, type=%d\n",
1372 region_num, addr, size, type);
1374 assert(region_num == 1);
1375 register_ioport_write(addr, size, 1, ioport_write1, s);
1376 register_ioport_read(addr, size, 1, ioport_read1, s);
1377 register_ioport_write(addr, size, 2, ioport_write2, s);
1378 register_ioport_read(addr, size, 2, ioport_read2, s);
1379 register_ioport_write(addr, size, 4, ioport_write4, s);
1380 register_ioport_read(addr, size, 4, ioport_read4, s);
1382 s->region[region_num] = addr;
1385 static void pci_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1387 EEPRO100State *s = opaque;
1388 addr -= s->region[0];
1389 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1390 eepro100_write1(s, addr, val);
1393 static void pci_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1395 EEPRO100State *s = opaque;
1396 addr -= s->region[0];
1397 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1398 eepro100_write2(s, addr, val);
1401 static void pci_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1403 EEPRO100State *s = opaque;
1404 addr -= s->region[0];
1405 //~ logout("addr=%s val=0x%02x\n", regname(addr), val);
1406 eepro100_write4(s, addr, val);
1409 static uint32_t pci_mmio_readb(void *opaque, target_phys_addr_t addr)
1411 EEPRO100State *s = opaque;
1412 addr -= s->region[0];
1413 //~ logout("addr=%s\n", regname(addr));
1414 return eepro100_read1(s, addr);
1417 static uint32_t pci_mmio_readw(void *opaque, target_phys_addr_t addr)
1419 EEPRO100State *s = opaque;
1420 addr -= s->region[0];
1421 //~ logout("addr=%s\n", regname(addr));
1422 return eepro100_read2(s, addr);
1425 static uint32_t pci_mmio_readl(void *opaque, target_phys_addr_t addr)
1427 EEPRO100State *s = opaque;
1428 addr -= s->region[0];
1429 //~ logout("addr=%s\n", regname(addr));
1430 return eepro100_read4(s, addr);
1433 static CPUWriteMemoryFunc *pci_mmio_write[] = {
1439 static CPUReadMemoryFunc *pci_mmio_read[] = {
1445 static void pci_mmio_map(PCIDevice * pci_dev, int region_num,
1446 uint32_t addr, uint32_t size, int type)
1448 PCIEEPRO100State *d = (PCIEEPRO100State *) pci_dev;
1450 logout("region %d, addr=0x%08x, size=0x%08x, type=%d\n",
1451 region_num, addr, size, type);
1453 if (region_num == 0) {
1454 /* Map control / status registers. */
1455 cpu_register_physical_memory(addr, size, d->eepro100.mmio_index);
1456 d->eepro100.region[region_num] = addr;
1460 static int nic_can_receive(void *opaque)
1462 EEPRO100State *s = opaque;
1464 return get_ru_state(s) == ru_ready;
1465 //~ return !eepro100_buffer_full(s);
1468 #define MIN_BUF_SIZE 60
1470 static void nic_receive(void *opaque, const uint8_t * buf, int size)
1473 * - Magic packets should set bit 30 in power management driver register.
1474 * - Interesting packets should set bit 29 in power management driver register.
1476 EEPRO100State *s = opaque;
1477 uint16_t rfd_status = 0xa000;
1478 static const uint8_t broadcast_macaddr[6] =
1479 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1481 /* TODO: check multiple IA bit. */
1482 assert(!(s->configuration[20] & BIT(6)));
1484 if (s->configuration[8] & 0x80) {
1485 /* CSMA is disabled. */
1486 logout("%p received while CSMA is disabled\n", s);
1488 } else if (size < 64 && (s->configuration[7] & 1)) {
1489 /* Short frame and configuration byte 7/0 (discard short receive) set:
1490 * Short frame is discarded */
1491 logout("%p received short frame (%d byte)\n", s, size);
1492 s->statistics.rx_short_frame_errors++;
1494 } else if ((size > MAX_ETH_FRAME_SIZE + 4) && !(s->configuration[18] & 8)) {
1495 /* Long frame and configuration byte 18/3 (long receive ok) not set:
1496 * Long frames are discarded. */
1497 logout("%p received long frame (%d byte), ignored\n", s, size);
1499 } else if (memcmp(buf, s->macaddr, 6) == 0) { // !!!
1500 /* Frame matches individual address. */
1501 /* TODO: check configuration byte 15/4 (ignore U/L). */
1502 logout("%p received frame for me, len=%d\n", s, size);
1503 } else if (memcmp(buf, broadcast_macaddr, 6) == 0) {
1504 /* Broadcast frame. */
1505 logout("%p received broadcast, len=%d\n", s, size);
1506 rfd_status |= 0x0002;
1507 } else if (buf[0] & 0x01) { // !!!
1508 /* Multicast frame. */
1509 logout("%p received multicast, len=%d\n", s, size);
1510 /* TODO: check multicast all bit. */
1511 assert(!(s->configuration[21] & BIT(3)));
1512 int mcast_idx = compute_mcast_idx(buf);
1513 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7)))) {
1516 rfd_status |= 0x0002;
1517 } else if (s->configuration[15] & 1) {
1518 /* Promiscuous: receive all. */
1519 logout("%p received frame in promiscuous mode, len=%d\n", s, size);
1520 rfd_status |= 0x0004;
1522 logout("%p received frame, ignored, len=%d,%s\n", s, size,
1523 nic_dump(buf, size));
1527 if (get_ru_state(s) != ru_ready) {
1528 /* No ressources available. */
1529 logout("no ressources, state=%u\n", get_ru_state(s));
1530 s->statistics.rx_resource_errors++;
1531 //~ assert(!"no ressources");
1535 //~ $3 = {status = 0x0, command = 0xc000, link = 0x2d220, rx_buf_addr = 0x207dc, count = 0x0, size = 0x5f8, packet = {0x0 <repeats 1518 times>}}
1537 cpu_physical_memory_read(s->ru_base + s->ru_offset, (uint8_t *) & rx,
1538 offsetof(eepro100_rx_t, packet));
1539 uint16_t rfd_command = le16_to_cpu(rx.command);
1540 uint16_t rfd_size = le16_to_cpu(rx.size);
1541 assert(size <= rfd_size);
1543 rfd_status |= 0x0080;
1545 logout("command 0x%04x, link 0x%08x, addr 0x%08x, size %u\n", rfd_command,
1546 rx.link, rx.rx_buf_addr, rfd_size);
1547 stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, status),
1549 stw_phys(s->ru_base + s->ru_offset + offsetof(eepro100_rx_t, count), size);
1550 /* Early receive interrupt not supported. */
1551 //~ eepro100_er_interrupt(s);
1552 /* Receive CRC Transfer not supported. */
1553 assert(!(s->configuration[18] & 4));
1554 /* TODO: check stripping enable bit. */
1555 //~ assert(!(s->configuration[17] & 1));
1556 cpu_physical_memory_write(s->ru_base + s->ru_offset +
1557 offsetof(eepro100_rx_t, packet), buf, size);
1558 s->statistics.rx_good_frames++;
1559 eepro100_fr_interrupt(s);
1560 s->ru_offset = le32_to_cpu(rx.link);
1561 if (rfd_command & 0x8000) {
1562 /* EL bit is set, so this was the last frame. */
1565 if (rfd_command & 0x4000) {
1567 set_ru_state(s, ru_suspended);
1571 static int nic_load(QEMUFile * f, void *opaque, int version_id)
1573 EEPRO100State *s = (EEPRO100State *) opaque;
1576 missing("NIC load");
1581 if (s->pci_dev && version_id >= 3) {
1582 ret = pci_device_load(s->pci_dev, f);
1587 if (version_id >= 2) {
1588 qemu_get_8s(f, &s->rxcr);
1593 qemu_get_8s(f, &s->cmd);
1594 qemu_get_be32s(f, &s->start);
1595 qemu_get_be32s(f, &s->stop);
1596 qemu_get_8s(f, &s->boundary);
1597 qemu_get_8s(f, &s->tsr);
1598 qemu_get_8s(f, &s->tpsr);
1599 qemu_get_be16s(f, &s->tcnt);
1600 qemu_get_be16s(f, &s->rcnt);
1601 qemu_get_be32s(f, &s->rsar);
1602 qemu_get_8s(f, &s->rsr);
1603 qemu_get_8s(f, &s->isr);
1604 qemu_get_8s(f, &s->dcfg);
1605 qemu_get_8s(f, &s->imr);
1606 qemu_get_buffer(f, s->phys, 6);
1607 qemu_get_8s(f, &s->curpag);
1608 qemu_get_buffer(f, s->mult, 8);
1609 qemu_get_buffer(f, s->mem, sizeof(s->mem));
1614 static void nic_save(QEMUFile * f, void *opaque)
1616 EEPRO100State *s = (EEPRO100State *) opaque;
1618 missing("NIC save");
1621 pci_device_save(s->pci_dev, f);
1623 qemu_put_8s(f, &s->rxcr);
1625 qemu_put_8s(f, &s->cmd);
1626 qemu_put_be32s(f, &s->start);
1627 qemu_put_be32s(f, &s->stop);
1628 qemu_put_8s(f, &s->boundary);
1629 qemu_put_8s(f, &s->tsr);
1630 qemu_put_8s(f, &s->tpsr);
1631 qemu_put_be16s(f, &s->tcnt);
1632 qemu_put_be16s(f, &s->rcnt);
1633 qemu_put_be32s(f, &s->rsar);
1634 qemu_put_8s(f, &s->rsr);
1635 qemu_put_8s(f, &s->isr);
1636 qemu_put_8s(f, &s->dcfg);
1637 qemu_put_8s(f, &s->imr);
1638 qemu_put_buffer(f, s->phys, 6);
1639 qemu_put_8s(f, &s->curpag);
1640 qemu_put_buffer(f, s->mult, 8);
1641 qemu_put_buffer(f, s->mem, sizeof(s->mem));
1644 static void nic_init(PCIBus * bus, NICInfo * nd,
1645 const char *name, uint32_t device)
1647 PCIEEPRO100State *d;
1652 d = (PCIEEPRO100State *) pci_register_device(bus, name,
1653 sizeof(PCIEEPRO100State), -1,
1658 s->pci_dev = &d->dev;
1662 /* Add 64 * 2 EEPROM. i82557 and i82558 support a 64 word EEPROM,
1663 * i82559 and later support 64 or 256 word EEPROM. */
1664 s->eeprom = eeprom93xx_new(EEPROM_SIZE);
1666 /* Handler for memory-mapped I/O */
1667 d->eepro100.mmio_index =
1668 cpu_register_io_memory(0, pci_mmio_read, pci_mmio_write, s);
1670 pci_register_io_region(&d->dev, 0, PCI_MEM_SIZE,
1671 PCI_ADDRESS_SPACE_MEM |
1672 PCI_ADDRESS_SPACE_MEM_PREFETCH, pci_mmio_map);
1673 pci_register_io_region(&d->dev, 1, PCI_IO_SIZE, PCI_ADDRESS_SPACE_IO,
1675 pci_register_io_region(&d->dev, 2, PCI_FLASH_SIZE, PCI_ADDRESS_SPACE_MEM,
1678 memcpy(s->macaddr, nd->macaddr, 6);
1679 logout("macaddr: %s\n", nic_dump(&s->macaddr[0], 6));
1680 assert(s->region[1] == 0);
1684 s->vc = qemu_new_vlan_client(nd->vlan, nic_receive, nic_can_receive, s);
1686 snprintf(s->vc->info_str, sizeof(s->vc->info_str),
1687 "eepro100 pci macaddr=%02x:%02x:%02x:%02x:%02x:%02x",
1690 s->macaddr[2], s->macaddr[3], s->macaddr[4], s->macaddr[5]);
1692 qemu_register_reset(nic_reset, s);
1694 /* XXX: instance number ? */
1695 register_savevm(name, 0, 3, nic_save, nic_load, s);
1698 void pci_i82551_init(PCIBus * bus, NICInfo * nd, int devfn)
1700 nic_init(bus, nd, "i82551", i82551);
1701 //~ uint8_t *pci_conf = d->dev.config;
1704 void pci_i82557b_init(PCIBus * bus, NICInfo * nd, int devfn)
1706 nic_init(bus, nd, "i82557b", i82557B);
1709 void pci_i82559er_init(PCIBus * bus, NICInfo * nd, int devfn)
1711 nic_init(bus, nd, "i82559er", i82559ER);