4 * Copyright (c) 2003 Vassili Karpov (malc)
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 #define log(...) fprintf (stderr, "dma: " __VA_ARGS__)
28 #define lwarn(...) fprintf (stderr, "dma: " __VA_ARGS__)
29 #define linfo(...) fprintf (stderr, "dma: " __VA_ARGS__)
30 #define ldebug(...) fprintf (stderr, "dma: " __VA_ARGS__)
37 #define LENOFA(a) ((int) (sizeof(a)/sizeof(a[0])))
46 DMA_transfer_handler transfer_handler;
53 static struct dma_cont {
59 struct dma_regs regs[4];
63 CMD_MEMORY_TO_MEMORY = 0x01,
64 CMD_FIXED_ADDRESS = 0x02,
65 CMD_BLOCK_CONTROLLER = 0x04,
66 CMD_COMPRESSED_TIME = 0x08,
67 CMD_CYCLIC_PRIORITY = 0x10,
68 CMD_EXTENDED_WRITE = 0x20,
71 CMD_NOT_SUPPORTED = CMD_MEMORY_TO_MEMORY | CMD_FIXED_ADDRESS
72 | CMD_COMPRESSED_TIME | CMD_CYCLIC_PRIORITY | CMD_EXTENDED_WRITE
73 | CMD_LOW_DREQ | CMD_LOW_DACK
77 static int channels[8] = {-1, 2, 3, 1, -1, -1, -1, 0};
79 static void write_page (void *opaque, uint32_t nport, uint32_t data)
81 struct dma_cont *d = opaque;
84 ichan = channels[nport & 7];
87 log ("invalid channel %#x %#x\n", nport, data);
90 d->regs[ichan].page = data;
93 static uint32_t read_page (void *opaque, uint32_t nport)
95 struct dma_cont *d = opaque;
98 ichan = channels[nport & 7];
101 log ("invalid channel read %#x\n", nport);
104 return d->regs[ichan].page;
107 static inline void init_chan (struct dma_cont *d, int ichan)
112 r->now[ADDR] = r->base[0] << d->dshift;
116 static inline int getff (struct dma_cont *d)
125 static uint32_t read_chan (void *opaque, uint32_t nport)
127 struct dma_cont *d = opaque;
128 int ichan, nreg, iport, ff, val;
131 iport = (nport >> d->dshift) & 0x0f;
138 val = (r->base[COUNT] << d->dshift) - r->now[COUNT];
140 val = r->now[ADDR] + r->now[COUNT];
142 return (val >> (d->dshift + (ff << 3))) & 0xff;
145 static void write_chan (void *opaque, uint32_t nport, uint32_t data)
147 struct dma_cont *d = opaque;
148 int iport, ichan, nreg;
151 iport = (nport >> d->dshift) & 0x0f;
156 r->base[nreg] = (r->base[nreg] & 0xff) | ((data << 8) & 0xff00);
157 init_chan (d, ichan);
159 r->base[nreg] = (r->base[nreg] & 0xff00) | (data & 0xff);
163 static void write_cont (void *opaque, uint32_t nport, uint32_t data)
165 struct dma_cont *d = opaque;
168 iport = (nport >> d->dshift) & 0x0f;
170 case 8: /* command */
171 if ((data != 0) && (data & CMD_NOT_SUPPORTED)) {
172 log ("command %#x not supported\n", data);
181 d->status |= 1 << (ichan + 4);
184 d->status &= ~(1 << (ichan + 4));
186 d->status &= ~(1 << ichan);
189 case 0xa: /* single mask */
191 d->mask |= 1 << (data & 3);
193 d->mask &= ~(1 << (data & 3));
205 op = (data >> 2) & 3;
206 ai = (data >> 4) & 1;
207 dir = (data >> 5) & 1;
208 opmode = (data >> 6) & 3;
210 linfo ("ichan %d, op %d, ai %d, dir %d, opmode %d\n",
211 ichan, op, ai, dir, opmode);
214 d->regs[ichan].mode = data;
218 case 0xc: /* clear flip flop */
222 case 0xd: /* reset */
229 case 0xe: /* clear mask for all channels */
233 case 0xf: /* write mask for all channels */
238 log ("dma: unknown iport %#x\n", iport);
244 linfo ("nport %#06x, ichan % 2d, val %#06x\n",
250 static uint32_t read_cont (void *opaque, uint32_t nport)
252 struct dma_cont *d = opaque;
255 iport = (nport >> d->dshift) & 0x0f;
257 case 0x08: /* status */
261 case 0x0f: /* mask */
271 int DMA_get_channel_mode (int nchan)
273 return dma_controllers[nchan > 3].regs[nchan & 3].mode;
276 void DMA_hold_DREQ (int nchan)
282 linfo ("held cont=%d chan=%d\n", ncont, ichan);
283 dma_controllers[ncont].status |= 1 << (ichan + 4);
286 void DMA_release_DREQ (int nchan)
292 linfo ("released cont=%d chan=%d\n", ncont, ichan);
293 dma_controllers[ncont].status &= ~(1 << (ichan + 4));
296 static void channel_run (int ncont, int ichan)
303 r = dma_controllers[ncont].regs + ichan;
304 /* ai = r->mode & 16; */
305 /* dir = r->mode & 32 ? -1 : 1; */
307 addr = (r->page << 16) | r->now[ADDR];
308 n = r->transfer_handler (r->opaque, addr,
309 (r->base[COUNT] << ncont) + (1 << ncont));
312 ldebug ("dma_pos %d size %d\n",
313 n, (r->base[1] << ncont) + (1 << ncont));
323 for (icont = 0; icont < 2; icont++, d++) {
324 for (ichan = 0; ichan < 4; ichan++) {
329 if ((0 == (d->mask & mask)) && (0 != (d->status & (mask << 4))))
330 channel_run (icont, ichan);
335 void DMA_register_channel (int nchan,
336 DMA_transfer_handler transfer_handler,
345 r = dma_controllers[ncont].regs + ichan;
346 r->transfer_handler = transfer_handler;
350 /* request the emulator to transfer a new DMA memory block ASAP */
351 void DMA_schedule(int nchan)
353 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT);
356 /* dshift = 0: 8 bit DMA, 1 = 16 bit DMA */
357 static void dma_init2(struct dma_cont *d, int base, int dshift, int page_base)
359 const static int page_port_list[] = { 0x1, 0x2, 0x3, 0x7 };
363 for (i = 0; i < 8; i++) {
364 register_ioport_write (base + (i << dshift), 1, 1, write_chan, d);
365 register_ioport_read (base + (i << dshift), 1, 1, read_chan, d);
367 for (i = 0; i < LENOFA (page_port_list); i++) {
368 register_ioport_write (page_base + page_port_list[i], 1, 1,
370 register_ioport_read (page_base + page_port_list[i], 1, 1,
373 for (i = 0; i < 8; i++) {
374 register_ioport_write (base + ((i + 8) << dshift), 1, 1,
376 register_ioport_read (base + ((i + 8) << dshift), 1, 1,
379 write_cont (d, base + (0x0d << dshift), 0);
384 dma_init2(&dma_controllers[0], 0x00, 0, 0x80);
385 dma_init2(&dma_controllers[1], 0xc0, 1, 0x88);