4 * Copyright (c) 2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 /* XXX: implement all timer modes */
29 //#define DEBUG_CUDA_PACKET
31 /* Bits in B data register: all active low */
32 #define TREQ 0x08 /* Transfer request (input) */
33 #define TACK 0x10 /* Transfer acknowledge (output) */
34 #define TIP 0x20 /* Transfer in progress (output) */
37 #define SR_CTRL 0x1c /* Shift register control bits */
38 #define SR_EXT 0x0c /* Shift on external clock */
39 #define SR_OUT 0x10 /* Shift out if 1 */
41 /* Bits in IFR and IER */
42 #define IER_SET 0x80 /* set bits in IER */
43 #define IER_CLR 0 /* clear bits in IER */
44 #define SR_INT 0x04 /* Shift register full/empty */
45 #define T1_INT 0x40 /* Timer 1 interrupt */
46 #define T2_INT 0x20 /* Timer 2 interrupt */
49 #define T1MODE 0xc0 /* Timer 1 mode */
50 #define T1MODE_CONT 0x40 /* continuous interrupts */
52 /* commands (1st byte) */
55 #define ERROR_PACKET 2
56 #define TIMER_PACKET 3
57 #define POWER_PACKET 4
58 #define MACIIC_PACKET 5
62 /* CUDA commands (2nd byte) */
63 #define CUDA_WARM_START 0x0
64 #define CUDA_AUTOPOLL 0x1
65 #define CUDA_GET_6805_ADDR 0x2
66 #define CUDA_GET_TIME 0x3
67 #define CUDA_GET_PRAM 0x7
68 #define CUDA_SET_6805_ADDR 0x8
69 #define CUDA_SET_TIME 0x9
70 #define CUDA_POWERDOWN 0xa
71 #define CUDA_POWERUP_TIME 0xb
72 #define CUDA_SET_PRAM 0xc
73 #define CUDA_MS_RESET 0xd
74 #define CUDA_SEND_DFAC 0xe
75 #define CUDA_BATTERY_SWAP_SENSE 0x10
76 #define CUDA_RESET_SYSTEM 0x11
77 #define CUDA_SET_IPL 0x12
78 #define CUDA_FILE_SERVER_FLAG 0x13
79 #define CUDA_SET_AUTO_RATE 0x14
80 #define CUDA_GET_AUTO_RATE 0x16
81 #define CUDA_SET_DEVICE_LIST 0x19
82 #define CUDA_GET_DEVICE_LIST 0x1a
83 #define CUDA_SET_ONE_SECOND_MODE 0x1b
84 #define CUDA_SET_POWER_MESSAGES 0x21
85 #define CUDA_GET_SET_IIC 0x22
86 #define CUDA_WAKEUP 0x23
87 #define CUDA_TIMER_TICKLE 0x24
88 #define CUDA_COMBINED_FORMAT_IIC 0x25
90 #define CUDA_TIMER_FREQ (4700000 / 6)
91 #define CUDA_ADB_POLL_FREQ 50
93 /* CUDA returns time_t's offset from Jan 1, 1904, not 1970 */
94 #define RTC_OFFSET 2082844800
96 typedef struct CUDATimer {
99 uint16_t counter_value; /* counter value at load time */
101 int64_t next_irq_time;
105 typedef struct CUDAState {
107 uint8_t b; /* B-side data */
108 uint8_t a; /* A-side data */
109 uint8_t dirb; /* B-side direction (1=output) */
110 uint8_t dira; /* A-side direction (1=output) */
111 uint8_t sr; /* Shift register */
112 uint8_t acr; /* Auxiliary control register */
113 uint8_t pcr; /* Peripheral control register */
114 uint8_t ifr; /* Interrupt flag register */
115 uint8_t ier; /* Interrupt enable register */
116 uint8_t anh; /* A-side data, no handshake */
120 uint8_t last_b; /* last value of B register */
121 uint8_t last_acr; /* last value of B register */
131 uint8_t data_in[128];
132 uint8_t data_out[16];
133 QEMUTimer *adb_poll_timer;
136 static CUDAState cuda_state;
139 static void cuda_update(CUDAState *s);
140 static void cuda_receive_packet_from_host(CUDAState *s,
141 const uint8_t *data, int len);
142 static void cuda_timer_update(CUDAState *s, CUDATimer *ti,
143 int64_t current_time);
145 static void cuda_update_irq(CUDAState *s)
147 if (s->ifr & s->ier & (SR_INT | T1_INT)) {
148 s->set_irq(s->irq_opaque, s->irq, 1);
150 s->set_irq(s->irq_opaque, s->irq, 0);
154 static unsigned int get_counter(CUDATimer *s)
157 unsigned int counter;
159 d = muldiv64(qemu_get_clock(vm_clock) - s->load_time,
160 CUDA_TIMER_FREQ, ticks_per_sec);
162 /* the timer goes down from latch to -1 (period of latch + 2) */
163 if (d <= (s->counter_value + 1)) {
164 counter = (s->counter_value - d) & 0xffff;
166 counter = (d - (s->counter_value + 1)) % (s->latch + 2);
167 counter = (s->latch - counter) & 0xffff;
170 counter = (s->counter_value - d) & 0xffff;
175 static void set_counter(CUDAState *s, CUDATimer *ti, unsigned int val)
178 printf("cuda: T%d.counter=%d\n",
179 1 + (ti->timer == NULL), val);
181 ti->load_time = qemu_get_clock(vm_clock);
182 ti->counter_value = val;
183 cuda_timer_update(s, ti, ti->load_time);
186 static int64_t get_next_irq_time(CUDATimer *s, int64_t current_time)
188 int64_t d, next_time;
189 unsigned int counter;
191 /* current counter value */
192 d = muldiv64(current_time - s->load_time,
193 CUDA_TIMER_FREQ, ticks_per_sec);
194 /* the timer goes down from latch to -1 (period of latch + 2) */
195 if (d <= (s->counter_value + 1)) {
196 counter = (s->counter_value - d) & 0xffff;
198 counter = (d - (s->counter_value + 1)) % (s->latch + 2);
199 counter = (s->latch - counter) & 0xffff;
202 /* Note: we consider the irq is raised on 0 */
203 if (counter == 0xffff) {
204 next_time = d + s->latch + 1;
205 } else if (counter == 0) {
206 next_time = d + s->latch + 2;
208 next_time = d + counter;
212 printf("latch=%d counter=%lld delta_next=%lld\n",
213 s->latch, d, next_time - d);
216 next_time = muldiv64(next_time, ticks_per_sec, CUDA_TIMER_FREQ) +
218 if (next_time <= current_time)
219 next_time = current_time + 1;
223 static void cuda_timer_update(CUDAState *s, CUDATimer *ti,
224 int64_t current_time)
228 if ((s->acr & T1MODE) != T1MODE_CONT) {
229 qemu_del_timer(ti->timer);
231 ti->next_irq_time = get_next_irq_time(ti, current_time);
232 qemu_mod_timer(ti->timer, ti->next_irq_time);
236 static void cuda_timer1(void *opaque)
238 CUDAState *s = opaque;
239 CUDATimer *ti = &s->timers[0];
241 cuda_timer_update(s, ti, ti->next_irq_time);
246 static uint32_t cuda_readb(void *opaque, target_phys_addr_t addr)
248 CUDAState *s = opaque;
251 addr = (addr >> 9) & 0xf;
266 val = get_counter(&s->timers[0]) & 0xff;
271 val = get_counter(&s->timers[0]) >> 8;
275 val = s->timers[0].latch & 0xff;
278 /* XXX: check this */
279 val = (s->timers[0].latch >> 8) & 0xff;
282 val = get_counter(&s->timers[1]) & 0xff;
286 val = get_counter(&s->timers[1]) >> 8;
311 if (addr != 13 || val != 0)
312 printf("cuda: read: reg=0x%x val=%02x\n", addr, val);
317 static void cuda_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
319 CUDAState *s = opaque;
321 addr = (addr >> 9) & 0xf;
323 printf("cuda: write: reg=0x%x val=%02x\n", addr, val);
341 s->timers[0].latch = (s->timers[0].latch & 0xff00) | val;
342 cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
345 s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8);
347 set_counter(s, &s->timers[0], s->timers[0].latch);
350 s->timers[0].latch = (s->timers[0].latch & 0xff00) | val;
351 cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
354 s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8);
356 cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
359 s->timers[1].latch = val;
360 set_counter(s, &s->timers[1], val);
363 set_counter(s, &s->timers[1], (val << 8) | s->timers[1].latch);
370 cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
385 s->ier |= val & 0x7f;
391 /* XXX: please explain me why the SPEC is not correct ! */
403 /* NOTE: TIP and TREQ are negated */
404 static void cuda_update(CUDAState *s)
406 int packet_received, len;
410 /* transfer requested from host */
412 if (s->acr & SR_OUT) {
414 if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) {
415 if (s->data_out_index < sizeof(s->data_out)) {
417 printf("cuda: send: %02x\n", s->sr);
419 s->data_out[s->data_out_index++] = s->sr;
425 if (s->data_in_index < s->data_in_size) {
427 if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) {
428 s->sr = s->data_in[s->data_in_index++];
430 printf("cuda: recv: %02x\n", s->sr);
432 /* indicate end of transfer */
433 if (s->data_in_index >= s->data_in_size) {
434 s->b = (s->b | TREQ);
442 /* no transfer requested: handle sync case */
443 if ((s->last_b & TIP) && (s->b & TACK) != (s->last_b & TACK)) {
444 /* update TREQ state each time TACK change state */
446 s->b = (s->b | TREQ);
448 s->b = (s->b & ~TREQ);
452 if (!(s->last_b & TIP)) {
453 /* handle end of host to cuda transfert */
454 packet_received = (s->data_out_index > 0);
455 /* always an IRQ at the end of transfert */
459 /* signal if there is data to read */
460 if (s->data_in_index < s->data_in_size) {
461 s->b = (s->b & ~TREQ);
466 s->last_acr = s->acr;
469 /* NOTE: cuda_receive_packet_from_host() can call cuda_update()
471 if (packet_received) {
472 len = s->data_out_index;
473 s->data_out_index = 0;
474 cuda_receive_packet_from_host(s, s->data_out, len);
478 static void cuda_send_packet_to_host(CUDAState *s,
479 const uint8_t *data, int len)
481 #ifdef DEBUG_CUDA_PACKET
484 printf("cuda_send_packet_to_host:\n");
485 for(i = 0; i < len; i++)
486 printf(" %02x", data[i]);
490 memcpy(s->data_in, data, len);
491 s->data_in_size = len;
492 s->data_in_index = 0;
498 static void cuda_adb_poll(void *opaque)
500 CUDAState *s = opaque;
501 uint8_t obuf[ADB_MAX_OUT_LEN + 2];
504 olen = adb_poll(&adb_bus, obuf + 2);
506 obuf[0] = ADB_PACKET;
507 obuf[1] = 0x40; /* polled data */
508 cuda_send_packet_to_host(s, obuf, olen + 2);
510 qemu_mod_timer(s->adb_poll_timer,
511 qemu_get_clock(vm_clock) +
512 (ticks_per_sec / CUDA_ADB_POLL_FREQ));
515 static void cuda_receive_packet(CUDAState *s,
516 const uint8_t *data, int len)
523 autopoll = (data[1] != 0);
524 if (autopoll != s->autopoll) {
525 s->autopoll = autopoll;
527 qemu_mod_timer(s->adb_poll_timer,
528 qemu_get_clock(vm_clock) +
529 (ticks_per_sec / CUDA_ADB_POLL_FREQ));
531 qemu_del_timer(s->adb_poll_timer);
534 obuf[0] = CUDA_PACKET;
536 cuda_send_packet_to_host(s, obuf, 2);
540 /* XXX: add time support ? */
541 ti = time(NULL) + RTC_OFFSET;
542 obuf[0] = CUDA_PACKET;
549 cuda_send_packet_to_host(s, obuf, 7);
551 case CUDA_FILE_SERVER_FLAG:
552 case CUDA_SET_DEVICE_LIST:
553 case CUDA_SET_AUTO_RATE:
554 case CUDA_SET_POWER_MESSAGES:
555 obuf[0] = CUDA_PACKET;
557 cuda_send_packet_to_host(s, obuf, 2);
560 obuf[0] = CUDA_PACKET;
562 cuda_send_packet_to_host(s, obuf, 2);
563 qemu_system_shutdown_request();
570 static void cuda_receive_packet_from_host(CUDAState *s,
571 const uint8_t *data, int len)
573 #ifdef DEBUG_CUDA_PACKET
576 printf("cuda_receive_packet_from_host:\n");
577 for(i = 0; i < len; i++)
578 printf(" %02x", data[i]);
585 uint8_t obuf[ADB_MAX_OUT_LEN + 2];
587 olen = adb_request(&adb_bus, obuf + 2, data + 1, len - 1);
589 obuf[0] = ADB_PACKET;
593 obuf[0] = ADB_PACKET;
597 cuda_send_packet_to_host(s, obuf, olen + 2);
601 cuda_receive_packet(s, data + 1, len - 1);
606 static void cuda_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
610 static void cuda_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
614 static uint32_t cuda_readw (void *opaque, target_phys_addr_t addr)
619 static uint32_t cuda_readl (void *opaque, target_phys_addr_t addr)
624 static CPUWriteMemoryFunc *cuda_write[] = {
630 static CPUReadMemoryFunc *cuda_read[] = {
636 int cuda_init(SetIRQFunc *set_irq, void *irq_opaque, int irq)
638 CUDAState *s = &cuda_state;
641 s->set_irq = set_irq;
642 s->irq_opaque = irq_opaque;
645 s->timers[0].index = 0;
646 s->timers[0].timer = qemu_new_timer(vm_clock, cuda_timer1, s);
647 s->timers[0].latch = 0xffff;
648 set_counter(s, &s->timers[0], 0xffff);
650 s->timers[1].index = 1;
651 s->timers[1].latch = 0;
652 // s->ier = T1_INT | SR_INT;
654 set_counter(s, &s->timers[1], 0xffff);
656 s->adb_poll_timer = qemu_new_timer(vm_clock, cuda_adb_poll, s);
657 cuda_mem_index = cpu_register_io_memory(0, cuda_read, cuda_write, s);
658 return cuda_mem_index;