4 * Copyright (c) 2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
26 /* Bits in B data register: all active low */
27 #define TREQ 0x08 /* Transfer request (input) */
28 #define TACK 0x10 /* Transfer acknowledge (output) */
29 #define TIP 0x20 /* Transfer in progress (output) */
32 #define SR_CTRL 0x1c /* Shift register control bits */
33 #define SR_EXT 0x0c /* Shift on external clock */
34 #define SR_OUT 0x10 /* Shift out if 1 */
36 /* Bits in IFR and IER */
37 #define IER_SET 0x80 /* set bits in IER */
38 #define IER_CLR 0 /* clear bits in IER */
39 #define SR_INT 0x04 /* Shift register full/empty */
40 #define T1_INT 0x40 /* Timer 1 interrupt */
43 #define T1MODE 0xc0 /* Timer 1 mode */
44 #define T1MODE_CONT 0x40 /* continuous interrupts */
46 /* commands (1st byte) */
49 #define ERROR_PACKET 2
50 #define TIMER_PACKET 3
51 #define POWER_PACKET 4
52 #define MACIIC_PACKET 5
56 /* CUDA commands (2nd byte) */
57 #define CUDA_WARM_START 0x0
58 #define CUDA_AUTOPOLL 0x1
59 #define CUDA_GET_6805_ADDR 0x2
60 #define CUDA_GET_TIME 0x3
61 #define CUDA_GET_PRAM 0x7
62 #define CUDA_SET_6805_ADDR 0x8
63 #define CUDA_SET_TIME 0x9
64 #define CUDA_POWERDOWN 0xa
65 #define CUDA_POWERUP_TIME 0xb
66 #define CUDA_SET_PRAM 0xc
67 #define CUDA_MS_RESET 0xd
68 #define CUDA_SEND_DFAC 0xe
69 #define CUDA_BATTERY_SWAP_SENSE 0x10
70 #define CUDA_RESET_SYSTEM 0x11
71 #define CUDA_SET_IPL 0x12
72 #define CUDA_FILE_SERVER_FLAG 0x13
73 #define CUDA_SET_AUTO_RATE 0x14
74 #define CUDA_GET_AUTO_RATE 0x16
75 #define CUDA_SET_DEVICE_LIST 0x19
76 #define CUDA_GET_DEVICE_LIST 0x1a
77 #define CUDA_SET_ONE_SECOND_MODE 0x1b
78 #define CUDA_SET_POWER_MESSAGES 0x21
79 #define CUDA_GET_SET_IIC 0x22
80 #define CUDA_WAKEUP 0x23
81 #define CUDA_TIMER_TICKLE 0x24
82 #define CUDA_COMBINED_FORMAT_IIC 0x25
84 #define CUDA_TIMER_FREQ (4700000 / 6)
86 typedef struct CUDATimer {
88 uint16_t counter_value; /* counter value at load time */
90 int64_t next_irq_time;
94 typedef struct CUDAState {
96 uint8_t b; /* B-side data */
97 uint8_t a; /* A-side data */
98 uint8_t dirb; /* B-side direction (1=output) */
99 uint8_t dira; /* A-side direction (1=output) */
100 uint8_t sr; /* Shift register */
101 uint8_t acr; /* Auxiliary control register */
102 uint8_t pcr; /* Peripheral control register */
103 uint8_t ifr; /* Interrupt flag register */
104 uint8_t ier; /* Interrupt enable register */
105 uint8_t anh; /* A-side data, no handshake */
109 uint8_t last_b; /* last value of B register */
110 uint8_t last_acr; /* last value of B register */
118 uint8_t data_in[128];
119 uint8_t data_out[16];
122 static CUDAState cuda_state;
125 static void cuda_update(CUDAState *s);
126 static void cuda_receive_packet_from_host(CUDAState *s,
127 const uint8_t *data, int len);
129 static void cuda_update_irq(CUDAState *s)
131 if (s->ifr & s->ier & SR_INT) {
132 pic_set_irq(s->irq, 1);
134 pic_set_irq(s->irq, 0);
138 static unsigned int get_counter(CUDATimer *s)
141 unsigned int counter;
143 d = muldiv64(qemu_get_clock(vm_clock) - s->load_time,
144 CUDA_TIMER_FREQ, ticks_per_sec);
145 if (d <= s->counter_value) {
148 counter = s->latch - 1 - ((d - s->counter_value) % s->latch);
153 static void set_counter(CUDATimer *s, unsigned int val)
155 s->load_time = qemu_get_clock(vm_clock);
156 s->counter_value = val;
159 static int64_t get_next_irq_time(CUDATimer *s, int64_t current_time)
161 int64_t d, next_time, base;
162 /* current counter value */
163 d = muldiv64(current_time - s->load_time,
164 CUDA_TIMER_FREQ, ticks_per_sec);
165 if (d <= s->counter_value) {
166 next_time = s->counter_value + 1;
168 base = ((d - s->counter_value) % s->latch);
169 base = (base * s->latch) + s->counter_value;
170 next_time = base + s->latch;
172 next_time = muldiv64(next_time, ticks_per_sec, CUDA_TIMER_FREQ) +
174 if (next_time <= current_time)
175 next_time = current_time + 1;
179 static void cuda_timer1(void *opaque)
181 CUDAState *s = opaque;
182 CUDATimer *ti = &s->timers[0];
184 ti->next_irq_time = get_next_irq_time(ti, ti->next_irq_time);
185 qemu_mod_timer(ti->timer, ti->next_irq_time);
190 static uint32_t cuda_readb(void *opaque, target_phys_addr_t addr)
192 CUDAState *s = opaque;
195 addr = (addr >> 9) & 0xf;
210 val = get_counter(&s->timers[0]) & 0xff;
215 val = get_counter(&s->timers[0]) >> 8;
220 val = s->timers[0].latch & 0xff;
223 val = (s->timers[0].latch >> 8) & 0xff;
226 val = get_counter(&s->timers[1]) & 0xff;
229 val = get_counter(&s->timers[1]) >> 8;
232 if (s->data_in_index < s->data_in_size) {
233 val = s->data_in[s->data_in_index];
256 printf("cuda: read: reg=0x%x val=%02x\n", addr, val);
261 static void cuda_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
263 CUDAState *s = opaque;
265 addr = (addr >> 9) & 0xf;
267 printf("cuda: write: reg=0x%x val=%02x\n", addr, val);
285 val = val | (get_counter(&s->timers[0]) & 0xff00);
286 set_counter(&s->timers[0], val);
289 val = (val << 8) | (get_counter(&s->timers[0]) & 0xff);
290 set_counter(&s->timers[0], val);
293 s->timers[0].latch = (s->timers[0].latch & 0xff00) | val;
296 s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8);
299 val = val | (get_counter(&s->timers[1]) & 0xff00);
300 set_counter(&s->timers[1], val);
303 val = (val << 8) | (get_counter(&s->timers[1]) & 0xff);
304 set_counter(&s->timers[1], val);
311 if ((s->acr & T1MODE) == T1MODE_CONT) {
312 if ((s->last_acr & T1MODE) != T1MODE_CONT) {
313 CUDATimer *ti = &s->timers[0];
314 /* activate timer interrupt */
315 ti->next_irq_time = get_next_irq_time(ti, qemu_get_clock(vm_clock));
316 qemu_mod_timer(ti->timer, ti->next_irq_time);
319 if ((s->last_acr & T1MODE) == T1MODE_CONT) {
320 CUDATimer *ti = &s->timers[0];
321 qemu_del_timer(ti->timer);
337 s->ier |= val & 0x7f;
351 /* NOTE: TIP and TREQ are negated */
352 static void cuda_update(CUDAState *s)
354 if (s->data_in_index < s->data_in_size) {
357 (s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) {
358 s->sr = s->data_in[s->data_in_index++];
363 if (s->data_in_index < s->data_in_size) {
364 /* there is some data to read */
365 s->b = (s->b & ~TREQ);
367 s->b = (s->b | TREQ);
370 if (s->acr & SR_OUT) {
373 (s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) {
374 if (s->data_out_index < sizeof(s->data_out)) {
375 s->data_out[s->data_out_index++] = s->sr;
382 /* check end of data output */
383 if (!(s->acr & SR_OUT) && (s->last_acr & SR_OUT)) {
384 if (s->data_out_index > 0)
385 cuda_receive_packet_from_host(s, s->data_out, s->data_out_index);
386 s->data_out_index = 0;
388 s->last_acr = s->acr;
392 static void cuda_send_packet_to_host(CUDAState *s,
393 const uint8_t *data, int len)
395 memcpy(s->data_in, data, len);
396 s->data_in_size = len;
397 s->data_in_index = 0;
403 void adb_send_packet(ADBBusState *bus, const uint8_t *buf, int len)
405 CUDAState *s = &cuda_state;
408 memcpy(data + 1, buf, len);
409 data[0] = ADB_PACKET;
410 cuda_send_packet_to_host(s, data, len + 1);
413 static void cuda_receive_packet(CUDAState *s,
414 const uint8_t *data, int len)
421 s->autopoll = data[1];
422 obuf[0] = CUDA_PACKET;
424 cuda_send_packet_to_host(s, obuf, 2);
427 /* XXX: add time support ? */
429 obuf[0] = CUDA_PACKET;
436 cuda_send_packet_to_host(s, obuf, 7);
439 case CUDA_FILE_SERVER_FLAG:
440 case CUDA_SET_DEVICE_LIST:
441 case CUDA_SET_AUTO_RATE:
442 case CUDA_SET_POWER_MESSAGES:
443 obuf[0] = CUDA_PACKET;
445 cuda_send_packet_to_host(s, obuf, 2);
452 static void cuda_receive_packet_from_host(CUDAState *s,
453 const uint8_t *data, int len)
457 adb_receive_packet(&adb_bus, data + 1, len - 1);
460 cuda_receive_packet(s, data + 1, len - 1);
465 static void cuda_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
469 static void cuda_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
473 static uint32_t cuda_readw (void *opaque, target_phys_addr_t addr)
478 static uint32_t cuda_readl (void *opaque, target_phys_addr_t addr)
483 static CPUWriteMemoryFunc *cuda_write[] = {
489 static CPUReadMemoryFunc *cuda_read[] = {
497 CUDAState *s = &cuda_state;
500 s->timers[0].latch = 0x10000;
501 set_counter(&s->timers[0], 0xffff);
502 s->timers[0].timer = qemu_new_timer(vm_clock, cuda_timer1, s);
503 s->timers[1].latch = 0x10000;
504 set_counter(&s->timers[1], 0xffff);
505 cuda_mem_index = cpu_register_io_memory(0, cuda_read, cuda_write, s);
506 return cuda_mem_index;