2 * ARM AMBA Generic/Distributed Interrupt Controller
4 * Copyright (c) 2006 CodeSourcery.
5 * Written by Paul Brook
7 * This code is licenced under the GPL.
10 /* TODO: Some variants of this controller can handle multiple CPUs.
11 Currently only single CPU operation is implemented. */
19 #define DPRINTF(fmt, args...) \
20 do { printf("arm_gic: " fmt , (int)s->base, ##args); } while (0)
22 #define DPRINTF(fmt, args...) do {} while(0)
25 /* Distributed interrupt controller. */
27 static const uint8_t gic_id[] =
28 { 0x90, 0x13, 0x04, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
32 typedef struct gic_irq_state
38 unsigned model:1; /* 0 = 1:N, 1 = N:N */
39 unsigned trigger:1; /* nonzero = edge triggered. */
42 #define GIC_SET_ENABLED(irq) s->irq_state[irq].enabled = 1
43 #define GIC_CLEAR_ENABLED(irq) s->irq_state[irq].enabled = 0
44 #define GIC_TEST_ENABLED(irq) s->irq_state[irq].enabled
45 #define GIC_SET_PENDING(irq) s->irq_state[irq].pending = 1
46 #define GIC_CLEAR_PENDING(irq) s->irq_state[irq].pending = 0
47 #define GIC_TEST_PENDING(irq) s->irq_state[irq].pending
48 #define GIC_SET_ACTIVE(irq) s->irq_state[irq].active = 1
49 #define GIC_CLEAR_ACTIVE(irq) s->irq_state[irq].active = 0
50 #define GIC_TEST_ACTIVE(irq) s->irq_state[irq].active
51 #define GIC_SET_MODEL(irq) s->irq_state[irq].model = 1
52 #define GIC_CLEAR_MODEL(irq) s->irq_state[irq].model = 0
53 #define GIC_TEST_MODEL(irq) s->irq_state[irq].model
54 #define GIC_SET_LEVEL(irq) s->irq_state[irq].level = 1
55 #define GIC_CLEAR_LEVEL(irq) s->irq_state[irq].level = 0
56 #define GIC_TEST_LEVEL(irq) s->irq_state[irq].level
57 #define GIC_SET_TRIGGER(irq) s->irq_state[irq].trigger = 1
58 #define GIC_CLEAR_TRIGGER(irq) s->irq_state[irq].trigger = 0
59 #define GIC_TEST_TRIGGER(irq) s->irq_state[irq].trigger
61 typedef struct gic_state
63 arm_pic_handler handler;
70 gic_irq_state irq_state[GIC_NIRQ];
71 int irq_target[GIC_NIRQ];
72 int priority[GIC_NIRQ];
73 int last_active[GIC_NIRQ];
81 /* TODO: Many places that call this routine could be optimized. */
82 /* Update interrupt status after enabled or pending bits have been changed. */
83 static void gic_update(gic_state *s)
89 s->current_pending = 1023;
90 if (!s->enabled || !s->cpu_enabled) {
91 pic_set_irq_new(s->parent, s->parent_irq, 0);
96 for (irq = 0; irq < 96; irq++) {
97 if (GIC_TEST_ENABLED(irq) && GIC_TEST_PENDING(irq)) {
98 if (s->priority[irq] < best_prio) {
99 best_prio = s->priority[irq];
104 if (best_prio > s->priority_mask) {
105 pic_set_irq_new(s->parent, s->parent_irq, 0);
107 s->current_pending = best_irq;
108 if (best_prio < s->running_priority) {
109 DPRINTF("Raised pending IRQ %d\n", best_irq);
110 pic_set_irq_new(s->parent, s->parent_irq, 1);
115 static void gic_set_irq(void *opaque, int irq, int level)
117 gic_state *s = (gic_state *)opaque;
118 /* The first external input line is internal interrupt 32. */
120 if (level == GIC_TEST_LEVEL(irq))
125 if (GIC_TEST_TRIGGER(irq) || GIC_TEST_ENABLED(irq)) {
126 DPRINTF("Set %d pending\n", irq);
127 GIC_SET_PENDING(irq);
130 GIC_CLEAR_LEVEL(irq);
135 static void gic_set_running_irq(gic_state *s, int irq)
137 s->running_irq = irq;
138 s->running_priority = s->priority[irq];
142 static uint32_t gic_acknowledge_irq(gic_state *s)
145 new_irq = s->current_pending;
146 if (new_irq == 1023 || s->priority[new_irq] >= s->running_priority) {
147 DPRINTF("ACK no pending IRQ\n");
150 pic_set_irq_new(s->parent, s->parent_irq, 0);
151 s->last_active[new_irq] = s->running_irq;
152 /* For level triggered interrupts we clear the pending bit while
153 the interrupt is active. */
154 GIC_CLEAR_PENDING(new_irq);
155 gic_set_running_irq(s, new_irq);
156 DPRINTF("ACK %d\n", new_irq);
160 static void gic_complete_irq(gic_state * s, int irq)
163 DPRINTF("EIO %d\n", irq);
164 if (s->running_irq == 1023)
165 return; /* No active IRQ. */
167 /* Mark level triggered interrupts as pending if they are still
169 if (!GIC_TEST_TRIGGER(irq) && GIC_TEST_ENABLED(irq)
170 && GIC_TEST_LEVEL(irq)) {
171 GIC_SET_PENDING(irq);
175 if (irq != s->running_irq) {
176 /* Complete an IRQ that is not currently running. */
177 int tmp = s->running_irq;
178 while (s->last_active[tmp] != 1023) {
179 if (s->last_active[tmp] == irq) {
180 s->last_active[tmp] = s->last_active[irq];
183 tmp = s->last_active[tmp];
189 /* Complete the current running IRQ. */
190 gic_set_running_irq(s, s->last_active[s->running_irq]);
194 static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset)
196 gic_state *s = (gic_state *)opaque;
201 offset -= s->base + 0x1000;
202 if (offset < 0x100) {
206 return (GIC_NIRQ / 32) - 1;
210 } else if (offset < 0x200) {
211 /* Interrupt Set/Clear Enable. */
213 irq = (offset - 0x100) * 8;
215 irq = (offset - 0x180) * 8;
219 for (i = 0; i < 8; i++) {
220 if (GIC_TEST_ENABLED(irq + i)) {
224 } else if (offset < 0x300) {
225 /* Interrupt Set/Clear Pending. */
227 irq = (offset - 0x200) * 8;
229 irq = (offset - 0x280) * 8;
233 for (i = 0; i < 8; i++) {
234 if (GIC_TEST_PENDING(irq + i)) {
238 } else if (offset < 0x400) {
239 /* Interrupt Active. */
240 irq = (offset - 0x300) * 8;
244 for (i = 0; i < 8; i++) {
245 if (GIC_TEST_ACTIVE(irq + i)) {
249 } else if (offset < 0x800) {
250 /* Interrupt Priority. */
251 irq = offset - 0x400;
254 res = s->priority[irq];
255 } else if (offset < 0xc00) {
256 /* Interrupt CPU Target. */
257 irq = offset - 0x800;
260 res = s->irq_target[irq];
261 } else if (offset < 0xf00) {
262 /* Interrupt Configuration. */
263 irq = (offset - 0xc00) * 2;
267 for (i = 0; i < 4; i++) {
268 if (GIC_TEST_MODEL(irq + i))
269 res |= (1 << (i * 2));
270 if (GIC_TEST_TRIGGER(irq + i))
271 res |= (2 << (i * 2));
273 } else if (offset < 0xfe0) {
275 } else /* offset >= 0xfe0 */ {
279 res = gic_id[(offset - 0xfe0) >> 2];
284 cpu_abort (cpu_single_env, "gic_dist_readb: Bad offset %x\n", offset);
288 static uint32_t gic_dist_readw(void *opaque, target_phys_addr_t offset)
291 val = gic_dist_readb(opaque, offset);
292 val |= gic_dist_readb(opaque, offset + 1) << 8;
296 static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset)
299 val = gic_dist_readw(opaque, offset);
300 val |= gic_dist_readw(opaque, offset + 2) << 16;
304 static void gic_dist_writeb(void *opaque, target_phys_addr_t offset,
307 gic_state *s = (gic_state *)opaque;
311 offset -= s->base + 0x1000;
312 if (offset < 0x100) {
314 s->enabled = (value & 1);
315 DPRINTF("Distribution %sabled\n", s->enabled ? "En" : "Dis");
316 } else if (offset < 4) {
321 } else if (offset < 0x180) {
322 /* Interrupt Set Enable. */
323 irq = (offset - 0x100) * 8;
326 for (i = 0; i < 8; i++) {
327 if (value & (1 << i)) {
328 if (!GIC_TEST_ENABLED(irq + i))
329 DPRINTF("Enabled IRQ %d\n", irq + i);
330 GIC_SET_ENABLED(irq + i);
331 /* If a raised level triggered IRQ enabled then mark
333 if (GIC_TEST_LEVEL(irq + i) && !GIC_TEST_TRIGGER(irq + i))
334 GIC_SET_PENDING(irq + i);
337 } else if (offset < 0x200) {
338 /* Interrupt Clear Enable. */
339 irq = (offset - 0x180) * 8;
342 for (i = 0; i < 8; i++) {
343 if (value & (1 << i)) {
344 if (GIC_TEST_ENABLED(irq + i))
345 DPRINTF("Disabled IRQ %d\n", irq + i);
346 GIC_CLEAR_ENABLED(irq + i);
349 } else if (offset < 0x280) {
350 /* Interrupt Set Pending. */
351 irq = (offset - 0x200) * 8;
354 for (i = 0; i < 8; i++) {
355 if (value & (1 << i)) {
356 GIC_SET_PENDING(irq + i);
359 } else if (offset < 0x300) {
360 /* Interrupt Clear Pending. */
361 irq = (offset - 0x280) * 8;
364 for (i = 0; i < 8; i++) {
365 if (value & (1 << i)) {
366 GIC_CLEAR_PENDING(irq + i);
369 } else if (offset < 0x400) {
370 /* Interrupt Active. */
372 } else if (offset < 0x800) {
373 /* Interrupt Priority. */
374 irq = offset - 0x400;
377 s->priority[irq] = value;
378 } else if (offset < 0xc00) {
379 /* Interrupt CPU Target. */
380 irq = offset - 0x800;
383 s->irq_target[irq] = value;
384 } else if (offset < 0xf00) {
385 /* Interrupt Configuration. */
386 irq = (offset - 0xc00) * 2;
389 for (i = 0; i < 4; i++) {
390 if (value & (1 << (i * 2))) {
391 GIC_SET_MODEL(irq + i);
393 GIC_CLEAR_MODEL(irq + i);
395 if (value & (2 << (i * 2))) {
396 GIC_SET_TRIGGER(irq + i);
398 GIC_CLEAR_TRIGGER(irq + i);
402 /* 0xf00 is only handled for word writes. */
408 cpu_abort (cpu_single_env, "gic_dist_writeb: Bad offset %x\n", offset);
411 static void gic_dist_writew(void *opaque, target_phys_addr_t offset,
414 gic_state *s = (gic_state *)opaque;
415 if (offset - s->base == 0xf00) {
416 GIC_SET_PENDING(value & 0x3ff);
420 gic_dist_writeb(opaque, offset, value & 0xff);
421 gic_dist_writeb(opaque, offset + 1, value >> 8);
424 static void gic_dist_writel(void *opaque, target_phys_addr_t offset,
427 gic_dist_writew(opaque, offset, value & 0xffff);
428 gic_dist_writew(opaque, offset + 2, value >> 16);
431 static CPUReadMemoryFunc *gic_dist_readfn[] = {
437 static CPUWriteMemoryFunc *gic_dist_writefn[] = {
443 static uint32_t gic_cpu_read(void *opaque, target_phys_addr_t offset)
445 gic_state *s = (gic_state *)opaque;
448 case 0x00: /* Control */
449 return s->cpu_enabled;
450 case 0x04: /* Priority mask */
451 return s->priority_mask;
452 case 0x08: /* Binary Point */
453 /* ??? Not implemented. */
455 case 0x0c: /* Acknowledge */
456 return gic_acknowledge_irq(s);
457 case 0x14: /* Runing Priority */
458 return s->running_priority;
459 case 0x18: /* Highest Pending Interrupt */
460 return s->current_pending;
462 cpu_abort (cpu_single_env, "gic_cpu_writeb: Bad offset %x\n", offset);
467 static void gic_cpu_write(void *opaque, target_phys_addr_t offset,
470 gic_state *s = (gic_state *)opaque;
473 case 0x00: /* Control */
474 s->cpu_enabled = (value & 1);
475 DPRINTF("CPU %sabled\n", s->cpu_enabled ? "En" : "Dis");
477 case 0x04: /* Priority mask */
478 s->priority_mask = (value & 0x3ff);
480 case 0x08: /* Binary Point */
481 /* ??? Not implemented. */
483 case 0x10: /* End Of Interrupt */
484 return gic_complete_irq(s, value & 0x3ff);
486 cpu_abort (cpu_single_env, "gic_cpu_writeb: Bad offset %x\n", offset);
492 static CPUReadMemoryFunc *gic_cpu_readfn[] = {
498 static CPUWriteMemoryFunc *gic_cpu_writefn[] = {
504 static void gic_reset(gic_state *s)
507 memset(s->irq_state, 0, GIC_NIRQ * sizeof(gic_irq_state));
508 s->priority_mask = 0xf0;
509 s->current_pending = 1023;
510 s->running_irq = 1023;
511 s->running_priority = 0x100;
512 for (i = 0; i < 15; i++) {
520 void *arm_gic_init(uint32_t base, void *parent, int parent_irq)
525 s = (gic_state *)qemu_mallocz(sizeof(gic_state));
528 s->handler = gic_set_irq;
530 s->parent_irq = parent_irq;
531 if (base != 0xffffffff) {
532 iomemtype = cpu_register_io_memory(0, gic_cpu_readfn,
534 cpu_register_physical_memory(base, 0x00000fff, iomemtype);
535 iomemtype = cpu_register_io_memory(0, gic_dist_readfn,
536 gic_dist_writefn, s);
537 cpu_register_physical_memory(base + 0x1000, 0x00000fff, iomemtype);