4 * Copyright (c) 2004-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 /* APIC Local Vector Table */
25 #define APIC_LVT_TIMER 0
26 #define APIC_LVT_THERMAL 1
27 #define APIC_LVT_PERFORM 2
28 #define APIC_LVT_LINT0 3
29 #define APIC_LVT_LINT1 4
30 #define APIC_LVT_ERROR 5
33 /* APIC delivery modes */
34 #define APIC_DM_FIXED 0
35 #define APIC_DM_LOWPRI 1
38 #define APIC_DM_INIT 5
39 #define APIC_DM_SIPI 6
40 #define APIC_DM_EXTINT 7
42 #define APIC_TRIGGER_EDGE 0
43 #define APIC_TRIGGER_LEVEL 1
45 #define APIC_LVT_TIMER_PERIODIC (1<<17)
46 #define APIC_LVT_MASKED (1<<16)
47 #define APIC_LVT_LEVEL_TRIGGER (1<<15)
48 #define APIC_LVT_REMOTE_IRR (1<<14)
49 #define APIC_INPUT_POLARITY (1<<13)
50 #define APIC_SEND_PENDING (1<<12)
52 #define ESR_ILLEGAL_ADDRESS (1 << 7)
54 #define APIC_SV_ENABLE (1 << 8)
56 typedef struct APICState {
61 uint32_t spurious_vec;
62 uint32_t isr[8]; /* in service register */
63 uint32_t tmr[8]; /* trigger mode register */
64 uint32_t irr[8]; /* interrupt request register */
65 uint32_t lvt[APIC_LVT_NB];
66 uint32_t esr; /* error register */
71 uint32_t initial_count;
72 int64_t initial_count_load_time, next_time;
76 static int apic_io_memory;
78 void cpu_set_apic_base(CPUState *env, uint64_t val)
80 APICState *s = env->apic_state;
82 printf("cpu_set_apic_base: %016llx\n", val);
84 s->apicbase = (val & 0xfffff000) |
85 (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
86 /* if disabled, cannot be enabled again */
87 if (!(val & MSR_IA32_APICBASE_ENABLE)) {
88 s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
89 env->cpuid_features &= ~CPUID_APIC;
90 s->spurious_vec &= ~APIC_SV_ENABLE;
94 uint64_t cpu_get_apic_base(CPUState *env)
96 APICState *s = env->apic_state;
98 printf("cpu_get_apic_base: %016llx\n", (uint64_t)s->apicbase);
103 void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
105 APICState *s = env->apic_state;
106 s->tpr = (val & 0x0f) << 4;
109 uint8_t cpu_get_apic_tpr(CPUX86State *env)
111 APICState *s = env->apic_state;
115 /* return -1 if no bit is set */
116 static int get_highest_priority_int(uint32_t *tab)
119 for(i = 0;i < 8; i++) {
121 return i * 32 + ffs(tab[i]) - 1;
127 static inline void set_bit(uint32_t *tab, int index)
131 mask = 1 << (index & 0x1f);
135 static inline void reset_bit(uint32_t *tab, int index)
139 mask = 1 << (index & 0x1f);
143 static int apic_get_ppr(APICState *s)
148 isrv = get_highest_priority_int(s->isr);
159 /* signal the CPU if an irq is pending */
160 static void apic_update_irq(APICState *s)
163 irrv = get_highest_priority_int(s->irr);
166 isrv = get_highest_priority_int(s->isr);
167 /* if the pending irq has less priority, we do not make a new request */
168 if (isrv >= 0 && irrv >= isrv)
170 cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
173 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode)
175 set_bit(s->irr, vector_num);
177 set_bit(s->tmr, vector_num);
179 reset_bit(s->tmr, vector_num);
183 static void apic_eoi(APICState *s)
186 isrv = get_highest_priority_int(s->isr);
189 reset_bit(s->isr, isrv);
193 int apic_get_interrupt(CPUState *env)
195 APICState *s = env->apic_state;
198 /* if the APIC is installed or enabled, we let the 8259 handle the
202 if (!(s->spurious_vec & APIC_SV_ENABLE))
205 /* XXX: spurious IRQ handling */
206 intno = get_highest_priority_int(s->irr);
209 reset_bit(s->irr, intno);
210 set_bit(s->isr, intno);
215 static uint32_t apic_get_current_count(APICState *s)
219 d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >>
221 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
223 val = s->initial_count - (d % (s->initial_count + 1));
225 if (d >= s->initial_count)
228 val = s->initial_count - d;
233 static void apic_timer_update(APICState *s, int64_t current_time)
235 int64_t next_time, d;
237 if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
238 d = (current_time - s->initial_count_load_time) >>
240 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
241 d = ((d / (s->initial_count + 1)) + 1) * (s->initial_count + 1);
243 if (d >= s->initial_count)
245 d = s->initial_count + 1;
247 next_time = s->initial_count_load_time + (d << s->count_shift);
248 qemu_mod_timer(s->timer, next_time);
249 s->next_time = next_time;
252 qemu_del_timer(s->timer);
256 static void apic_timer(void *opaque)
258 APICState *s = opaque;
260 if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
261 apic_set_irq(s, s->lvt[APIC_LVT_TIMER] & 0xff, APIC_TRIGGER_EDGE);
263 apic_timer_update(s, s->next_time);
266 static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
271 static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
276 static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
280 static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
284 static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
291 env = cpu_single_env;
296 index = (addr >> 4) & 0xff;
301 case 0x03: /* version */
302 val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
309 val = apic_get_ppr(s);
312 val = s->spurious_vec;
315 val = s->isr[index & 7];
318 val = s->tmr[index & 7];
321 val = s->irr[index & 7];
327 val = s->lvt[index - 0x32];
331 val = s->icr[index & 1];
334 val = s->initial_count;
337 val = apic_get_current_count(s);
340 val = s->divide_conf;
343 s->esr |= ESR_ILLEGAL_ADDRESS;
348 printf("APIC read: %08x = %08x\n", (uint32_t)addr, val);
353 static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
359 env = cpu_single_env;
365 printf("APIC write: %08x = %08x\n", (uint32_t)addr, val);
368 index = (addr >> 4) & 0xff;
380 s->spurious_vec = val & 0x1ff;
384 s->icr[index & 1] = val;
388 int n = index - 0x32;
390 if (n == APIC_LVT_TIMER)
391 apic_timer_update(s, qemu_get_clock(vm_clock));
395 s->initial_count = val;
396 s->initial_count_load_time = qemu_get_clock(vm_clock);
397 apic_timer_update(s, s->initial_count_load_time);
402 s->divide_conf = val & 0xb;
403 v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
404 s->count_shift = (v + 1) & 7;
408 s->esr |= ESR_ILLEGAL_ADDRESS;
415 static CPUReadMemoryFunc *apic_mem_read[3] = {
421 static CPUWriteMemoryFunc *apic_mem_write[3] = {
427 int apic_init(CPUState *env)
432 s = malloc(sizeof(APICState));
435 memset(s, 0, sizeof(*s));
438 s->apicbase = 0xfee00000 |
439 MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE;
440 for(i = 0; i < APIC_LVT_NB; i++)
441 s->lvt[i] = 1 << 16; /* mask LVT */
442 s->spurious_vec = 0xff;
444 if (apic_io_memory == 0) {
445 /* NOTE: the APIC is directly connected to the CPU - it is not
446 on the global memory bus. */
447 apic_io_memory = cpu_register_io_memory(0, apic_mem_read,
448 apic_mem_write, NULL);
449 cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000, apic_io_memory);
451 s->timer = qemu_new_timer(vm_clock, apic_timer, s);