4 * Copyright (c) 2004-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 //#define DEBUG_IOAPIC
25 /* APIC Local Vector Table */
26 #define APIC_LVT_TIMER 0
27 #define APIC_LVT_THERMAL 1
28 #define APIC_LVT_PERFORM 2
29 #define APIC_LVT_LINT0 3
30 #define APIC_LVT_LINT1 4
31 #define APIC_LVT_ERROR 5
34 /* APIC delivery modes */
35 #define APIC_DM_FIXED 0
36 #define APIC_DM_LOWPRI 1
39 #define APIC_DM_INIT 5
40 #define APIC_DM_SIPI 6
41 #define APIC_DM_EXTINT 7
43 /* APIC destination mode */
44 #define APIC_DESTMODE_FLAT 0xf
45 #define APIC_DESTMODE_CLUSTER 1
47 #define APIC_TRIGGER_EDGE 0
48 #define APIC_TRIGGER_LEVEL 1
50 #define APIC_LVT_TIMER_PERIODIC (1<<17)
51 #define APIC_LVT_MASKED (1<<16)
52 #define APIC_LVT_LEVEL_TRIGGER (1<<15)
53 #define APIC_LVT_REMOTE_IRR (1<<14)
54 #define APIC_INPUT_POLARITY (1<<13)
55 #define APIC_SEND_PENDING (1<<12)
57 #define IOAPIC_NUM_PINS 0x18
59 #define ESR_ILLEGAL_ADDRESS (1 << 7)
61 #define APIC_SV_ENABLE (1 << 8)
63 typedef struct APICState {
69 uint32_t spurious_vec;
72 uint32_t isr[8]; /* in service register */
73 uint32_t tmr[8]; /* trigger mode register */
74 uint32_t irr[8]; /* interrupt request register */
75 uint32_t lvt[APIC_LVT_NB];
76 uint32_t esr; /* error register */
81 uint32_t initial_count;
82 int64_t initial_count_load_time, next_time;
85 struct APICState *next_apic;
93 uint64_t ioredtbl[IOAPIC_NUM_PINS];
96 static int apic_io_memory;
97 static APICState *first_local_apic = NULL;
98 static int last_apic_id = 0;
100 static void apic_init_ipi(APICState *s);
101 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode);
102 static void apic_update_irq(APICState *s);
104 static void apic_bus_deliver(uint32_t deliver_bitmask, uint8_t delivery_mode,
105 uint8_t vector_num, uint8_t polarity,
106 uint8_t trigger_mode)
108 APICState *apic_iter;
110 switch (delivery_mode) {
112 /* XXX: search for focus processor, arbitration */
113 if (deliver_bitmask) {
115 while ((deliver_bitmask & m) == 0)
129 /* normal INIT IPI sent to processors */
130 for (apic_iter = first_local_apic; apic_iter != NULL;
131 apic_iter = apic_iter->next_apic) {
132 if (deliver_bitmask & (1 << apic_iter->id))
133 apic_init_ipi(apic_iter);
138 /* handled in I/O APIC code */
145 for (apic_iter = first_local_apic; apic_iter != NULL;
146 apic_iter = apic_iter->next_apic) {
147 if (deliver_bitmask & (1 << apic_iter->id))
148 apic_set_irq(apic_iter, vector_num, trigger_mode);
152 void cpu_set_apic_base(CPUState *env, uint64_t val)
154 APICState *s = env->apic_state;
156 printf("cpu_set_apic_base: %016llx\n", val);
158 s->apicbase = (val & 0xfffff000) |
159 (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
160 /* if disabled, cannot be enabled again */
161 if (!(val & MSR_IA32_APICBASE_ENABLE)) {
162 s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
163 env->cpuid_features &= ~CPUID_APIC;
164 s->spurious_vec &= ~APIC_SV_ENABLE;
168 uint64_t cpu_get_apic_base(CPUState *env)
170 APICState *s = env->apic_state;
172 printf("cpu_get_apic_base: %016llx\n", (uint64_t)s->apicbase);
177 void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
179 APICState *s = env->apic_state;
180 s->tpr = (val & 0x0f) << 4;
184 uint8_t cpu_get_apic_tpr(CPUX86State *env)
186 APICState *s = env->apic_state;
190 static int fls_bit(int value)
192 unsigned int ret = 0;
195 __asm__ __volatile__ ("bsr %1, %0\n" : "+r" (ret) : "rm" (value));
199 value >>= 16, ret = 16;
201 value >>= 8, ret += 8;
203 value >>= 4, ret += 4;
205 value >>= 2, ret += 2;
206 return ret + (value >> 1);
210 static inline void set_bit(uint32_t *tab, int index)
214 mask = 1 << (index & 0x1f);
218 static inline void reset_bit(uint32_t *tab, int index)
222 mask = 1 << (index & 0x1f);
226 /* return -1 if no bit is set */
227 static int get_highest_priority_int(uint32_t *tab)
230 for(i = 7; i >= 0; i--) {
232 return i * 32 + fls_bit(tab[i]);
238 static int apic_get_ppr(APICState *s)
243 isrv = get_highest_priority_int(s->isr);
254 static int apic_get_arb_pri(APICState *s)
256 /* XXX: arbitration */
260 /* signal the CPU if an irq is pending */
261 static void apic_update_irq(APICState *s)
264 if (!(s->spurious_vec & APIC_SV_ENABLE))
266 irrv = get_highest_priority_int(s->irr);
269 ppr = apic_get_ppr(s);
270 if (ppr && (irrv & 0xf0) <= (ppr & 0xf0))
272 cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
275 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode)
277 set_bit(s->irr, vector_num);
279 set_bit(s->tmr, vector_num);
281 reset_bit(s->tmr, vector_num);
285 static void apic_eoi(APICState *s)
288 isrv = get_highest_priority_int(s->isr);
291 reset_bit(s->isr, isrv);
292 /* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
293 set the remote IRR bit for level triggered interrupts. */
297 static uint32_t apic_get_delivery_bitmask(uint8_t dest, uint8_t dest_mode)
300 APICState *apic_iter;
302 if (dest_mode == 0) {
308 /* XXX: cluster mode */
309 for (apic_iter = first_local_apic; apic_iter != NULL;
310 apic_iter = apic_iter->next_apic) {
311 if (dest & apic_iter->log_dest)
312 mask |= (1 << apic_iter->id);
320 static void apic_init_ipi(APICState *s)
324 for(i = 0; i < APIC_LVT_NB; i++)
325 s->lvt[i] = 1 << 16; /* mask LVT */
327 s->spurious_vec = 0xff;
330 memset(s->isr, 0, sizeof(s->isr));
331 memset(s->tmr, 0, sizeof(s->tmr));
332 memset(s->irr, 0, sizeof(s->irr));
333 memset(s->lvt, 0, sizeof(s->lvt));
335 memset(s->icr, 0, sizeof(s->icr));
338 s->initial_count = 0;
339 s->initial_count_load_time = 0;
343 /* send a SIPI message to the CPU to start it */
344 static void apic_startup(APICState *s, int vector_num)
346 CPUState *env = s->cpu_env;
347 if (!(env->hflags & HF_HALTED_MASK))
350 cpu_x86_load_seg_cache(env, R_CS, vector_num << 8, vector_num << 12,
352 env->hflags &= ~HF_HALTED_MASK;
355 static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode,
356 uint8_t delivery_mode, uint8_t vector_num,
357 uint8_t polarity, uint8_t trigger_mode)
359 uint32_t deliver_bitmask = 0;
360 int dest_shorthand = (s->icr[0] >> 18) & 3;
361 APICState *apic_iter;
363 switch (dest_shorthand) {
365 deliver_bitmask = apic_get_delivery_bitmask(dest, dest_mode);
368 deliver_bitmask = (1 << s->id);
371 deliver_bitmask = 0xffffffff;
374 deliver_bitmask = 0xffffffff & ~(1 << s->id);
378 switch (delivery_mode) {
381 int trig_mode = (s->icr[0] >> 15) & 1;
382 int level = (s->icr[0] >> 14) & 1;
383 if (level == 0 && trig_mode == 1) {
384 for (apic_iter = first_local_apic; apic_iter != NULL;
385 apic_iter = apic_iter->next_apic) {
386 if (deliver_bitmask & (1 << apic_iter->id)) {
387 apic_iter->arb_id = apic_iter->id;
396 for (apic_iter = first_local_apic; apic_iter != NULL;
397 apic_iter = apic_iter->next_apic) {
398 if (deliver_bitmask & (1 << apic_iter->id)) {
399 apic_startup(apic_iter, vector_num);
405 apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
409 int apic_get_interrupt(CPUState *env)
411 APICState *s = env->apic_state;
414 /* if the APIC is installed or enabled, we let the 8259 handle the
418 if (!(s->spurious_vec & APIC_SV_ENABLE))
421 /* XXX: spurious IRQ handling */
422 intno = get_highest_priority_int(s->irr);
425 reset_bit(s->irr, intno);
426 if (s->tpr && intno <= s->tpr)
427 return s->spurious_vec & 0xff;
428 set_bit(s->isr, intno);
433 static uint32_t apic_get_current_count(APICState *s)
437 d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >>
439 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
441 val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
443 if (d >= s->initial_count)
446 val = s->initial_count - d;
451 static void apic_timer_update(APICState *s, int64_t current_time)
453 int64_t next_time, d;
455 if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
456 d = (current_time - s->initial_count_load_time) >>
458 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
459 d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);
461 if (d >= s->initial_count)
463 d = (uint64_t)s->initial_count + 1;
465 next_time = s->initial_count_load_time + (d << s->count_shift);
466 qemu_mod_timer(s->timer, next_time);
467 s->next_time = next_time;
470 qemu_del_timer(s->timer);
474 static void apic_timer(void *opaque)
476 APICState *s = opaque;
478 if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
479 apic_set_irq(s, s->lvt[APIC_LVT_TIMER] & 0xff, APIC_TRIGGER_EDGE);
481 apic_timer_update(s, s->next_time);
484 static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
489 static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
494 static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
498 static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
502 static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
509 env = cpu_single_env;
514 index = (addr >> 4) & 0xff;
519 case 0x03: /* version */
520 val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
526 val = apic_get_arb_pri(s);
530 val = apic_get_ppr(s);
533 val = s->log_dest << 24;
536 val = s->dest_mode << 28;
539 val = s->spurious_vec;
542 val = s->isr[index & 7];
545 val = s->tmr[index & 7];
548 val = s->irr[index & 7];
555 val = s->icr[index & 1];
558 val = s->lvt[index - 0x32];
561 val = s->initial_count;
564 val = apic_get_current_count(s);
567 val = s->divide_conf;
570 s->esr |= ESR_ILLEGAL_ADDRESS;
575 printf("APIC read: %08x = %08x\n", (uint32_t)addr, val);
580 static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
586 env = cpu_single_env;
592 printf("APIC write: %08x = %08x\n", (uint32_t)addr, val);
595 index = (addr >> 4) & 0xff;
613 s->log_dest = val >> 24;
616 s->dest_mode = val >> 28;
619 s->spurious_vec = val & 0x1ff;
629 apic_deliver(s, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
630 (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
631 (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
638 int n = index - 0x32;
640 if (n == APIC_LVT_TIMER)
641 apic_timer_update(s, qemu_get_clock(vm_clock));
645 s->initial_count = val;
646 s->initial_count_load_time = qemu_get_clock(vm_clock);
647 apic_timer_update(s, s->initial_count_load_time);
654 s->divide_conf = val & 0xb;
655 v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
656 s->count_shift = (v + 1) & 7;
660 s->esr |= ESR_ILLEGAL_ADDRESS;
665 static void apic_save(QEMUFile *f, void *opaque)
667 APICState *s = opaque;
670 qemu_put_be32s(f, &s->apicbase);
671 qemu_put_8s(f, &s->id);
672 qemu_put_8s(f, &s->arb_id);
673 qemu_put_8s(f, &s->tpr);
674 qemu_put_be32s(f, &s->spurious_vec);
675 qemu_put_8s(f, &s->log_dest);
676 qemu_put_8s(f, &s->dest_mode);
677 for (i = 0; i < 8; i++) {
678 qemu_put_be32s(f, &s->isr[i]);
679 qemu_put_be32s(f, &s->tmr[i]);
680 qemu_put_be32s(f, &s->irr[i]);
682 for (i = 0; i < APIC_LVT_NB; i++) {
683 qemu_put_be32s(f, &s->lvt[i]);
685 qemu_put_be32s(f, &s->esr);
686 qemu_put_be32s(f, &s->icr[0]);
687 qemu_put_be32s(f, &s->icr[1]);
688 qemu_put_be32s(f, &s->divide_conf);
689 qemu_put_be32s(f, &s->count_shift);
690 qemu_put_be32s(f, &s->initial_count);
691 qemu_put_be64s(f, &s->initial_count_load_time);
692 qemu_put_be64s(f, &s->next_time);
695 static int apic_load(QEMUFile *f, void *opaque, int version_id)
697 APICState *s = opaque;
703 /* XXX: what if the base changes? (registered memory regions) */
704 qemu_get_be32s(f, &s->apicbase);
705 qemu_get_8s(f, &s->id);
706 qemu_get_8s(f, &s->arb_id);
707 qemu_get_8s(f, &s->tpr);
708 qemu_get_be32s(f, &s->spurious_vec);
709 qemu_get_8s(f, &s->log_dest);
710 qemu_get_8s(f, &s->dest_mode);
711 for (i = 0; i < 8; i++) {
712 qemu_get_be32s(f, &s->isr[i]);
713 qemu_get_be32s(f, &s->tmr[i]);
714 qemu_get_be32s(f, &s->irr[i]);
716 for (i = 0; i < APIC_LVT_NB; i++) {
717 qemu_get_be32s(f, &s->lvt[i]);
719 qemu_get_be32s(f, &s->esr);
720 qemu_get_be32s(f, &s->icr[0]);
721 qemu_get_be32s(f, &s->icr[1]);
722 qemu_get_be32s(f, &s->divide_conf);
723 qemu_get_be32s(f, &s->count_shift);
724 qemu_get_be32s(f, &s->initial_count);
725 qemu_get_be64s(f, &s->initial_count_load_time);
726 qemu_get_be64s(f, &s->next_time);
730 static void apic_reset(void *opaque)
732 APICState *s = opaque;
736 static CPUReadMemoryFunc *apic_mem_read[3] = {
742 static CPUWriteMemoryFunc *apic_mem_write[3] = {
748 int apic_init(CPUState *env)
752 s = qemu_mallocz(sizeof(APICState));
757 s->id = last_apic_id++;
759 s->apicbase = 0xfee00000 |
760 (s->id ? 0 : MSR_IA32_APICBASE_BSP) | MSR_IA32_APICBASE_ENABLE;
762 /* XXX: mapping more APICs at the same memory location */
763 if (apic_io_memory == 0) {
764 /* NOTE: the APIC is directly connected to the CPU - it is not
765 on the global memory bus. */
766 apic_io_memory = cpu_register_io_memory(0, apic_mem_read,
767 apic_mem_write, NULL);
768 cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000,
771 s->timer = qemu_new_timer(vm_clock, apic_timer, s);
773 register_savevm("apic", 0, 1, apic_save, apic_load, s);
774 qemu_register_reset(apic_reset, s);
776 s->next_apic = first_local_apic;
777 first_local_apic = s;
782 static void ioapic_service(IOAPICState *s)
787 uint8_t delivery_mode;
794 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
797 entry = s->ioredtbl[i];
798 if (!(entry & APIC_LVT_MASKED)) {
799 trig_mode = ((entry >> 15) & 1);
801 dest_mode = (entry >> 11) & 1;
802 delivery_mode = (entry >> 8) & 7;
803 polarity = (entry >> 13) & 1;
804 if (trig_mode == APIC_TRIGGER_EDGE)
806 if (delivery_mode == APIC_DM_EXTINT)
807 vector = pic_read_irq(isa_pic);
809 vector = entry & 0xff;
810 apic_bus_deliver(apic_get_delivery_bitmask(dest, dest_mode),
811 delivery_mode, vector, polarity, trig_mode);
817 void ioapic_set_irq(void *opaque, int vector, int level)
819 IOAPICState *s = opaque;
821 if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
822 uint32_t mask = 1 << vector;
823 uint64_t entry = s->ioredtbl[vector];
825 if ((entry >> 15) & 1) {
826 /* level triggered */
843 static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr)
845 IOAPICState *s = opaque;
852 } else if (addr == 0x10) {
853 switch (s->ioregsel) {
858 val = 0x11 | ((IOAPIC_NUM_PINS - 1) << 16); /* version 0x11 */
864 index = (s->ioregsel - 0x10) >> 1;
865 if (index >= 0 && index < IOAPIC_NUM_PINS) {
867 val = s->ioredtbl[index] >> 32;
869 val = s->ioredtbl[index] & 0xffffffff;
873 printf("I/O APIC read: %08x = %08x\n", s->ioregsel, val);
879 static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
881 IOAPICState *s = opaque;
888 } else if (addr == 0x10) {
890 printf("I/O APIC write: %08x = %08x\n", s->ioregsel, val);
892 switch (s->ioregsel) {
894 s->id = (val >> 24) & 0xff;
900 index = (s->ioregsel - 0x10) >> 1;
901 if (index >= 0 && index < IOAPIC_NUM_PINS) {
902 if (s->ioregsel & 1) {
903 s->ioredtbl[index] &= 0xffffffff;
904 s->ioredtbl[index] |= (uint64_t)val << 32;
906 s->ioredtbl[index] &= ~0xffffffffULL;
907 s->ioredtbl[index] |= val;
915 static void ioapic_save(QEMUFile *f, void *opaque)
917 IOAPICState *s = opaque;
920 qemu_put_8s(f, &s->id);
921 qemu_put_8s(f, &s->ioregsel);
922 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
923 qemu_put_be64s(f, &s->ioredtbl[i]);
927 static int ioapic_load(QEMUFile *f, void *opaque, int version_id)
929 IOAPICState *s = opaque;
935 qemu_get_8s(f, &s->id);
936 qemu_get_8s(f, &s->ioregsel);
937 for (i = 0; i < IOAPIC_NUM_PINS; i++) {
938 qemu_get_be64s(f, &s->ioredtbl[i]);
943 static void ioapic_reset(void *opaque)
945 IOAPICState *s = opaque;
948 memset(s, 0, sizeof(*s));
949 for(i = 0; i < IOAPIC_NUM_PINS; i++)
950 s->ioredtbl[i] = 1 << 16; /* mask LVT */
953 static CPUReadMemoryFunc *ioapic_mem_read[3] = {
959 static CPUWriteMemoryFunc *ioapic_mem_write[3] = {
965 IOAPICState *ioapic_init(void)
970 s = qemu_mallocz(sizeof(IOAPICState));
974 s->id = last_apic_id++;
976 io_memory = cpu_register_io_memory(0, ioapic_mem_read,
977 ioapic_mem_write, s);
978 cpu_register_physical_memory(0xfec00000, 0x1000, io_memory);
980 register_savevm("ioapic", 0, 1, ioapic_save, ioapic_load, s);
981 qemu_register_reset(ioapic_reset, s);