4 * Copyright (c) 2004-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 /* APIC Local Vector Table */
25 #define APIC_LVT_TIMER 0
26 #define APIC_LVT_THERMAL 1
27 #define APIC_LVT_PERFORM 2
28 #define APIC_LVT_LINT0 3
29 #define APIC_LVT_LINT1 4
30 #define APIC_LVT_ERROR 5
33 /* APIC delivery modes */
34 #define APIC_DM_FIXED 0
35 #define APIC_DM_LOWPRI 1
38 #define APIC_DM_INIT 5
39 #define APIC_DM_SIPI 6
40 #define APIC_DM_EXTINT 7
42 #define APIC_TRIGGER_EDGE 0
43 #define APIC_TRIGGER_LEVEL 1
45 #define APIC_LVT_TIMER_PERIODIC (1<<17)
46 #define APIC_LVT_MASKED (1<<16)
47 #define APIC_LVT_LEVEL_TRIGGER (1<<15)
48 #define APIC_LVT_REMOTE_IRR (1<<14)
49 #define APIC_INPUT_POLARITY (1<<13)
50 #define APIC_SEND_PENDING (1<<12)
52 #define ESR_ILLEGAL_ADDRESS (1 << 7)
54 #define APIC_SV_ENABLE (1 << 8)
56 typedef struct APICState {
61 uint32_t spurious_vec;
62 uint32_t isr[8]; /* in service register */
63 uint32_t tmr[8]; /* trigger mode register */
64 uint32_t irr[8]; /* interrupt request register */
65 uint32_t lvt[APIC_LVT_NB];
66 uint32_t esr; /* error register */
71 uint32_t initial_count;
72 int64_t initial_count_load_time, next_time;
76 static int apic_io_memory;
78 void cpu_set_apic_base(CPUState *env, uint64_t val)
80 APICState *s = env->apic_state;
82 printf("cpu_set_apic_base: %016llx\n", val);
84 s->apicbase = (val & 0xfffff000) |
85 (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
86 /* if disabled, cannot be enabled again */
87 if (!(val & MSR_IA32_APICBASE_ENABLE)) {
88 s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
89 env->cpuid_features &= ~CPUID_APIC;
90 s->spurious_vec &= ~APIC_SV_ENABLE;
94 uint64_t cpu_get_apic_base(CPUState *env)
96 APICState *s = env->apic_state;
98 printf("cpu_get_apic_base: %016llx\n", (uint64_t)s->apicbase);
103 /* return -1 if no bit is set */
104 static int get_highest_priority_int(uint32_t *tab)
107 for(i = 0;i < 8; i++) {
109 return i * 32 + ffs(tab[i]) - 1;
115 static inline void set_bit(uint32_t *tab, int index)
119 mask = 1 << (index & 0x1f);
123 static inline void reset_bit(uint32_t *tab, int index)
127 mask = 1 << (index & 0x1f);
131 static int apic_get_ppr(APICState *s)
136 isrv = get_highest_priority_int(s->isr);
147 /* signal the CPU if an irq is pending */
148 static void apic_update_irq(APICState *s)
151 irrv = get_highest_priority_int(s->irr);
154 isrv = get_highest_priority_int(s->isr);
155 /* if the pending irq has less priority, we do not make a new request */
156 if (isrv >= 0 && irrv >= isrv)
158 cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
161 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode)
163 set_bit(s->irr, vector_num);
165 set_bit(s->tmr, vector_num);
167 reset_bit(s->tmr, vector_num);
171 static void apic_eoi(APICState *s)
174 isrv = get_highest_priority_int(s->isr);
177 reset_bit(s->isr, isrv);
181 int apic_get_interrupt(CPUState *env)
183 APICState *s = env->apic_state;
186 /* if the APIC is installed or enabled, we let the 8259 handle the
190 if (!(s->spurious_vec & APIC_SV_ENABLE))
193 /* XXX: spurious IRQ handling */
194 intno = get_highest_priority_int(s->irr);
197 reset_bit(s->irr, intno);
198 set_bit(s->isr, intno);
203 static uint32_t apic_get_current_count(APICState *s)
207 d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >>
209 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
211 val = s->initial_count - (d % (s->initial_count + 1));
213 if (d >= s->initial_count)
216 val = s->initial_count - d;
221 static void apic_timer_update(APICState *s, int64_t current_time)
223 int64_t next_time, d;
225 if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
226 d = (current_time - s->initial_count_load_time) >>
228 if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
229 d = ((d / (s->initial_count + 1)) + 1) * (s->initial_count + 1);
231 if (d >= s->initial_count)
233 d = s->initial_count + 1;
235 next_time = s->initial_count_load_time + (d << s->count_shift);
236 qemu_mod_timer(s->timer, next_time);
237 s->next_time = next_time;
240 qemu_del_timer(s->timer);
244 static void apic_timer(void *opaque)
246 APICState *s = opaque;
248 if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
249 apic_set_irq(s, s->lvt[APIC_LVT_TIMER] & 0xff, APIC_TRIGGER_EDGE);
251 apic_timer_update(s, s->next_time);
254 static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
259 static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
264 static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
268 static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
272 static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
279 env = cpu_single_env;
284 index = (addr >> 4) & 0xff;
289 case 0x03: /* version */
290 val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
297 val = apic_get_ppr(s);
300 val = s->spurious_vec;
303 val = s->isr[index & 7];
306 val = s->tmr[index & 7];
309 val = s->irr[index & 7];
315 val = s->lvt[index - 0x32];
319 val = s->icr[index & 1];
322 val = s->initial_count;
325 val = apic_get_current_count(s);
328 val = s->divide_conf;
331 s->esr |= ESR_ILLEGAL_ADDRESS;
336 printf("APIC read: %08x = %08x\n", (uint32_t)addr, val);
341 static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
347 env = cpu_single_env;
353 printf("APIC write: %08x = %08x\n", (uint32_t)addr, val);
356 index = (addr >> 4) & 0xff;
368 s->spurious_vec = val & 0x1ff;
372 s->icr[index & 1] = val;
376 int n = index - 0x32;
378 if (n == APIC_LVT_TIMER)
379 apic_timer_update(s, qemu_get_clock(vm_clock));
383 s->initial_count = val;
384 s->initial_count_load_time = qemu_get_clock(vm_clock);
385 apic_timer_update(s, s->initial_count_load_time);
390 s->divide_conf = val & 0xb;
391 v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
392 s->count_shift = (v + 1) & 7;
396 s->esr |= ESR_ILLEGAL_ADDRESS;
403 static CPUReadMemoryFunc *apic_mem_read[3] = {
409 static CPUWriteMemoryFunc *apic_mem_write[3] = {
415 int apic_init(CPUState *env)
420 s = malloc(sizeof(APICState));
423 memset(s, 0, sizeof(*s));
426 s->apicbase = 0xfee00000 |
427 MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE;
428 for(i = 0; i < APIC_LVT_NB; i++)
429 s->lvt[i] = 1 << 16; /* mask LVT */
430 s->spurious_vec = 0xff;
432 if (apic_io_memory == 0) {
433 /* NOTE: the APIC is directly connected to the CPU - it is not
434 on the global memory bus. */
435 apic_io_memory = cpu_register_io_memory(0, apic_mem_read,
436 apic_mem_write, NULL);
437 cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000, apic_io_memory);
439 s->timer = qemu_new_timer(vm_clock, apic_timer, s);