2 * QEMU Ultrasparc APB PCI host
4 * Copyright (c) 2006 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 typedef target_phys_addr_t pci_addr_t;
28 typedef PCIHostState APBState;
30 static void pci_apb_config_writel (void *opaque, target_phys_addr_t addr,
36 for (i = 11; i < 32; i++) {
37 if ((val & (1 << i)) != 0)
40 s->config_reg = (1 << 16) | (val & 0x7FC) | (i << 11);
43 static uint32_t pci_apb_config_readl (void *opaque,
44 target_phys_addr_t addr)
50 devfn = (s->config_reg >> 8) & 0xFF;
51 val = (1 << (devfn >> 3)) | ((devfn & 0x07) << 8) | (s->config_reg & 0xFC);
55 static CPUWriteMemoryFunc *pci_apb_config_write[] = {
56 &pci_apb_config_writel,
57 &pci_apb_config_writel,
58 &pci_apb_config_writel,
61 static CPUReadMemoryFunc *pci_apb_config_read[] = {
62 &pci_apb_config_readl,
63 &pci_apb_config_readl,
64 &pci_apb_config_readl,
67 static void apb_config_writel (void *opaque, target_phys_addr_t addr,
72 switch (addr & 0x3f) {
73 case 0x00: // Control/Status
76 case 0x20: // Diagnostic
77 case 0x28: // Target address space
84 static uint32_t apb_config_readl (void *opaque,
85 target_phys_addr_t addr)
90 switch (addr & 0x3f) {
91 case 0x00: // Control/Status
94 case 0x20: // Diagnostic
95 case 0x28: // Target address space
104 static CPUWriteMemoryFunc *apb_config_write[] = {
110 static CPUReadMemoryFunc *apb_config_read[] = {
116 static CPUWriteMemoryFunc *pci_apb_write[] = {
117 &pci_host_data_writeb,
118 &pci_host_data_writew,
119 &pci_host_data_writel,
122 static CPUReadMemoryFunc *pci_apb_read[] = {
123 &pci_host_data_readb,
124 &pci_host_data_readw,
125 &pci_host_data_readl,
128 static void pci_apb_iowriteb (void *opaque, target_phys_addr_t addr,
131 cpu_outb(NULL, addr & 0xffff, val);
134 static void pci_apb_iowritew (void *opaque, target_phys_addr_t addr,
137 cpu_outw(NULL, addr & 0xffff, val);
140 static void pci_apb_iowritel (void *opaque, target_phys_addr_t addr,
143 cpu_outl(NULL, addr & 0xffff, val);
146 static uint32_t pci_apb_ioreadb (void *opaque, target_phys_addr_t addr)
150 val = cpu_inb(NULL, addr & 0xffff);
154 static uint32_t pci_apb_ioreadw (void *opaque, target_phys_addr_t addr)
158 val = cpu_inw(NULL, addr & 0xffff);
162 static uint32_t pci_apb_ioreadl (void *opaque, target_phys_addr_t addr)
166 val = cpu_inl(NULL, addr & 0xffff);
170 static CPUWriteMemoryFunc *pci_apb_iowrite[] = {
176 static CPUReadMemoryFunc *pci_apb_ioread[] = {
182 /* ??? This is probably wrong. */
183 static void pci_apb_set_irq(PCIDevice *d, void *pic, int irq_num, int level)
185 pic_set_irq_new(pic, d->config[PCI_INTERRUPT_LINE], level);
188 PCIBus *pci_apb_init(target_ulong special_base, target_ulong mem_base,
193 int pci_mem_config, pci_mem_data, apb_config, pci_ioport;
195 s = qemu_mallocz(sizeof(APBState));
196 /* Ultrasparc APB main bus */
197 s->bus = pci_register_bus(pci_apb_set_irq, pic, 0);
199 pci_mem_config = cpu_register_io_memory(0, pci_apb_config_read,
200 pci_apb_config_write, s);
201 apb_config = cpu_register_io_memory(0, apb_config_read,
202 apb_config_write, s);
203 pci_mem_data = cpu_register_io_memory(0, pci_apb_read,
205 pci_ioport = cpu_register_io_memory(0, pci_apb_ioread,
208 cpu_register_physical_memory(special_base + 0x2000ULL, 0x40, apb_config);
209 cpu_register_physical_memory(special_base + 0x1000000ULL, 0x10, pci_mem_config);
210 cpu_register_physical_memory(special_base + 0x2000000ULL, 0x10000, pci_ioport);
211 cpu_register_physical_memory(mem_base, 0x10000000, pci_mem_data); // XXX size should be 4G-prom
213 d = pci_register_device(s->bus, "Advanced PCI Bus", sizeof(PCIDevice),
215 d->config[0x00] = 0x8e; // vendor_id : Sun
216 d->config[0x01] = 0x10;
217 d->config[0x02] = 0x00; // device_id
218 d->config[0x03] = 0xa0;
219 d->config[0x04] = 0x06; // command = bus master, pci mem
220 d->config[0x05] = 0x00;
221 d->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
222 d->config[0x07] = 0x03; // status = medium devsel
223 d->config[0x08] = 0x00; // revision
224 d->config[0x09] = 0x00; // programming i/f
225 d->config[0x0A] = 0x00; // class_sub = pci host
226 d->config[0x0B] = 0x06; // class_base = PCI_bridge
227 d->config[0x0D] = 0x10; // latency_timer
228 d->config[0x0E] = 0x00; // header_type