2 * MUSB OTG driver core code
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
68 * RESULT: one device may be perceived as blocking another one.
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific informarion
87 * (plus recentrly, SOC or family details)
89 * Most of the conditional compilation will (someday) vanish.
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/init.h>
97 #include <linux/list.h>
98 #include <linux/kobject.h>
99 #include <linux/platform_device.h>
100 #include <linux/io.h>
103 #include <mach/hardware.h>
104 #include <mach/memory.h>
105 #include <asm/mach-types.h>
108 #include "musb_core.h"
111 #ifdef CONFIG_ARCH_DAVINCI
115 static struct musb *the_musb;
116 static struct musb_ctx ctx;
118 #ifndef CONFIG_MUSB_PIO_ONLY
119 static int __initdata use_dma = 1;
121 static int __initdata use_dma;
123 module_param(use_dma, bool, 0);
124 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
126 unsigned musb_debug = 0;
127 module_param_named(debug, musb_debug, uint, S_IRUGO | S_IWUSR);
128 MODULE_PARM_DESC(debug, "Debug message level. Default = 0");
130 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
131 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
133 #define MUSB_VERSION "6.0"
135 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
137 #define MUSB_DRIVER_NAME "musb_hdrc"
138 const char musb_driver_name[] = MUSB_DRIVER_NAME;
140 MODULE_DESCRIPTION(DRIVER_INFO);
141 MODULE_AUTHOR(DRIVER_AUTHOR);
142 MODULE_LICENSE("GPL");
143 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
145 static inline int musb_verify_charger(void __iomem *addr)
149 /* Reset the transceiver */
150 r = musb_ulpi_readb(addr, ISP1704_FUNC_CTRL);
151 r |= ISP1704_FUNC_CTRL_RESET;
152 musb_ulpi_writeb(addr, ISP1704_FUNC_CTRL, r);
155 /* Set normal mode */
156 r &= ~(ISP1704_FUNC_CTRL_RESET | (3 << ISP1704_FUNC_CTRL_OPMODE));
157 musb_ulpi_writeb(addr, ISP1704_FUNC_CTRL, r);
159 /* Clear the DP and DM pull-down bits */
160 r = musb_ulpi_readb(addr, ISP1704_OTG_CTRL);
161 r &= ~(ISP1704_OTG_CTRL_DP_PULLDOWN | ISP1704_OTG_CTRL_DM_PULLDOWN);
162 musb_ulpi_writeb(addr, ISP1704_OTG_CTRL, r);
164 /* Enable strong pull-up on DP (1.5K) and reset */
165 r = musb_ulpi_readb(addr, ISP1704_FUNC_CTRL);
166 r |= ISP1704_FUNC_CTRL_TERMSELECT | ISP1704_FUNC_CTRL_RESET;
167 musb_ulpi_writeb(addr, ISP1704_FUNC_CTRL, r);
170 /* Read the line state */
171 if (musb_ulpi_readb(addr, ISP1704_DEBUG)) {
172 /* Is it a charger or PS2 connection */
174 /* Enable weak pull-up resistor on DP */
175 r = musb_ulpi_readb(addr, ISP1704_PWR_CTRL);
176 r |= ISP1704_PWR_CTRL_DP_WKPU_EN;
177 musb_ulpi_writeb(addr, ISP1704_PWR_CTRL, r);
179 /* Disable strong pull-up on DP (1.5K) */
180 r = musb_ulpi_readb(addr, ISP1704_FUNC_CTRL);
181 r &= ~ISP1704_FUNC_CTRL_TERMSELECT;
182 musb_ulpi_writeb(addr, ISP1704_FUNC_CTRL, r);
184 /* Enable weak pull-down resistor on DM */
185 r = musb_ulpi_readb(addr, ISP1704_OTG_CTRL);
186 r |= ISP1704_OTG_CTRL_DM_PULLDOWN;
187 musb_ulpi_writeb(addr, ISP1704_OTG_CTRL, r);
189 /* It's a charger if the line states are clear */
190 if (!(musb_ulpi_readb(addr, ISP1704_DEBUG)))
193 /* Disable weak pull-up resistor on DP */
194 r = musb_ulpi_readb(addr, ISP1704_PWR_CTRL);
195 r &= ~ISP1704_PWR_CTRL_DP_WKPU_EN;
196 musb_ulpi_writeb(addr, ISP1704_PWR_CTRL, r);
200 /* Disable strong pull-up on DP (1.5K) */
201 r = musb_ulpi_readb(addr, ISP1704_FUNC_CTRL);
202 r &= ~ISP1704_FUNC_CTRL_TERMSELECT;
203 musb_ulpi_writeb(addr, ISP1704_FUNC_CTRL, r);
209 /* Bad connections with the charger may lead into the transceiver
210 * thinking that a device was just connected. We can wait for 5 ms to
211 * ensure that these cases will generate SUSPEND interrupt and not
212 * RESET. Reading and writing to the transceiver may still cause
213 * RESET interrupts. We mask out RESET/RESUME interrupts to
216 static int check_charger;
217 static int musb_charger_detect(struct musb *musb)
219 unsigned long timeout;
226 /* Using ulpi with musb is quite tricky. The following code
227 * was written based on the ulpi application note.
229 * The order of reads and writes and quite important, don't
230 * change it unless you really know what you're doing
233 switch(musb->xceiv->state) {
234 case OTG_STATE_B_IDLE:
235 /* we always reset transceiver */
238 /* HACK: ULPI tends to get stuck when booting with
239 * the cable connected
241 r = musb_readb(musb->mregs, MUSB_DEVCTL);
242 if ((r & MUSB_DEVCTL_VBUS)
243 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
244 musb_save_ctx_and_suspend(&musb->g, 0);
245 musb_restore_ctx_and_resume(&musb->g);
246 if (musb->board && musb->board->set_pm_limits)
247 musb->board->set_pm_limits(
248 musb->controller, 1);
251 /* disable RESET and RESUME interrupts */
252 r = musb_readb(musb->mregs, MUSB_INTRUSBE);
253 r &= ~(MUSB_INTR_RESUME | MUSB_INTR_RESET);
254 musb_writeb(musb->mregs, MUSB_INTRUSBE, r);
256 if (musb->board && musb->board->xceiv_reset)
257 musb->board->xceiv_reset();
259 /* then we resume to sync with controller */
260 r = musb_readb(musb->mregs, MUSB_POWER);
261 musb_writeb(musb->mregs, MUSB_POWER,
262 r | MUSB_POWER_RESUME);
264 musb_writeb(musb->mregs, MUSB_POWER,
265 r & ~MUSB_POWER_RESUME);
267 /* now we set SW control bit in PWR_CTRL register */
268 musb_ulpi_writeb(musb->mregs, ISP1704_PWR_CTRL,
269 ISP1704_PWR_CTRL_SWCTRL);
271 r = musb_ulpi_readb(musb->mregs, ISP1704_PWR_CTRL);
272 r |= (ISP1704_PWR_CTRL_SWCTRL | ISP1704_PWR_CTRL_DPVSRC_EN);
274 /* and finally enable manual charger detection */
275 musb_ulpi_writeb(musb->mregs, ISP1704_PWR_CTRL, r);
278 timeout = jiffies + msecs_to_jiffies(300);
279 while (!time_after(jiffies, timeout)) {
280 /* Check if there is a charger */
281 vdat = !!(musb_ulpi_readb(musb->mregs, ISP1704_PWR_CTRL)
282 & ISP1704_PWR_CTRL_VDAT_DET);
287 vdat = musb_verify_charger(musb->mregs);
289 r &= ~ISP1704_PWR_CTRL_DPVSRC_EN;
291 /* Clear DPVSRC_EN, otherwise usb communication doesn't work */
292 musb_ulpi_writeb(musb->mregs, ISP1704_PWR_CTRL, r);
300 /* enable interrupts */
301 musb_writeb(musb->mregs, MUSB_INTRUSBE, ctx.intrusbe);
303 /* Make sure the communication starts normally */
304 r = musb_readb(musb->mregs, MUSB_POWER);
305 musb_writeb(musb->mregs, MUSB_POWER,
306 r | MUSB_POWER_RESUME);
308 musb_writeb(musb->mregs, MUSB_POWER,
309 r & ~MUSB_POWER_RESUME);
310 if (vdat && musb->xceiv->state != OTG_STATE_B_IDLE) {
313 otg_set_suspend(musb->xceiv, 1);
316 musb->is_charger = vdat;
322 /*-------------------------------------------------------------------------*/
324 static inline struct musb *dev_to_musb(struct device *dev)
326 #ifdef CONFIG_USB_MUSB_HDRC_HCD
327 /* usbcore insists dev->driver_data is a "struct hcd *" */
328 return hcd_to_musb(dev_get_drvdata(dev));
330 return dev_get_drvdata(dev);
334 /*-------------------------------------------------------------------------*/
336 #if !defined(CONFIG_USB_TUSB6010) && !defined(CONFIG_BLACKFIN)
339 * Load an endpoint's FIFO
341 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
343 void __iomem *fifo = hw_ep->fifo;
347 DBG_nonverb(4, "%cX ep%d fifo %p count %d buf %p\n",
348 'T', hw_ep->epnum, fifo, len, src);
350 /* we can't assume unaligned reads work */
351 if (likely((0x01 & (unsigned long) src) == 0)) {
354 /* best case is 32bit-aligned source address */
355 if ((0x02 & (unsigned long) src) == 0) {
357 writesl(fifo, src + index, len >> 2);
358 index += len & ~0x03;
361 musb_writew(fifo, 0, *(u16 *)&src[index]);
366 writesw(fifo, src + index, len >> 1);
367 index += len & ~0x01;
371 musb_writeb(fifo, 0, src[index]);
374 writesb(fifo, src, len);
379 * Unload an endpoint's FIFO
381 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
383 void __iomem *fifo = hw_ep->fifo;
385 DBG_nonverb(4, "%cX ep%d fifo %p count %d buf %p\n",
386 'R', hw_ep->epnum, fifo, len, dst);
388 /* we can't assume unaligned writes work */
389 if (likely((0x01 & (unsigned long) dst) == 0)) {
392 /* best case is 32bit-aligned destination address */
393 if ((0x02 & (unsigned long) dst) == 0) {
395 readsl(fifo, dst, len >> 2);
399 *(u16 *)&dst[index] = musb_readw(fifo, 0);
404 readsw(fifo, dst, len >> 1);
409 dst[index] = musb_readb(fifo, 0);
412 readsb(fifo, dst, len);
416 #endif /* normal PIO */
419 /*-------------------------------------------------------------------------*/
421 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
422 static const u8 musb_test_packet[53] = {
423 /* implicit SYNC then DATA0 to start */
426 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
428 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
430 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
431 /* JJJJJJJKKKKKKK x8 */
432 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
434 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
435 /* JKKKKKKK x10, JK */
436 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
438 /* implicit CRC16 then EOP to end */
441 void musb_load_testpacket(struct musb *musb)
443 void __iomem *regs = musb->endpoints[0].regs;
445 musb_ep_select(musb->mregs, 0);
446 musb_write_fifo(musb->control_ep,
447 sizeof(musb_test_packet), musb_test_packet);
448 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
451 /*-------------------------------------------------------------------------*/
453 const char *otg_state_string(struct musb *musb)
455 switch (musb->xceiv->state) {
456 case OTG_STATE_A_IDLE: return "a_idle";
457 case OTG_STATE_A_WAIT_VRISE: return "a_wait_vrise";
458 case OTG_STATE_A_WAIT_BCON: return "a_wait_bcon";
459 case OTG_STATE_A_HOST: return "a_host";
460 case OTG_STATE_A_SUSPEND: return "a_suspend";
461 case OTG_STATE_A_PERIPHERAL: return "a_peripheral";
462 case OTG_STATE_A_WAIT_VFALL: return "a_wait_vfall";
463 case OTG_STATE_A_VBUS_ERR: return "a_vbus_err";
464 case OTG_STATE_B_IDLE: return "b_idle";
465 case OTG_STATE_B_SRP_INIT: return "b_srp_init";
466 case OTG_STATE_B_PERIPHERAL: return "b_peripheral";
467 case OTG_STATE_B_WAIT_ACON: return "b_wait_acon";
468 case OTG_STATE_B_HOST: return "b_host";
469 default: return "UNDEFINED";
473 #ifdef CONFIG_USB_MUSB_OTG
476 * See also USB_OTG_1-3.pdf 6.6.5 Timers
477 * REVISIT: Are the other timers done in the hardware?
479 #define TB_ASE0_BRST 100 /* Min 3.125 ms */
482 * Handles OTG hnp timeouts, such as b_ase0_brst
484 void musb_otg_timer_func(unsigned long data)
486 struct musb *musb = (struct musb *)data;
489 spin_lock_irqsave(&musb->lock, flags);
490 switch (musb->xceiv->state) {
491 case OTG_STATE_B_WAIT_ACON:
492 DBG(1, "HNP: b_wait_acon timeout; back to b_peripheral\n");
493 musb_g_disconnect(musb);
494 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
497 case OTG_STATE_A_WAIT_BCON:
498 DBG(1, "HNP: a_wait_bcon timeout; back to a_host\n");
502 DBG(1, "HNP: Unhandled mode %s\n", otg_state_string(musb));
504 musb->ignore_disconnect = 0;
505 spin_unlock_irqrestore(&musb->lock, flags);
508 static DEFINE_TIMER(musb_otg_timer, musb_otg_timer_func, 0, 0);
511 * Stops the B-device HNP state. Caller must take care of locking.
513 void musb_hnp_stop(struct musb *musb)
515 struct usb_hcd *hcd = musb_to_hcd(musb);
516 void __iomem *mbase = musb->mregs;
519 switch (musb->xceiv->state) {
520 case OTG_STATE_A_PERIPHERAL:
521 case OTG_STATE_A_WAIT_VFALL:
522 case OTG_STATE_A_WAIT_BCON:
523 DBG(1, "HNP: Switching back to A-host\n");
524 musb_g_disconnect(musb);
525 musb->xceiv->state = OTG_STATE_A_IDLE;
529 case OTG_STATE_B_HOST:
530 DBG(1, "HNP: Disabling HR\n");
531 hcd->self.is_b_host = 0;
532 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
534 reg = musb_readb(mbase, MUSB_POWER);
535 reg |= MUSB_POWER_SUSPENDM;
536 musb_writeb(mbase, MUSB_POWER, reg);
537 /* REVISIT: Start SESSION_REQUEST here? */
540 DBG(1, "HNP: Stopping in unknown state %s\n",
541 otg_state_string(musb));
545 * When returning to A state after HNP, avoid hub_port_rebounce(),
546 * which cause occasional OPT A "Did not receive reset after connect"
549 musb->port1_status &=
550 ~(1 << USB_PORT_FEAT_C_CONNECTION);
556 * Interrupt Service Routine to record USB "global" interrupts.
557 * Since these do not happen often and signify things of
558 * paramount importance, it seems OK to check them individually;
559 * the order of the tests is specified in the manual
561 * @param musb instance pointer
562 * @param int_usb register contents
567 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
570 irqreturn_t handled = IRQ_NONE;
571 void __iomem *mbase = musb->mregs;
573 u8 testmode = musb_readb(musb->mregs, MUSB_TESTMODE);
575 DBG(3, "<== State=%s Testmode=%02x Power=%02x, DevCtl=%02x, int_usb=0x%x\n",
576 otg_state_string(musb), testmode, power, devctl, int_usb);
578 /* in host mode, the peripheral may issue remote wakeup.
579 * in peripheral mode, the host may resume the link.
580 * spurious RESUME irqs happen too, paired with SUSPEND.
582 if (int_usb & MUSB_INTR_RESUME) {
583 handled = IRQ_HANDLED;
584 DBG(3, "RESUME (%s)\n", otg_state_string(musb));
586 if (devctl & MUSB_DEVCTL_HM) {
587 #ifdef CONFIG_USB_MUSB_HDRC_HCD
588 switch (musb->xceiv->state) {
589 case OTG_STATE_A_SUSPEND:
590 /* remote wakeup? later, GetPortStatus
591 * will stop RESUME signaling
594 if (power & MUSB_POWER_SUSPENDM) {
596 musb->int_usb &= ~MUSB_INTR_SUSPEND;
597 DBG(2, "Spurious SUSPENDM\n");
601 power &= ~MUSB_POWER_SUSPENDM;
602 musb_writeb(mbase, MUSB_POWER,
603 power | MUSB_POWER_RESUME);
605 musb->port1_status |=
606 (USB_PORT_STAT_C_SUSPEND << 16)
607 | MUSB_PORT_STAT_RESUME;
608 musb->rh_timer = jiffies
609 + msecs_to_jiffies(20);
611 musb->xceiv->state = OTG_STATE_A_HOST;
613 usb_hcd_resume_root_hub(musb_to_hcd(musb));
615 case OTG_STATE_B_WAIT_ACON:
616 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
621 WARNING("bogus %s RESUME (%s)\n",
623 otg_state_string(musb));
627 switch (musb->xceiv->state) {
628 #ifdef CONFIG_USB_MUSB_HDRC_HCD
629 case OTG_STATE_A_SUSPEND:
630 /* possibly DISCONNECT is upcoming */
631 musb->xceiv->state = OTG_STATE_A_HOST;
632 usb_hcd_resume_root_hub(musb_to_hcd(musb));
635 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
636 case OTG_STATE_B_WAIT_ACON:
637 case OTG_STATE_B_PERIPHERAL:
638 /* disconnect while suspended? we may
639 * not get a disconnect irq...
641 if ((devctl & MUSB_DEVCTL_VBUS)
642 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
644 musb->int_usb |= MUSB_INTR_DISCONNECT;
645 musb->int_usb &= ~MUSB_INTR_SUSPEND;
650 case OTG_STATE_B_IDLE:
651 musb->int_usb &= ~MUSB_INTR_SUSPEND;
655 WARNING("bogus %s RESUME (%s)\n",
657 otg_state_string(musb));
662 #ifdef CONFIG_USB_MUSB_HDRC_HCD
663 /* see manual for the order of the tests */
664 if (int_usb & MUSB_INTR_SESSREQ) {
665 DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(musb));
667 /* IRQ arrives from ID pin sense or (later, if VBUS power
668 * is removed) SRP. responses are time critical:
669 * - turn on VBUS (with silicon-specific mechanism)
670 * - go through A_WAIT_VRISE
671 * - ... to A_WAIT_BCON.
672 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
673 * NOTE : Spurious SESS_REQ int's detected, which should
674 * be discarded silently.
676 if ((devctl & MUSB_DEVCTL_VBUS)
677 && !(devctl & MUSB_DEVCTL_BDEVICE)) {
678 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
679 musb->ep0_stage = MUSB_EP0_START;
680 musb->xceiv->state = OTG_STATE_A_IDLE;
682 musb_set_vbus(musb, 1);
684 DBG(5,"discarding SESSREQ INT: VBUS < SessEnd\n");
687 handled = IRQ_HANDLED;
690 if (int_usb & MUSB_INTR_VBUSERROR) {
693 /* During connection as an A-Device, we may see a short
694 * current spikes causing voltage drop, because of cable
695 * and peripheral capacitance combined with vbus draw.
696 * (So: less common with truly self-powered devices, where
697 * vbus doesn't act like a power supply.)
699 * Such spikes are short; usually less than ~500 usec, max
700 * of ~2 msec. That is, they're not sustained overcurrent
701 * errors, though they're reported using VBUSERROR irqs.
703 * Workarounds: (a) hardware: use self powered devices.
704 * (b) software: ignore non-repeated VBUS errors.
706 * REVISIT: do delays from lots of DEBUG_KERNEL checks
707 * make trouble here, keeping VBUS < 4.4V ?
709 switch (musb->xceiv->state) {
710 case OTG_STATE_A_HOST:
711 /* recovery is dicey once we've gotten past the
712 * initial stages of enumeration, but if VBUS
713 * stayed ok at the other end of the link, and
714 * another reset is due (at least for high speed,
715 * to redo the chirp etc), it might work OK...
717 case OTG_STATE_A_WAIT_BCON:
718 case OTG_STATE_A_WAIT_VRISE:
719 if (musb->vbuserr_retry) {
720 musb->vbuserr_retry--;
722 devctl |= MUSB_DEVCTL_SESSION;
723 musb_writeb(mbase, MUSB_DEVCTL, devctl);
725 musb->port1_status |=
726 (1 << USB_PORT_FEAT_OVER_CURRENT)
727 | (1 << USB_PORT_FEAT_C_OVER_CURRENT);
734 DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
735 otg_state_string(musb),
738 switch (devctl & MUSB_DEVCTL_VBUS) {
739 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
740 s = "<SessEnd"; break;
741 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
742 s = "<AValid"; break;
743 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
744 s = "<VBusValid"; break;
745 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
749 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
752 /* go through A_WAIT_VFALL then start a new session */
754 musb_set_vbus(musb, 0);
755 handled = IRQ_HANDLED;
758 if (int_usb & MUSB_INTR_SUSPEND) {
759 DBG(1, "SUSPEND (%s) devctl %02x power %02x\n",
760 otg_state_string(musb), devctl, power);
761 handled = IRQ_HANDLED;
763 switch (musb->xceiv->state) {
764 #ifdef CONFIG_USB_MUSB_OTG
765 case OTG_STATE_A_PERIPHERAL:
767 * We cannot stop HNP here, devctl BDEVICE might be
772 case OTG_STATE_B_IDLE:
773 if (!musb->is_active)
775 case OTG_STATE_B_PERIPHERAL:
776 musb_g_suspend(musb);
777 musb->is_active = is_otg_enabled(musb)
778 && musb->xceiv->gadget->b_hnp_enable;
779 if (musb->is_active) {
780 #ifdef CONFIG_USB_MUSB_OTG
781 musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
782 DBG(1, "HNP: Setting timer for b_ase0_brst\n");
783 musb_otg_timer.data = (unsigned long)musb;
784 mod_timer(&musb_otg_timer, jiffies
785 + msecs_to_jiffies(TB_ASE0_BRST));
789 case OTG_STATE_A_WAIT_BCON:
790 if (musb->a_wait_bcon != 0)
791 musb_platform_try_idle(musb, jiffies
792 + msecs_to_jiffies(musb->a_wait_bcon));
794 case OTG_STATE_A_HOST:
795 musb->xceiv->state = OTG_STATE_A_SUSPEND;
796 musb->is_active = is_otg_enabled(musb)
797 && musb->xceiv->host->b_hnp_enable;
799 case OTG_STATE_B_HOST:
800 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
801 DBG(1, "REVISIT: SUSPEND as B_HOST\n");
804 /* "should not happen" */
810 if (int_usb & MUSB_INTR_CONNECT) {
811 struct usb_hcd *hcd = musb_to_hcd(musb);
813 handled = IRQ_HANDLED;
815 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
817 musb->ep0_stage = MUSB_EP0_START;
819 #ifdef CONFIG_USB_MUSB_OTG
820 /* flush endpoints when transitioning from Device Mode */
821 if (is_peripheral_active(musb)) {
822 /* REVISIT HNP; just force disconnect */
824 musb_writew(mbase, MUSB_INTRTXE, musb->epmask);
825 musb_writew(mbase, MUSB_INTRRXE, musb->epmask & 0xfffe);
826 musb_writeb(mbase, MUSB_INTRUSBE, 0xf7);
828 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
829 |USB_PORT_STAT_HIGH_SPEED
830 |USB_PORT_STAT_ENABLE
832 musb->port1_status |= USB_PORT_STAT_CONNECTION
833 |(USB_PORT_STAT_C_CONNECTION << 16);
835 /* high vs full speed is just a guess until after reset */
836 if (devctl & MUSB_DEVCTL_LSDEV)
837 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
840 usb_hcd_poll_rh_status(hcd);
842 usb_hcd_resume_root_hub(hcd);
846 /* indicate new connection to OTG machine */
847 switch (musb->xceiv->state) {
848 case OTG_STATE_B_PERIPHERAL:
849 if (int_usb & MUSB_INTR_SUSPEND) {
850 DBG(1, "HNP: SUSPEND+CONNECT, now b_host\n");
851 musb->xceiv->state = OTG_STATE_B_HOST;
852 hcd->self.is_b_host = 1;
853 int_usb &= ~MUSB_INTR_SUSPEND;
855 DBG(1, "CONNECT as b_peripheral???\n");
857 case OTG_STATE_B_WAIT_ACON:
858 DBG(1, "HNP: Waiting to switch to b_host state\n");
859 musb->xceiv->state = OTG_STATE_B_HOST;
860 hcd->self.is_b_host = 1;
863 if ((devctl & MUSB_DEVCTL_VBUS)
864 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
865 musb->xceiv->state = OTG_STATE_A_HOST;
866 hcd->self.is_b_host = 0;
870 DBG(1, "CONNECT (%s) devctl %02x\n",
871 otg_state_string(musb), devctl);
873 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
875 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
876 DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n",
877 otg_state_string(musb),
878 MUSB_MODE(musb), devctl);
879 handled = IRQ_HANDLED;
881 switch (musb->xceiv->state) {
882 #ifdef CONFIG_USB_MUSB_HDRC_HCD
883 case OTG_STATE_A_HOST:
884 case OTG_STATE_A_SUSPEND:
885 usb_hcd_resume_root_hub(musb_to_hcd(musb));
886 musb_root_disconnect(musb);
887 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb))
888 musb_platform_try_idle(musb, jiffies
889 + msecs_to_jiffies(musb->a_wait_bcon));
892 #ifdef CONFIG_USB_MUSB_OTG
893 case OTG_STATE_B_HOST:
896 case OTG_STATE_A_PERIPHERAL:
898 musb_root_disconnect(musb);
900 case OTG_STATE_B_WAIT_ACON:
903 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
904 case OTG_STATE_B_PERIPHERAL:
905 case OTG_STATE_B_IDLE:
906 /* Workaround for a problem of Vbus quickly dropping
907 * during Certification tests.
909 * Undo the workaround on disconnect
912 /* Disable suspend so we can write to ULPI */
913 r = musb_readb(musb->mregs, MUSB_POWER);
914 musb_writeb(musb->mregs, MUSB_POWER,
915 r & ~MUSB_POWER_ENSUSPEND);
916 musb_ulpi_writeb(musb->mregs,
917 ISP1704_USB_INTFALL, 0x1f);
918 musb_ulpi_writeb(musb->mregs,
919 ISP1704_USB_INTRISE, 0x1f);
920 musb_writeb(musb->mregs, MUSB_POWER,
921 r | MUSB_POWER_ENSUSPEND);
923 musb_g_disconnect(musb);
924 /** UGLY UGLY HACK: Windows problems with multiple
927 * This is necessary to notify gadget driver this was
928 * a physical disconnection and not only a port reset.
930 if (musb->gadget_driver->vbus_disconnect)
931 musb->gadget_driver->vbus_disconnect(&musb->g);
936 WARNING("unhandled DISCONNECT transition (%s)\n",
937 otg_state_string(musb));
942 /* mentor saves a bit: bus reset and babble share the same irq.
943 * only host sees babble; only peripheral sees bus reset.
945 if (int_usb & MUSB_INTR_RESET) {
946 handled = IRQ_HANDLED;
947 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
949 * Looks like non-HS BABBLE can be ignored, but
950 * HS BABBLE is an error condition. For HS the solution
951 * is to avoid babble in the first place and fix what
952 * caused BABBLE. When HS BABBLE happens we can only
955 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
956 DBG(1, "BABBLE devctl: %02x\n", devctl);
958 ERR("Stopping host session -- babble\n");
959 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
961 } else if (is_peripheral_capable()) {
962 DBG(1, "BUS RESET as %s\n", otg_state_string(musb));
963 switch (musb->xceiv->state) {
964 #ifdef CONFIG_USB_OTG
965 case OTG_STATE_A_SUSPEND:
966 /* We need to ignore disconnect on suspend
967 * otherwise tusb 2.0 won't reconnect after a
968 * power cycle, which breaks otg compliance.
970 musb->ignore_disconnect = 1;
973 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
974 DBG(1, "HNP: Setting timer as %s\n",
975 otg_state_string(musb));
976 musb_otg_timer.data = (unsigned long)musb;
977 mod_timer(&musb_otg_timer, jiffies
978 + msecs_to_jiffies(100));
980 case OTG_STATE_A_PERIPHERAL:
983 case OTG_STATE_B_WAIT_ACON:
984 DBG(1, "HNP: RESET (%s), to b_peripheral\n",
985 otg_state_string(musb));
986 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
990 case OTG_STATE_B_IDLE:
991 /* Workaround the charger detection problems */
992 if ((devctl & MUSB_DEVCTL_VBUS)
993 != (3 << MUSB_DEVCTL_VBUS_SHIFT))
997 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
999 case OTG_STATE_B_PERIPHERAL:
1000 /* Workaround for a problem of Vbus quickly dropping
1001 * during Certification tests.
1003 * The guess is that vbus drops due to the circuitry
1004 * for overcurrent protection and that makes transceiver
1005 * think VBUS is not valid anymore. Transceiver will
1006 * then send an RXCMD to PHY which will cause it to
1007 * disconnect from the bus even though we disable the
1010 musb_ulpi_writeb(musb->mregs,
1011 ISP1704_USB_INTFALL, 0x1d);
1012 musb_ulpi_writeb(musb->mregs,
1013 ISP1704_USB_INTRISE, 0x1d);
1018 DBG(1, "Unhandled BUS RESET as %s\n",
1019 otg_state_string(musb));
1025 /* REVISIT ... this would be for multiplexing periodic endpoints, or
1026 * supporting transfer phasing to prevent exceeding ISO bandwidth
1027 * limits of a given frame or microframe.
1029 * It's not needed for peripheral side, which dedicates endpoints;
1030 * though it _might_ use SOF irqs for other purposes.
1032 * And it's not currently needed for host side, which also dedicates
1033 * endpoints, relies on TX/RX interval registers, and isn't claimed
1034 * to support ISO transfers yet.
1036 if (int_usb & MUSB_INTR_SOF) {
1037 void __iomem *mbase = musb->mregs;
1038 struct musb_hw_ep *ep;
1042 DBG(6, "START_OF_FRAME\n");
1043 handled = IRQ_HANDLED;
1045 /* start any periodic Tx transfers waiting for current frame */
1046 frame = musb_readw(mbase, MUSB_FRAME);
1047 ep = musb->endpoints;
1048 for (epnum = 1; (epnum < musb->nr_endpoints)
1049 && (musb->epmask >= (1 << epnum));
1052 * FIXME handle framecounter wraps (12 bits)
1053 * eliminate duplicated StartUrb logic
1055 if (ep->dwWaitFrame >= frame) {
1056 ep->dwWaitFrame = 0;
1057 pr_debug("SOF --> periodic TX%s on %d\n",
1058 ep->tx_channel ? " DMA" : "",
1060 if (!ep->tx_channel)
1061 musb_h_tx_start(musb, epnum);
1063 cppi_hostdma_start(musb, epnum);
1065 } /* end of for loop */
1069 schedule_work(&musb->irq_work);
1074 /*-------------------------------------------------------------------------*/
1077 * Program the HDRC to start (enable interrupts, dma, etc.).
1079 void musb_start(struct musb *musb)
1081 void __iomem *regs = musb->mregs;
1082 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
1085 DBG(2, "<== devctl %02x\n", devctl);
1087 /* Ensure the clocks are on */
1088 if (musb->set_clock)
1089 musb->set_clock(musb->clock, 1);
1091 clk_enable(musb->clock);
1093 /* Set INT enable registers, enable interrupts */
1094 musb_writew(regs, MUSB_INTRTXE, musb->epmask);
1095 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
1096 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
1098 musb_writeb(regs, MUSB_TESTMODE, 0);
1100 power = MUSB_POWER_ISOUPDATE | MUSB_POWER_SOFTCONN
1101 | MUSB_POWER_HSENAB;
1103 /* ENSUSPEND wedges tusb */
1105 power |= MUSB_POWER_ENSUSPEND;
1107 /* put into basic highspeed mode and start session */
1108 musb_writeb(regs, MUSB_POWER, power);
1110 musb->is_active = 0;
1111 devctl = musb_readb(regs, MUSB_DEVCTL);
1112 devctl &= ~MUSB_DEVCTL_SESSION;
1114 if (is_otg_enabled(musb)) {
1115 /* session started after:
1116 * (a) ID-grounded irq, host mode;
1117 * (b) vbus present/connect IRQ, peripheral mode;
1118 * (c) peripheral initiates, using SRP
1120 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
1121 musb->is_active = 1;
1123 devctl |= MUSB_DEVCTL_SESSION;
1125 } else if (is_host_enabled(musb)) {
1126 /* assume ID pin is hard-wired to ground */
1127 devctl |= MUSB_DEVCTL_SESSION;
1129 } else /* peripheral is enabled */ {
1130 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
1131 musb->is_active = 1;
1133 musb_platform_enable(musb);
1134 musb_writeb(regs, MUSB_DEVCTL, devctl);
1138 static void musb_generic_disable(struct musb *musb)
1140 void __iomem *mbase = musb->mregs;
1143 /* Clocks need to be turned on with OFF-mode */
1144 if (musb->set_clock)
1145 musb->set_clock(musb->clock, 1);
1147 clk_enable(musb->clock);
1149 /* disable interrupts */
1150 musb_writeb(mbase, MUSB_INTRUSBE, 0);
1151 musb_writew(mbase, MUSB_INTRTXE, 0);
1152 musb_writew(mbase, MUSB_INTRRXE, 0);
1155 musb_writeb(mbase, MUSB_DEVCTL, 0);
1157 /* flush pending interrupts */
1158 temp = musb_readb(mbase, MUSB_INTRUSB);
1159 temp = musb_readw(mbase, MUSB_INTRTX);
1160 temp = musb_readw(mbase, MUSB_INTRRX);
1164 void musb_emergency_stop(void)
1169 musb_stop(the_musb);
1171 EXPORT_SYMBOL_GPL(musb_emergency_stop);
1174 * Make the HDRC stop (disable interrupts, etc.);
1175 * reversible by musb_start
1176 * called on gadget driver unregister
1177 * with controller locked, irqs blocked
1178 * acts as a NOP unless some role activated the hardware
1180 void musb_stop(struct musb *musb)
1182 /* stop IRQs, timers, ... */
1183 musb_platform_disable(musb);
1184 musb_generic_disable(musb);
1185 DBG(3, "HDRC disabled\n");
1188 * - mark host and/or peripheral drivers unusable/inactive
1189 * - disable DMA (and enable it in HdrcStart)
1190 * - make sure we can musb_start() after musb_stop(); with
1191 * OTG mode, gadget driver module rmmod/modprobe cycles that
1194 musb_platform_try_idle(musb, 0);
1197 static void musb_shutdown(struct platform_device *pdev)
1199 struct musb *musb = dev_to_musb(&pdev->dev);
1200 unsigned long flags;
1202 spin_lock_irqsave(&musb->lock, flags);
1203 musb_platform_disable(musb);
1204 musb_generic_disable(musb);
1206 clk_put(musb->clock);
1209 spin_unlock_irqrestore(&musb->lock, flags);
1211 /* FIXME power down */
1215 /*-------------------------------------------------------------------------*/
1218 * The silicon either has hard-wired endpoint configurations, or else
1219 * "dynamic fifo" sizing. The driver has support for both, though at this
1220 * writing only the dynamic sizing is very well tested. Since we switched
1221 * away from compile-time hardware parameters, we can no longer rely on
1222 * dead code elimination to leave only the relevant one in the object file.
1224 * We don't currently use dynamic fifo setup capability to do anything
1225 * more than selecting one of a bunch of predefined configurations.
1227 #if defined(CONFIG_USB_TUSB6010) || \
1228 defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
1229 static ushort __initdata fifo_mode = 4;
1231 static ushort __initdata fifo_mode = 2;
1234 /* "modprobe ... fifo_mode=1" etc */
1235 module_param(fifo_mode, ushort, 0);
1236 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1239 enum fifo_style { FIFO_RXTX, FIFO_TX, FIFO_RX } __attribute__ ((packed));
1240 enum buf_mode { BUF_SINGLE, BUF_DOUBLE } __attribute__ ((packed));
1244 enum fifo_style style;
1250 * tables defining fifo_mode values. define more if you like.
1251 * for host side, make sure both halves of ep1 are set up.
1254 /* mode 0 - fits in 2KB */
1255 static struct fifo_cfg __initdata mode_0_cfg[] = {
1256 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1257 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1258 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1259 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1260 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1263 /* mode 1 - fits in 4KB */
1264 static struct fifo_cfg __initdata mode_1_cfg[] = {
1265 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1266 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1267 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1268 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1269 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1272 /* mode 2 - fits in 4KB */
1273 static struct fifo_cfg __initdata mode_2_cfg[] = {
1274 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1275 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1276 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1277 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1278 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1279 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1282 /* mode 3 - fits in 4KB */
1283 static struct fifo_cfg __initdata mode_3_cfg[] = {
1284 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1285 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1286 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1287 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1288 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1289 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1292 /* mode 4 - fits in 16KB */
1293 static struct fifo_cfg __initdata mode_4_cfg[] = {
1294 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1295 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1296 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1297 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1298 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1299 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1300 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1301 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1302 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1303 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1304 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1305 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1306 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1307 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1308 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1309 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 64, },
1310 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1311 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 64, },
1312 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 512, },
1313 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1314 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1315 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 256, },
1316 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1317 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 256, },
1318 { .hw_ep_num = 13, .style = FIFO_TX, .maxpacket = 256, },
1319 { .hw_ep_num = 13, .style = FIFO_RX, .maxpacket = 4096, },
1320 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1321 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1324 /* mode 5 - fits in 16KB */
1325 static struct fifo_cfg __initdata mode_5_cfg[] = {
1326 /* phonet or mass storage */
1327 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_SINGLE, },
1328 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_SINGLE, },
1331 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_SINGLE, },
1332 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_SINGLE, },
1335 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_SINGLE, },
1336 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_SINGLE, },
1339 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_SINGLE, },
1340 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_SINGLE, },
1341 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 16, },
1344 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_SINGLE, },
1345 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_SINGLE, },
1346 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 16, },
1349 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1350 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1352 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1353 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1355 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 512, },
1356 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1358 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 512, },
1359 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1363 * configure a fifo; for non-shared endpoints, this may be called
1364 * once for a tx fifo and once for an rx fifo.
1366 * returns negative errno or offset for next fifo.
1369 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1370 const struct fifo_cfg *cfg, u16 offset)
1372 void __iomem *mbase = musb->mregs;
1374 u16 maxpacket = cfg->maxpacket;
1375 u16 c_off = offset >> 3;
1378 /* expect hw_ep has already been zero-initialized */
1380 size = ffs(max(maxpacket, (u16) 8)) - 1;
1381 maxpacket = 1 << size;
1384 if (cfg->mode == BUF_DOUBLE) {
1385 if ((offset + (maxpacket << 1)) >
1386 (1 << (musb->config->ram_bits + 2)))
1388 c_size |= MUSB_FIFOSZ_DPB;
1390 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1394 /* configure the FIFO */
1395 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1397 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1398 /* EP0 reserved endpoint for control, bidirectional;
1399 * EP1 reserved for bulk, two unidirection halves.
1401 if (hw_ep->epnum == 1)
1402 musb->bulk_ep = hw_ep;
1403 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1405 switch (cfg->style) {
1407 musb_write_txfifosz(mbase, c_size);
1408 musb_write_txfifoadd(mbase, c_off);
1409 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1410 hw_ep->max_packet_sz_tx = maxpacket;
1411 ctx.txfifosz[hw_ep->epnum] = c_size;
1412 ctx.txfifoadd[hw_ep->epnum] = c_off;
1415 musb_write_rxfifosz(mbase, c_size);
1416 musb_write_rxfifoadd(mbase, c_off);
1417 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1418 hw_ep->max_packet_sz_rx = maxpacket;
1419 ctx.rxfifosz[hw_ep->epnum] = c_size;
1420 ctx.rxfifoadd[hw_ep->epnum] = c_off;
1423 musb_write_txfifosz(mbase, c_size);
1424 musb_write_txfifoadd(mbase, c_off);
1425 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1426 hw_ep->max_packet_sz_rx = maxpacket;
1428 musb_write_rxfifosz(mbase, c_size);
1429 musb_write_rxfifoadd(mbase, c_off);
1430 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1431 hw_ep->max_packet_sz_tx = maxpacket;
1433 /* Save the context of endpoints. */
1434 ctx.rxfifosz[hw_ep->epnum] = c_size;
1435 ctx.txfifosz[hw_ep->epnum] = c_size;
1436 ctx.txfifoadd[hw_ep->epnum] = c_off;
1437 ctx.rxfifoadd[hw_ep->epnum] = c_off;
1439 hw_ep->is_shared_fifo = true;
1443 /* NOTE rx and tx endpoint irqs aren't managed separately,
1444 * which happens to be ok
1446 musb->epmask |= (1 << hw_ep->epnum);
1448 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1451 static struct fifo_cfg __initdata ep0_cfg = {
1452 .style = FIFO_RXTX, .maxpacket = 64,
1455 static int __init ep_config_from_table(struct musb *musb)
1457 const struct fifo_cfg *cfg;
1460 struct musb_hw_ep *hw_ep = musb->endpoints;
1462 if (machine_is_nokia_rx51())
1465 switch (fifo_mode) {
1471 n = ARRAY_SIZE(mode_0_cfg);
1475 n = ARRAY_SIZE(mode_1_cfg);
1479 n = ARRAY_SIZE(mode_2_cfg);
1483 n = ARRAY_SIZE(mode_3_cfg);
1487 n = ARRAY_SIZE(mode_4_cfg);
1491 n = ARRAY_SIZE(mode_5_cfg);
1495 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1496 musb_driver_name, fifo_mode);
1499 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1500 /* assert(offset > 0) */
1502 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1503 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1506 for (i = 0; i < n; i++) {
1507 u8 epn = cfg->hw_ep_num;
1509 if (epn >= musb->config->num_eps) {
1510 pr_debug("%s: invalid ep %d\n",
1511 musb_driver_name, epn);
1514 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1516 pr_debug("%s: mem overrun, ep %d\n",
1517 musb_driver_name, epn);
1521 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1524 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1526 n + 1, musb->config->num_eps * 2 - 1,
1527 offset, (1 << (musb->config->ram_bits + 2)));
1529 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1530 if (!musb->bulk_ep) {
1531 pr_debug("%s: missing bulk\n", musb_driver_name);
1541 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1542 * @param musb the controller
1544 static int __init ep_config_from_hw(struct musb *musb)
1547 struct musb_hw_ep *hw_ep;
1548 void *mbase = musb->mregs;
1551 DBG(2, "<== static silicon ep config\n");
1553 /* FIXME pick up ep0 maxpacket size */
1555 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1556 musb_ep_select(mbase, epnum);
1557 hw_ep = musb->endpoints + epnum;
1559 ret = musb_read_fifosize(musb, hw_ep, epnum);
1563 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1565 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1566 /* pick an RX/TX endpoint for bulk */
1567 if (hw_ep->max_packet_sz_tx < 512
1568 || hw_ep->max_packet_sz_rx < 512)
1571 /* REVISIT: this algorithm is lazy, we should at least
1572 * try to pick a double buffered endpoint.
1576 musb->bulk_ep = hw_ep;
1580 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1581 if (!musb->bulk_ep) {
1582 pr_debug("%s: missing bulk\n", musb_driver_name);
1590 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1592 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1593 * configure endpoints, or take their config from silicon
1595 static int __init musb_core_init(u16 musb_type, struct musb *musb)
1602 u16 hwvers, rev_major, rev_minor;
1603 char aInfo[78], aRevision[32], aDate[12];
1604 void __iomem *mbase = musb->mregs;
1608 /* log core options (read using indexed model) */
1609 musb_ep_select(mbase, 0);
1610 reg = musb_read_configdata(mbase);
1612 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1613 if (reg & MUSB_CONFIGDATA_DYNFIFO)
1614 strcat(aInfo, ", dyn FIFOs");
1615 if (reg & MUSB_CONFIGDATA_MPRXE) {
1616 strcat(aInfo, ", bulk combine");
1618 musb->bulk_combine = true;
1620 strcat(aInfo, " (X)"); /* no driver support */
1623 if (reg & MUSB_CONFIGDATA_MPTXE) {
1624 strcat(aInfo, ", bulk split");
1626 musb->bulk_split = true;
1628 strcat(aInfo, " (X)"); /* no driver support */
1631 if (reg & MUSB_CONFIGDATA_HBRXE) {
1632 strcat(aInfo, ", HB-ISO Rx");
1633 strcat(aInfo, " (X)"); /* no driver support */
1635 if (reg & MUSB_CONFIGDATA_HBTXE) {
1636 strcat(aInfo, ", HB-ISO Tx");
1637 strcat(aInfo, " (X)"); /* no driver support */
1639 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1640 strcat(aInfo, ", SoftConn");
1642 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1643 musb_driver_name, reg, aInfo);
1646 data = musb_readl(mbase, 0x404);
1647 sprintf(aDate, "%04d-%02x-%02x", (data & 0xffff),
1648 (data >> 16) & 0xff, (data >> 24) & 0xff);
1649 /* FIXME ID2 and ID3 are unused */
1650 data = musb_readl(mbase, 0x408);
1651 printk(KERN_DEBUG "ID2=%lx\n", (long unsigned)data);
1652 data = musb_readl(mbase, 0x40c);
1653 printk(KERN_DEBUG "ID3=%lx\n", (long unsigned)data);
1654 reg = musb_readb(mbase, 0x400);
1655 musb_type = ('M' == reg) ? MUSB_CONTROLLER_MHDRC : MUSB_CONTROLLER_HDRC;
1659 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1660 musb->is_multipoint = 1;
1663 musb->is_multipoint = 0;
1665 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1666 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1668 "%s: kernel must blacklist external hubs\n",
1674 /* log release info */
1675 hwvers = musb_read_hwvers(mbase);
1676 rev_major = (hwvers >> 10) & 0x1f;
1677 rev_minor = hwvers & 0x3ff;
1678 snprintf(aRevision, 32, "%d.%d%s", rev_major,
1679 rev_minor, (hwvers & 0x8000) ? "RC" : "");
1680 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1681 musb_driver_name, type, aRevision, aDate);
1684 musb_configure_ep0(musb);
1686 /* discover endpoint configuration */
1687 musb->nr_endpoints = 1;
1690 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1691 if (musb->config->dyn_fifo)
1692 status = ep_config_from_table(musb);
1694 ERR("reconfigure software for Dynamic FIFOs\n");
1698 if (!musb->config->dyn_fifo)
1699 status = ep_config_from_hw(musb);
1701 ERR("reconfigure software for static FIFOs\n");
1709 /* finish init, and print endpoint config */
1710 for (i = 0; i < musb->nr_endpoints; i++) {
1711 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1713 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1714 #ifdef CONFIG_USB_TUSB6010
1715 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1716 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1717 hw_ep->fifo_sync_va =
1718 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1721 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1723 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1726 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1727 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1728 /* init list of in and out qhs */
1729 INIT_LIST_HEAD(&hw_ep->in_list);
1730 INIT_LIST_HEAD(&hw_ep->out_list);
1731 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1732 hw_ep->rx_reinit = 1;
1733 hw_ep->tx_reinit = 1;
1736 if (hw_ep->max_packet_sz_tx) {
1738 "%s: hw_ep %d%s, %smax %d\n",
1739 musb_driver_name, i,
1740 hw_ep->is_shared_fifo ? "shared" : "tx",
1741 hw_ep->tx_double_buffered
1742 ? "doublebuffer, " : "",
1743 hw_ep->max_packet_sz_tx);
1745 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1747 "%s: hw_ep %d%s, %smax %d\n",
1748 musb_driver_name, i,
1750 hw_ep->rx_double_buffered
1751 ? "doublebuffer, " : "",
1752 hw_ep->max_packet_sz_rx);
1754 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1755 DBG(1, "hw_ep %d not configured\n", i);
1761 /*-------------------------------------------------------------------------*/
1763 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
1765 static irqreturn_t generic_interrupt(int irq, void *__hci)
1767 unsigned long flags;
1768 irqreturn_t retval = IRQ_NONE;
1769 struct musb *musb = __hci;
1771 spin_lock_irqsave(&musb->lock, flags);
1773 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
1774 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
1775 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
1777 while (musb->int_usb || musb->int_tx || musb->int_rx)
1778 retval |= musb_interrupt(musb);
1780 spin_unlock_irqrestore(&musb->lock, flags);
1782 /* REVISIT we sometimes get spurious IRQs on g_ep0
1785 if (retval != IRQ_HANDLED)
1786 DBG(5, "spurious?\n");
1792 #define generic_interrupt NULL
1796 * handle all the irqs defined by the HDRC core. for now we expect: other
1797 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1798 * will be assigned, and the irq will already have been acked.
1800 * called in irq context with spinlock held, irqs blocked
1802 irqreturn_t musb_interrupt(struct musb *musb)
1804 irqreturn_t retval = IRQ_NONE;
1805 u8 devctl, power, int_usb;
1809 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1810 power = musb_readb(musb->mregs, MUSB_POWER);
1812 DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n",
1813 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1814 musb->int_usb, musb->int_tx, musb->int_rx);
1816 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1817 if (is_otg_enabled(musb)|| is_peripheral_enabled(musb))
1818 if (!musb->gadget_driver) {
1819 DBG(5, "No gadget driver loaded\n");
1827 /* the core can interrupt us for multiple reasons; docs have
1828 * a generic interrupt flowchart to follow
1830 int_usb = musb->int_usb;
1832 int_usb &= ~MUSB_INTR_SOF;
1834 retval |= musb_stage0_irq(musb, int_usb, devctl, power);
1836 /* "stage 1" is handling endpoint irqs */
1838 /* handle endpoint 0 first */
1839 if (musb->int_tx & 1) {
1841 if (devctl & MUSB_DEVCTL_HM)
1842 retval |= musb_h_ep0_irq(musb);
1844 retval |= musb_g_ep0_irq(musb);
1847 /* TX on endpoints 1-15 */
1848 reg = musb->int_tx >> 1;
1853 /* musb_ep_select(musb->mregs, ep_num); */
1854 /* REVISIT just retval |= ep->tx_irq(...) */
1855 retval = IRQ_HANDLED;
1856 if (devctl & MUSB_DEVCTL_HM) {
1857 if (is_host_capable())
1858 musb_host_tx(musb, ep_num);
1860 if (is_peripheral_capable())
1861 musb_g_tx(musb, ep_num);
1868 /* RX on endpoints 1-15 */
1869 reg = musb->int_rx >> 1;
1874 /* musb_ep_select(musb->mregs, ep_num); */
1875 /* REVISIT just retval = ep->rx_irq(...) */
1876 retval = IRQ_HANDLED;
1877 if (devctl & MUSB_DEVCTL_HM) {
1878 if (is_host_capable())
1879 musb_host_rx(musb, ep_num);
1881 if (is_peripheral_capable())
1882 musb_g_rx(musb, ep_num, false);
1894 #ifndef CONFIG_MUSB_PIO_ONLY
1895 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1897 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1899 /* called with controller lock already held */
1902 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1903 if (!cppi_ti_dma()) {
1905 if (devctl & MUSB_DEVCTL_HM)
1906 musb_h_ep0_irq(musb);
1908 musb_g_ep0_irq(musb);
1912 /* endpoints 1..15 */
1914 if (devctl & MUSB_DEVCTL_HM) {
1915 if (is_host_capable())
1916 musb_host_tx(musb, epnum);
1918 if (is_peripheral_capable())
1919 musb_g_tx(musb, epnum);
1923 if (devctl & MUSB_DEVCTL_HM) {
1924 if (is_host_capable())
1925 musb_host_rx(musb, epnum);
1927 if (is_peripheral_capable())
1928 musb_g_rx(musb, epnum, true);
1935 /*-------------------------------------------------------------------------*/
1940 musb_charger_show(struct device *dev, struct device_attribute *attr, char *buf)
1942 struct musb *musb = dev_to_musb(dev);
1944 return sprintf(buf, "%d\n", (musb->is_charger ?
1945 musb->is_charger : musb_charger_detect(musb)));
1947 static DEVICE_ATTR(charger, 0444, musb_charger_show, NULL);
1950 musb_amp_show(struct device *dev, struct device_attribute *attr, char *buf)
1952 struct musb *musb = dev_to_musb(dev);
1954 return sprintf(buf, "%d\n", musb->power_draw);
1956 static DEVICE_ATTR(mA, 0444, musb_amp_show, NULL);
1959 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1961 struct musb *musb = dev_to_musb(dev);
1964 mutex_lock(&musb->mutex);
1965 ret = sprintf(buf, "%s\n", otg_state_string(musb));
1966 mutex_unlock(&musb->mutex);
1972 musb_connect_show(struct device *dev, struct device_attribute *attr, char *buf)
1974 struct musb *musb = dev_to_musb(dev);
1975 unsigned long flags;
1978 spin_lock_irqsave(&musb->lock, flags);
1979 ret = sprintf(buf, "%d\n", musb->softconnect);
1980 spin_unlock_irqrestore(&musb->lock, flags);
1986 musb_connect_store(struct device *dev, struct device_attribute *attr,
1987 const char *buf, size_t n)
1989 struct musb *musb = dev_to_musb(dev);
1990 unsigned long flags;
1995 status = sscanf(buf, "%u", &val);
1997 printk(KERN_ERR "invalid parameter, %d\n", status);
2001 spin_lock_irqsave(&musb->lock, flags);
2003 power = musb_readb(musb->mregs, MUSB_POWER);
2006 power |= MUSB_POWER_SOFTCONN;
2008 power &= ~MUSB_POWER_SOFTCONN;
2010 musb->softconnect = !!val;
2011 musb_writeb(musb->mregs, MUSB_POWER, power);
2013 spin_unlock_irqrestore(&musb->lock, flags);
2017 static DEVICE_ATTR(connect, 0644, musb_connect_show, musb_connect_store);
2020 musb_mode_store(struct device *dev, struct device_attribute *attr,
2021 const char *buf, size_t n)
2023 struct musb *musb = dev_to_musb(dev);
2026 mutex_lock(&musb->mutex);
2027 if (sysfs_streq(buf, "host"))
2028 status = musb_platform_set_mode(musb, MUSB_HOST);
2029 else if (sysfs_streq(buf, "peripheral"))
2030 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
2031 else if (sysfs_streq(buf, "otg"))
2032 status = musb_platform_set_mode(musb, MUSB_OTG);
2035 mutex_unlock(&musb->mutex);
2037 return (status == 0) ? n : status;
2039 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
2042 musb_vbus_store(struct device *dev, struct device_attribute *attr,
2043 const char *buf, size_t n)
2045 struct musb *musb = dev_to_musb(dev);
2046 unsigned long flags;
2049 if (sscanf(buf, "%lu", &val) < 1) {
2050 printk(KERN_ERR "Invalid VBUS timeout ms value\n");
2054 spin_lock_irqsave(&musb->lock, flags);
2055 musb->a_wait_bcon = val;
2056 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
2057 musb->is_active = 0;
2058 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
2059 spin_unlock_irqrestore(&musb->lock, flags);
2065 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
2067 struct musb *musb = dev_to_musb(dev);
2068 unsigned long flags;
2072 spin_lock_irqsave(&musb->lock, flags);
2073 val = musb->a_wait_bcon;
2074 vbus = musb_platform_get_vbus_status(musb);
2075 spin_unlock_irqrestore(&musb->lock, flags);
2077 return sprintf(buf, "Vbus %s, timeout %lu\n",
2078 vbus ? "on" : "off", val);
2080 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
2082 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2085 musb_suspend_show(struct device *dev, struct device_attribute *attr, char *buf)
2087 struct musb *musb = dev_to_musb(dev);
2089 return sprintf(buf, "%d\n", musb->is_suspended);
2091 static DEVICE_ATTR(suspend, 0444, musb_suspend_show, NULL);
2093 /* Gadget drivers can't know that a host is connected so they might want
2094 * to start SRP, but users can. This allows userspace to trigger SRP.
2097 musb_srp_store(struct device *dev, struct device_attribute *attr,
2098 const char *buf, size_t n)
2100 struct musb *musb = dev_to_musb(dev);
2103 if (sscanf(buf, "%hu", &srp) != 1
2105 printk(KERN_ERR "SRP: Value must be 1\n");
2110 musb_g_wakeup(musb);
2114 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
2116 #endif /* CONFIG_USB_GADGET_MUSB_HDRC */
2120 /* Only used to provide driver mode change events */
2121 static void musb_irq_work(struct work_struct *data)
2123 struct musb *musb = container_of(data, struct musb, irq_work);
2124 static int old_state, old_ma, old_suspend;
2126 if (musb->xceiv->state != old_state) {
2127 old_state = musb->xceiv->state;
2128 sysfs_notify(&musb->controller->kobj, NULL, "mode");
2130 if (musb->power_draw != old_ma) {
2131 old_ma = musb->power_draw;
2132 sysfs_notify(&musb->controller->kobj, NULL, "mA");
2134 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2135 if (old_suspend != musb->is_suspended) {
2136 old_suspend = musb->is_suspended;
2137 sysfs_notify(&musb->controller->kobj, NULL, "suspend");
2142 /* --------------------------------------------------------------------------
2146 static struct musb *__init
2147 allocate_instance(struct device *dev,
2148 struct musb_hdrc_config *config, void __iomem *mbase)
2151 struct musb_hw_ep *ep;
2153 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2154 struct usb_hcd *hcd;
2156 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
2159 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
2161 musb = hcd_to_musb(hcd);
2163 hcd->uses_new_polling = 1;
2165 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
2167 musb = kzalloc(sizeof *musb, GFP_KERNEL);
2170 dev_set_drvdata(dev, musb);
2174 musb->mregs = mbase;
2175 musb->ctrl_base = mbase;
2176 musb->nIrq = -ENODEV;
2177 musb->config = config;
2178 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
2179 for (epnum = 0, ep = musb->endpoints;
2180 epnum < musb->config->num_eps;
2186 musb->controller = dev;
2190 static void musb_free(struct musb *musb)
2192 /* this has multiple entry modes. it handles fault cleanup after
2193 * probe(), where things may be partially set up, as well as rmmod
2194 * cleanup after everything's been de-activated.
2198 device_remove_file(musb->controller, &dev_attr_mA);
2199 device_remove_file(musb->controller, &dev_attr_connect);
2200 device_remove_file(musb->controller, &dev_attr_charger);
2201 device_remove_file(musb->controller, &dev_attr_mode);
2202 device_remove_file(musb->controller, &dev_attr_vbus);
2203 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2204 device_remove_file(musb->controller, &dev_attr_suspend);
2205 device_remove_file(musb->controller, &dev_attr_srp);
2209 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2210 musb_gadget_cleanup(musb);
2213 if (musb->nIrq >= 0) {
2215 disable_irq_wake(musb->nIrq);
2216 free_irq(musb->nIrq, musb);
2218 if (is_dma_capable() && musb->dma_controller) {
2219 struct dma_controller *c = musb->dma_controller;
2222 dma_controller_destroy(c);
2225 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
2226 musb_platform_exit(musb);
2227 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
2230 clk_disable(musb->clock);
2231 clk_put(musb->clock);
2234 #ifdef CONFIG_USB_MUSB_OTG
2235 put_device(musb->xceiv->dev);
2238 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2239 usb_put_hcd(musb_to_hcd(musb));
2246 * Perform generic per-controller initialization.
2248 * @pDevice: the controller (already clocked, etc)
2250 * @mregs: virtual address of controller registers,
2251 * not yet corrected for platform-specific offsets
2254 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
2258 struct musb_hdrc_platform_data *plat = dev->platform_data;
2260 /* The driver might handle more features than the board; OK.
2261 * Fail when the board needs a feature that's not enabled.
2264 dev_dbg(dev, "no platform_data?\n");
2267 switch (plat->mode) {
2269 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2274 case MUSB_PERIPHERAL:
2275 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2281 #ifdef CONFIG_USB_MUSB_OTG
2287 dev_err(dev, "incompatible Kconfig role setting\n");
2292 musb = allocate_instance(dev, plat->config, ctrl);
2298 spin_lock_init(&musb->lock);
2299 mutex_init(&musb->mutex);
2300 musb->board = plat->board;
2301 musb->board_mode = plat->mode;
2302 musb->board_set_power = plat->set_power;
2303 musb->set_clock = plat->set_clock;
2304 musb->min_power = plat->min_power;
2305 musb->use_dma = use_dma;
2307 /* Clock usage is chip-specific ... functional clock (DaVinci,
2308 * OMAP2430), or PHY ref (some TUSB6010 boards). All this core
2309 * code does is make sure a clock handle is available; platform
2310 * code manages it during start/stop and suspend/resume.
2313 musb->clock = clk_get(dev, plat->clock);
2314 if (IS_ERR(musb->clock)) {
2315 status = PTR_ERR(musb->clock);
2321 /* assume vbus is off */
2323 /* platform adjusts musb->mregs and musb->isr if needed,
2324 * and activates clocks
2326 musb->isr = generic_interrupt;
2327 status = musb_platform_init(musb);
2336 #ifndef CONFIG_MUSB_PIO_ONLY
2337 if (use_dma && dev->dma_mask) {
2338 struct dma_controller *c;
2340 c = dma_controller_create(musb, musb->mregs);
2341 musb->dma_controller = c;
2346 /* ideally this would be abstracted in platform setup */
2347 if (!musb->use_dma || !musb->dma_controller)
2348 dev->dma_mask = NULL;
2350 /* be sure interrupts are disabled before connecting ISR */
2351 musb_platform_disable(musb);
2352 musb_generic_disable(musb);
2354 /* setup musb parts of the core (especially endpoints) */
2355 status = musb_core_init(plat->config->multipoint
2356 ? MUSB_CONTROLLER_MHDRC
2357 : MUSB_CONTROLLER_HDRC, musb);
2361 /* Init IRQ workqueue before request_irq */
2362 INIT_WORK(&musb->irq_work, musb_irq_work);
2364 /* attach to the IRQ */
2365 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
2366 dev_err(dev, "request_irq %d failed!\n", nIrq);
2371 /* FIXME this handles wakeup irqs wrong */
2372 if (enable_irq_wake(nIrq) == 0) {
2374 device_init_wakeup(dev, 1);
2379 pr_info("%s: USB %s mode controller at %p using %s, IRQ %d\n",
2382 switch (musb->board_mode) {
2383 case MUSB_HOST: s = "Host"; break;
2384 case MUSB_PERIPHERAL: s = "Peripheral"; break;
2385 default: s = "OTG"; break;
2388 (is_dma_capable() && musb->dma_controller)
2392 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2393 /* host side needs more setup, except for no-host modes */
2394 if (musb->board_mode != MUSB_PERIPHERAL) {
2395 struct usb_hcd *hcd = musb_to_hcd(musb);
2397 if (musb->board_mode == MUSB_OTG)
2398 hcd->self.otg_port = 1;
2399 musb->xceiv->host = &hcd->self;
2400 hcd->power_budget = 2 * (plat->power ? : 250);
2402 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
2404 /* For the host-only role, we can activate right away.
2405 * (We expect the ID pin to be forcibly grounded!!)
2406 * Otherwise, wait till the gadget driver hooks up.
2408 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
2409 MUSB_HST_MODE(musb);
2410 musb->xceiv->default_a = 1;
2411 musb->xceiv->state = OTG_STATE_A_IDLE;
2413 status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
2417 DBG(1, "%s mode, status %d, devctl %02x %c\n",
2419 musb_readb(musb->mregs, MUSB_DEVCTL),
2420 (musb_readb(musb->mregs, MUSB_DEVCTL)
2421 & MUSB_DEVCTL_BDEVICE
2424 } else /* peripheral is enabled */ {
2425 MUSB_DEV_MODE(musb);
2426 musb->xceiv->default_a = 0;
2427 musb->xceiv->state = OTG_STATE_B_IDLE;
2429 status = musb_gadget_setup(musb);
2433 DBG(1, "%s mode, status %d, dev%02x\n",
2434 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2436 musb_readb(musb->mregs, MUSB_DEVCTL));
2440 if (!(musb_debug_create("driver/musb_hdrc", musb)))
2441 DBG(1, "could not create procfs entry\n");
2444 status = device_create_file(dev, &dev_attr_mA);
2445 status = device_create_file(dev, &dev_attr_connect);
2446 status = device_create_file(dev, &dev_attr_charger);
2447 status = device_create_file(dev, &dev_attr_mode);
2448 status = device_create_file(dev, &dev_attr_vbus);
2449 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2450 status = device_create_file(dev, &dev_attr_suspend);
2451 status = device_create_file(dev, &dev_attr_srp);
2452 #endif /* CONFIG_USB_GADGET_MUSB_HDRC */
2458 /* Resets the controller. Has to be done. Without this, most likely
2459 * the state machine inside the transceiver doesn't get fixed properly
2461 musb_save_ctx_and_suspend(&musb->g, 0);
2462 musb_restore_ctx_and_resume(&musb->g);
2468 device_remove_file(dev, &dev_attr_mA);
2469 device_remove_file(dev, &dev_attr_connect);
2470 device_remove_file(dev, &dev_attr_charger);
2471 device_remove_file(musb->controller, &dev_attr_mode);
2472 device_remove_file(musb->controller, &dev_attr_vbus);
2473 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2474 device_remove_file(musb->controller, &dev_attr_suspend);
2475 device_remove_file(musb->controller, &dev_attr_srp);
2478 musb_platform_exit(musb);
2480 dev_err(musb->controller,
2481 "musb_init_controller failed with status %d\n", status);
2484 clk_put(musb->clock);
2485 device_init_wakeup(dev, 0);
2492 /*-------------------------------------------------------------------------*/
2494 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2495 * bridge to a platform device; this driver then suffices.
2498 #ifndef CONFIG_MUSB_PIO_ONLY
2499 static u64 *orig_dma_mask;
2502 static int __init musb_probe(struct platform_device *pdev)
2504 struct device *dev = &pdev->dev;
2505 int irq = platform_get_irq(pdev, 0);
2506 struct resource *iomem;
2509 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2510 if (!iomem || irq == 0)
2513 base = ioremap(iomem->start, iomem->end - iomem->start + 1);
2515 dev_err(dev, "ioremap failed\n");
2519 #ifndef CONFIG_MUSB_PIO_ONLY
2520 /* clobbered by use_dma=n */
2521 orig_dma_mask = dev->dma_mask;
2523 /* Store initial mask for USB interrupts */
2524 ctx.intrusbe = 0xf7;
2526 return musb_init_controller(dev, irq, base);
2529 static int __devexit musb_remove(struct platform_device *pdev)
2531 struct musb *musb = dev_to_musb(&pdev->dev);
2532 void __iomem *ctrl_base = musb->ctrl_base;
2534 /* this gets called on rmmod.
2535 * - Host mode: host may still be active
2536 * - Peripheral mode: peripheral is deactivated (or never-activated)
2537 * - OTG mode: both roles are deactivated (or never-activated)
2539 musb_shutdown(pdev);
2540 musb_debug_delete("driver/musb_hdrc", musb);
2541 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2542 if (musb->board_mode == MUSB_HOST)
2543 usb_remove_hcd(musb_to_hcd(musb));
2547 device_init_wakeup(&pdev->dev, 0);
2548 #ifndef CONFIG_MUSB_PIO_ONLY
2549 pdev->dev.dma_mask = orig_dma_mask;
2556 void musb_save_ctx(struct musb *musb)
2558 ctx.power = musb_readb(musb->mregs, MUSB_POWER);
2559 ctx.intrtxe = musb_readw(musb->mregs, MUSB_INTRTXE);
2560 ctx.intrrxe = musb_readw(musb->mregs, MUSB_INTRRXE);
2561 ctx.intrusbe = musb_readb(musb->mregs, MUSB_INTRUSBE);
2562 ctx.devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2565 void musb_restore_ctx(struct musb *musb)
2568 musb_writeb(musb->mregs, MUSB_POWER, ctx.power);
2569 musb_writew(musb->mregs, MUSB_INTRTX, 0x00);
2570 musb_writew(musb->mregs, MUSB_INTRTXE, ctx.intrtxe);
2571 musb_writew(musb->mregs, MUSB_INTRRX, 0x00);
2572 musb_writew(musb->mregs, MUSB_INTRRXE, ctx.intrrxe);
2573 musb_writeb(musb->mregs, MUSB_INTRUSB, 0x00);
2574 musb_writeb(musb->mregs, MUSB_INTRUSBE, ctx.intrusbe);
2575 musb_writeb(musb->mregs, MUSB_DEVCTL, ctx.devctl);
2577 /* iterate over every endpoint, select it and restore its context */
2578 for (i = 0; i < musb->config->num_eps; i++) {
2579 musb_writeb(musb->mregs, MUSB_INDEX, i);
2580 musb_writeb(musb->mregs, MUSB_RXFIFOSZ, ctx.rxfifosz[i]);
2581 musb_writeb(musb->mregs, MUSB_TXFIFOSZ, ctx.txfifosz[i]);
2582 musb_writew(musb->mregs, MUSB_TXFIFOADD, ctx.txfifoadd[i]);
2583 musb_writew(musb->mregs, MUSB_RXFIFOADD, ctx.rxfifoadd[i]);
2587 static int musb_suspend(struct platform_device *pdev, pm_message_t message)
2589 unsigned long flags;
2590 struct musb *musb = dev_to_musb(&pdev->dev);
2595 spin_lock_irqsave(&musb->lock, flags);
2597 if (is_peripheral_active(musb)) {
2598 /* FIXME force disconnect unless we know USB will wake
2599 * the system up quickly enough to respond ...
2601 } else if (is_host_active(musb)) {
2602 /* we know all the children are suspended; sometimes
2603 * they will even be wakeup-enabled.
2608 musb_save_ctx(musb);
2610 if (musb->set_clock)
2611 musb->set_clock(musb->clock, 0);
2613 clk_disable(musb->clock);
2615 spin_unlock_irqrestore(&musb->lock, flags);
2619 static int musb_resume(struct platform_device *pdev)
2621 unsigned long flags;
2622 struct musb *musb = dev_to_musb(&pdev->dev);
2627 spin_lock_irqsave(&musb->lock, flags);
2629 if (musb->set_clock)
2630 musb->set_clock(musb->clock, 1);
2632 clk_enable(musb->clock);
2634 /* restore context */
2635 musb_restore_ctx(musb);
2637 /* for static cmos like DaVinci, register values were preserved
2638 * unless for some reason the whole soc powered down and we're
2639 * not treating that as a whole-system restart (e.g. swsusp)
2641 spin_unlock_irqrestore(&musb->lock, flags);
2646 #define musb_suspend NULL
2647 #define musb_resume NULL
2650 static struct platform_driver musb_driver = {
2652 .name = (char *)musb_driver_name,
2653 .bus = &platform_bus_type,
2654 .owner = THIS_MODULE,
2656 .remove = __devexit_p(musb_remove),
2657 .shutdown = musb_shutdown,
2658 .suspend = musb_suspend,
2659 .resume = musb_resume,
2662 /*-------------------------------------------------------------------------*/
2664 static int __init musb_init(void)
2666 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2671 pr_info("%s: version " MUSB_VERSION ", "
2672 #ifdef CONFIG_MUSB_PIO_ONLY
2674 #elif defined(CONFIG_USB_TI_CPPI_DMA)
2676 #elif defined(CONFIG_USB_INVENTRA_DMA)
2678 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
2684 #ifdef CONFIG_USB_MUSB_OTG
2685 "otg (peripheral+host)"
2686 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
2688 #elif defined(CONFIG_USB_MUSB_HDRC_HCD)
2692 musb_driver_name, musb_debug);
2693 return platform_driver_probe(&musb_driver, musb_probe);
2696 /* make us init after usbcore and before usb
2697 * gadget and host-side drivers start to register
2699 subsys_initcall(musb_init);
2701 static void __exit musb_cleanup(void)
2703 platform_driver_unregister(&musb_driver);
2705 module_exit(musb_cleanup);