2 * MUSB OTG driver core code
4 * Copyright 2005 Mentor Graphics Corporation
5 * Copyright (C) 2005-2006 by Texas Instruments
6 * Copyright (C) 2006-2007 Nokia Corporation
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
22 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
23 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
24 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
25 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
28 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
29 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 * Inventra (Multipoint) Dual-Role Controller Driver for Linux.
38 * This consists of a Host Controller Driver (HCD) and a peripheral
39 * controller driver implementing the "Gadget" API; OTG support is
40 * in the works. These are normal Linux-USB controller drivers which
41 * use IRQs and have no dedicated thread.
43 * This version of the driver has only been used with products from
44 * Texas Instruments. Those products integrate the Inventra logic
45 * with other DMA, IRQ, and bus modules, as well as other logic that
46 * needs to be reflected in this driver.
49 * NOTE: the original Mentor code here was pretty much a collection
50 * of mechanisms that don't seem to have been fully integrated/working
51 * for *any* Linux kernel version. This version aims at Linux 2.6.now,
52 * Key open issues include:
54 * - Lack of host-side transaction scheduling, for all transfer types.
55 * The hardware doesn't do it; instead, software must.
57 * This is not an issue for OTG devices that don't support external
58 * hubs, but for more "normal" USB hosts it's a user issue that the
59 * "multipoint" support doesn't scale in the expected ways. That
60 * includes DaVinci EVM in a common non-OTG mode.
62 * * Control and bulk use dedicated endpoints, and there's as
63 * yet no mechanism to either (a) reclaim the hardware when
64 * peripherals are NAKing, which gets complicated with bulk
65 * endpoints, or (b) use more than a single bulk endpoint in
68 * RESULT: one device may be perceived as blocking another one.
70 * * Interrupt and isochronous will dynamically allocate endpoint
71 * hardware, but (a) there's no record keeping for bandwidth;
72 * (b) in the common case that few endpoints are available, there
73 * is no mechanism to reuse endpoints to talk to multiple devices.
75 * RESULT: At one extreme, bandwidth can be overcommitted in
76 * some hardware configurations, no faults will be reported.
77 * At the other extreme, the bandwidth capabilities which do
78 * exist tend to be severely undercommitted. You can't yet hook
79 * up both a keyboard and a mouse to an external USB hub.
83 * This gets many kinds of configuration information:
84 * - Kconfig for everything user-configurable
85 * - platform_device for addressing, irq, and platform_data
86 * - platform_data is mostly for board-specific informarion
87 * (plus recentrly, SOC or family details)
89 * Most of the conditional compilation will (someday) vanish.
92 #include <linux/module.h>
93 #include <linux/kernel.h>
94 #include <linux/sched.h>
95 #include <linux/slab.h>
96 #include <linux/init.h>
97 #include <linux/list.h>
98 #include <linux/kobject.h>
99 #include <linux/platform_device.h>
100 #include <linux/io.h>
103 #include <mach/hardware.h>
104 #include <mach/memory.h>
105 #include <asm/mach-types.h>
108 #include "musb_core.h"
111 #ifdef CONFIG_ARCH_DAVINCI
115 static struct musb *the_musb;
116 static struct musb_ctx ctx;
118 #ifndef CONFIG_MUSB_PIO_ONLY
119 static int __initdata use_dma = 1;
121 static int __initdata use_dma;
123 module_param(use_dma, bool, 0);
124 MODULE_PARM_DESC(use_dma, "enable/disable use of DMA");
126 unsigned musb_debug = 0;
127 module_param_named(debug, musb_debug, uint, S_IRUGO | S_IWUSR);
128 MODULE_PARM_DESC(debug, "Debug message level. Default = 0");
130 #define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
131 #define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
133 #define MUSB_VERSION "6.0"
135 #define DRIVER_INFO DRIVER_DESC ", v" MUSB_VERSION
137 #define MUSB_DRIVER_NAME "musb_hdrc"
138 const char musb_driver_name[] = MUSB_DRIVER_NAME;
140 MODULE_DESCRIPTION(DRIVER_INFO);
141 MODULE_AUTHOR(DRIVER_AUTHOR);
142 MODULE_LICENSE("GPL");
143 MODULE_ALIAS("platform:" MUSB_DRIVER_NAME);
145 static inline int musb_verify_charger(void __iomem *addr)
149 /* Reset the transceiver */
150 r = musb_ulpi_readb(addr, ISP1704_FUNC_CTRL);
151 r |= ISP1704_FUNC_CTRL_RESET;
152 musb_ulpi_writeb(addr, ISP1704_FUNC_CTRL, r);
155 /* Set normal mode */
156 r &= ~(ISP1704_FUNC_CTRL_RESET | (3 << ISP1704_FUNC_CTRL_OPMODE));
157 musb_ulpi_writeb(addr, ISP1704_FUNC_CTRL, r);
159 /* Clear the DP and DM pull-down bits */
160 r = musb_ulpi_readb(addr, ISP1704_OTG_CTRL);
161 r &= ~(ISP1704_OTG_CTRL_DP_PULLDOWN | ISP1704_OTG_CTRL_DM_PULLDOWN);
162 musb_ulpi_writeb(addr, ISP1704_OTG_CTRL, r);
164 /* Enable strong pull-up on DP (1.5K) and reset */
165 r = musb_ulpi_readb(addr, ISP1704_FUNC_CTRL);
166 r |= ISP1704_FUNC_CTRL_TERMSELECT | ISP1704_FUNC_CTRL_RESET;
167 musb_ulpi_writeb(addr, ISP1704_FUNC_CTRL, r);
170 /* Read the line state */
171 if (musb_ulpi_readb(addr, ISP1704_DEBUG)) {
172 /* Is it a charger or PS2 connection */
174 /* Enable weak pull-up resistor on DP */
175 r = musb_ulpi_readb(addr, ISP1704_PWR_CTRL);
176 r |= ISP1704_PWR_CTRL_DP_WKPU_EN;
177 musb_ulpi_writeb(addr, ISP1704_PWR_CTRL, r);
179 /* Disable strong pull-up on DP (1.5K) */
180 r = musb_ulpi_readb(addr, ISP1704_FUNC_CTRL);
181 r &= ~ISP1704_FUNC_CTRL_TERMSELECT;
182 musb_ulpi_writeb(addr, ISP1704_FUNC_CTRL, r);
184 /* Enable weak pull-down resistor on DM */
185 r = musb_ulpi_readb(addr, ISP1704_OTG_CTRL);
186 r |= ISP1704_OTG_CTRL_DM_PULLDOWN;
187 musb_ulpi_writeb(addr, ISP1704_OTG_CTRL, r);
189 /* It's a charger if the line states are clear */
190 if (!(musb_ulpi_readb(addr, ISP1704_DEBUG)))
193 /* Disable weak pull-up resistor on DP */
194 r = musb_ulpi_readb(addr, ISP1704_PWR_CTRL);
195 r &= ~ISP1704_PWR_CTRL_DP_WKPU_EN;
196 musb_ulpi_writeb(addr, ISP1704_PWR_CTRL, r);
200 /* Disable strong pull-up on DP (1.5K) */
201 r = musb_ulpi_readb(addr, ISP1704_FUNC_CTRL);
202 r &= ~ISP1704_FUNC_CTRL_TERMSELECT;
203 musb_ulpi_writeb(addr, ISP1704_FUNC_CTRL, r);
209 /* Bad connections with the charger may lead into the transceiver
210 * thinking that a device was just connected. We can wait for 5 ms to
211 * ensure that these cases will generate SUSPEND interrupt and not
212 * RESET. Reading and writing to the transceiver may still cause
213 * RESET interrupts. We mask out RESET/RESUME interrupts to
216 static int check_charger;
217 static int musb_charger_detect(struct musb *musb)
219 unsigned long timeout;
226 /* Using ulpi with musb is quite tricky. The following code
227 * was written based on the ulpi application note.
229 * The order of reads and writes and quite important, don't
230 * change it unless you really know what you're doing
233 DBG(4, "Some asshole called musb_charger_detect!");
235 switch(musb->xceiv->state) {
236 case OTG_STATE_B_IDLE:
237 /* we always reset transceiver */
240 /* HACK: ULPI tends to get stuck when booting with
241 * the cable connected
243 r = musb_readb(musb->mregs, MUSB_DEVCTL);
244 if ((r & MUSB_DEVCTL_VBUS)
245 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
246 musb_save_ctx_and_suspend(&musb->g, 0);
247 musb_restore_ctx_and_resume(&musb->g);
248 if (musb->board && musb->board->set_pm_limits)
249 musb->board->set_pm_limits(
250 musb->controller, 1);
253 /* disable RESET and RESUME interrupts */
254 r = musb_readb(musb->mregs, MUSB_INTRUSBE);
255 r &= ~(MUSB_INTR_RESUME | MUSB_INTR_RESET);
256 musb_writeb(musb->mregs, MUSB_INTRUSBE, r);
258 if (musb->board && musb->board->xceiv_reset)
259 musb->board->xceiv_reset();
261 /* then we resume to sync with controller */
262 r = musb_readb(musb->mregs, MUSB_POWER);
263 musb_writeb(musb->mregs, MUSB_POWER,
264 r | MUSB_POWER_RESUME);
266 musb_writeb(musb->mregs, MUSB_POWER,
267 r & ~MUSB_POWER_RESUME);
269 /* now we set SW control bit in PWR_CTRL register */
270 musb_ulpi_writeb(musb->mregs, ISP1704_PWR_CTRL,
271 ISP1704_PWR_CTRL_SWCTRL);
273 r = musb_ulpi_readb(musb->mregs, ISP1704_PWR_CTRL);
274 r |= (ISP1704_PWR_CTRL_SWCTRL | ISP1704_PWR_CTRL_DPVSRC_EN);
276 /* and finally enable manual charger detection */
277 musb_ulpi_writeb(musb->mregs, ISP1704_PWR_CTRL, r);
280 timeout = jiffies + msecs_to_jiffies(300);
281 while (!time_after(jiffies, timeout)) {
282 /* Check if there is a charger */
283 vdat = !!(musb_ulpi_readb(musb->mregs, ISP1704_PWR_CTRL)
284 & ISP1704_PWR_CTRL_VDAT_DET);
289 vdat = musb_verify_charger(musb->mregs);
291 r &= ~ISP1704_PWR_CTRL_DPVSRC_EN;
293 /* Clear DPVSRC_EN, otherwise usb communication doesn't work */
294 musb_ulpi_writeb(musb->mregs, ISP1704_PWR_CTRL, r);
302 /* enable interrupts */
303 musb_writeb(musb->mregs, MUSB_INTRUSBE, ctx.intrusbe);
305 /* Make sure the communication starts normally */
306 r = musb_readb(musb->mregs, MUSB_POWER);
307 musb_writeb(musb->mregs, MUSB_POWER,
308 r | MUSB_POWER_RESUME);
310 musb_writeb(musb->mregs, MUSB_POWER,
311 r & ~MUSB_POWER_RESUME);
312 if (vdat && musb->xceiv->state != OTG_STATE_B_IDLE) {
315 otg_set_suspend(musb->xceiv, 1);
318 musb->is_charger = vdat;
324 /*-------------------------------------------------------------------------*/
326 static inline struct musb *dev_to_musb(struct device *dev)
328 #ifdef CONFIG_USB_MUSB_HDRC_HCD
329 /* usbcore insists dev->driver_data is a "struct hcd *" */
330 return hcd_to_musb(dev_get_drvdata(dev));
332 return dev_get_drvdata(dev);
336 /*-------------------------------------------------------------------------*/
338 #if !defined(CONFIG_USB_TUSB6010) && !defined(CONFIG_BLACKFIN)
341 * Load an endpoint's FIFO
343 void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
345 void __iomem *fifo = hw_ep->fifo;
349 DBG_nonverb(4, "%cX ep%d fifo %p count %d buf %p\n",
350 'T', hw_ep->epnum, fifo, len, src);
352 /* we can't assume unaligned reads work */
353 if (likely((0x01 & (unsigned long) src) == 0)) {
356 /* best case is 32bit-aligned source address */
357 if ((0x02 & (unsigned long) src) == 0) {
359 writesl(fifo, src + index, len >> 2);
360 index += len & ~0x03;
363 musb_writew(fifo, 0, *(u16 *)&src[index]);
368 writesw(fifo, src + index, len >> 1);
369 index += len & ~0x01;
373 musb_writeb(fifo, 0, src[index]);
376 writesb(fifo, src, len);
381 * Unload an endpoint's FIFO
383 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
385 void __iomem *fifo = hw_ep->fifo;
387 DBG_nonverb(4, "%cX ep%d fifo %p count %d buf %p\n",
388 'R', hw_ep->epnum, fifo, len, dst);
390 /* we can't assume unaligned writes work */
391 if (likely((0x01 & (unsigned long) dst) == 0)) {
394 /* best case is 32bit-aligned destination address */
395 if ((0x02 & (unsigned long) dst) == 0) {
397 readsl(fifo, dst, len >> 2);
401 *(u16 *)&dst[index] = musb_readw(fifo, 0);
406 readsw(fifo, dst, len >> 1);
411 dst[index] = musb_readb(fifo, 0);
414 readsb(fifo, dst, len);
418 #endif /* normal PIO */
421 /*-------------------------------------------------------------------------*/
423 /* for high speed test mode; see USB 2.0 spec 7.1.20 */
424 static const u8 musb_test_packet[53] = {
425 /* implicit SYNC then DATA0 to start */
428 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
430 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
432 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee, 0xee,
433 /* JJJJJJJKKKKKKK x8 */
434 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
436 0x7f, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd,
437 /* JKKKKKKK x10, JK */
438 0xfc, 0x7e, 0xbf, 0xdf, 0xef, 0xf7, 0xfb, 0xfd, 0x7e
440 /* implicit CRC16 then EOP to end */
443 void musb_load_testpacket(struct musb *musb)
445 void __iomem *regs = musb->endpoints[0].regs;
447 musb_ep_select(musb->mregs, 0);
448 musb_write_fifo(musb->control_ep,
449 sizeof(musb_test_packet), musb_test_packet);
450 musb_writew(regs, MUSB_CSR0, MUSB_CSR0_TXPKTRDY);
453 /*-------------------------------------------------------------------------*/
455 const char *otg_state_string(struct musb *musb)
457 switch (musb->xceiv->state) {
458 case OTG_STATE_A_IDLE: return "a_idle";
459 case OTG_STATE_A_WAIT_VRISE: return "a_wait_vrise";
460 case OTG_STATE_A_WAIT_BCON: return "a_wait_bcon";
461 case OTG_STATE_A_HOST: return "a_host";
462 case OTG_STATE_A_SUSPEND: return "a_suspend";
463 case OTG_STATE_A_PERIPHERAL: return "a_peripheral";
464 case OTG_STATE_A_WAIT_VFALL: return "a_wait_vfall";
465 case OTG_STATE_A_VBUS_ERR: return "a_vbus_err";
466 case OTG_STATE_B_IDLE: return "b_idle";
467 case OTG_STATE_B_SRP_INIT: return "b_srp_init";
468 case OTG_STATE_B_PERIPHERAL: return "b_peripheral";
469 case OTG_STATE_B_WAIT_ACON: return "b_wait_acon";
470 case OTG_STATE_B_HOST: return "b_host";
471 default: return "UNDEFINED";
475 #ifdef CONFIG_USB_MUSB_OTG
478 * See also USB_OTG_1-3.pdf 6.6.5 Timers
479 * REVISIT: Are the other timers done in the hardware?
481 #define TB_ASE0_BRST 100 /* Min 3.125 ms */
484 * Handles OTG hnp timeouts, such as b_ase0_brst
486 void musb_otg_timer_func(unsigned long data)
488 struct musb *musb = (struct musb *)data;
491 spin_lock_irqsave(&musb->lock, flags);
492 switch (musb->xceiv->state) {
493 case OTG_STATE_B_WAIT_ACON:
494 DBG(1, "HNP: b_wait_acon timeout; back to b_peripheral\n");
495 musb_g_disconnect(musb);
496 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
499 case OTG_STATE_A_WAIT_BCON:
500 DBG(1, "HNP: a_wait_bcon timeout; back to a_host\n");
504 DBG(1, "HNP: Unhandled mode %s\n", otg_state_string(musb));
506 musb->ignore_disconnect = 0;
507 spin_unlock_irqrestore(&musb->lock, flags);
510 static DEFINE_TIMER(musb_otg_timer, musb_otg_timer_func, 0, 0);
513 * Stops the B-device HNP state. Caller must take care of locking.
515 void musb_hnp_stop(struct musb *musb)
517 struct usb_hcd *hcd = musb_to_hcd(musb);
518 void __iomem *mbase = musb->mregs;
521 switch (musb->xceiv->state) {
522 case OTG_STATE_A_PERIPHERAL:
523 case OTG_STATE_A_WAIT_VFALL:
524 case OTG_STATE_A_WAIT_BCON:
525 DBG(1, "HNP: Switching back to A-host\n");
526 musb_g_disconnect(musb);
527 musb->xceiv->state = OTG_STATE_A_IDLE;
531 case OTG_STATE_B_HOST:
532 DBG(1, "HNP: Disabling HR\n");
533 hcd->self.is_b_host = 0;
534 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
536 reg = musb_readb(mbase, MUSB_POWER);
537 reg |= MUSB_POWER_SUSPENDM;
538 musb_writeb(mbase, MUSB_POWER, reg);
539 /* REVISIT: Start SESSION_REQUEST here? */
542 DBG(1, "HNP: Stopping in unknown state %s\n",
543 otg_state_string(musb));
547 * When returning to A state after HNP, avoid hub_port_rebounce(),
548 * which cause occasional OPT A "Did not receive reset after connect"
551 musb->port1_status &=
552 ~(1 << USB_PORT_FEAT_C_CONNECTION);
558 * Interrupt Service Routine to record USB "global" interrupts.
559 * Since these do not happen often and signify things of
560 * paramount importance, it seems OK to check them individually;
561 * the order of the tests is specified in the manual
563 * @param musb instance pointer
564 * @param int_usb register contents
569 static irqreturn_t musb_stage0_irq(struct musb *musb, u8 int_usb,
572 irqreturn_t handled = IRQ_NONE;
573 void __iomem *mbase = musb->mregs;
575 u8 testmode = musb_readb(musb->mregs, MUSB_TESTMODE);
577 DBG(3, "<== State=%s Testmode=%02x Power=%02x, DevCtl=%02x, int_usb=0x%x\n",
578 otg_state_string(musb), testmode, power, devctl, int_usb);
580 /* in host mode, the peripheral may issue remote wakeup.
581 * in peripheral mode, the host may resume the link.
582 * spurious RESUME irqs happen too, paired with SUSPEND.
584 if (int_usb & MUSB_INTR_RESUME) {
585 handled = IRQ_HANDLED;
586 DBG(3, "RESUME (%s)\n", otg_state_string(musb));
588 if (devctl & MUSB_DEVCTL_HM) {
589 #ifdef CONFIG_USB_MUSB_HDRC_HCD
590 switch (musb->xceiv->state) {
591 case OTG_STATE_A_SUSPEND:
592 /* remote wakeup? later, GetPortStatus
593 * will stop RESUME signaling
596 if (power & MUSB_POWER_SUSPENDM) {
598 musb->int_usb &= ~MUSB_INTR_SUSPEND;
599 DBG(2, "Spurious SUSPENDM\n");
603 power &= ~MUSB_POWER_SUSPENDM;
604 musb_writeb(mbase, MUSB_POWER,
605 power | MUSB_POWER_RESUME);
607 musb->port1_status |=
608 (USB_PORT_STAT_C_SUSPEND << 16)
609 | MUSB_PORT_STAT_RESUME;
610 musb->rh_timer = jiffies
611 + msecs_to_jiffies(20);
613 musb->xceiv->state = OTG_STATE_A_HOST;
615 usb_hcd_resume_root_hub(musb_to_hcd(musb));
617 case OTG_STATE_B_WAIT_ACON:
618 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
623 WARNING("bogus %s RESUME (%s)\n",
625 otg_state_string(musb));
629 switch (musb->xceiv->state) {
630 #ifdef CONFIG_USB_MUSB_HDRC_HCD
631 case OTG_STATE_A_SUSPEND:
632 /* possibly DISCONNECT is upcoming */
633 musb->xceiv->state = OTG_STATE_A_HOST;
634 usb_hcd_resume_root_hub(musb_to_hcd(musb));
637 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
638 case OTG_STATE_B_WAIT_ACON:
639 case OTG_STATE_B_PERIPHERAL:
640 /* disconnect while suspended? we may
641 * not get a disconnect irq...
643 if ((devctl & MUSB_DEVCTL_VBUS)
644 != (3 << MUSB_DEVCTL_VBUS_SHIFT)
646 musb->int_usb |= MUSB_INTR_DISCONNECT;
647 musb->int_usb &= ~MUSB_INTR_SUSPEND;
652 case OTG_STATE_B_IDLE:
653 musb->int_usb &= ~MUSB_INTR_SUSPEND;
657 WARNING("bogus %s RESUME (%s)\n",
659 otg_state_string(musb));
664 #ifdef CONFIG_USB_MUSB_HDRC_HCD
665 /* see manual for the order of the tests */
666 if (int_usb & MUSB_INTR_SESSREQ) {
667 DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(musb));
669 /* IRQ arrives from ID pin sense or (later, if VBUS power
670 * is removed) SRP. responses are time critical:
671 * - turn on VBUS (with silicon-specific mechanism)
672 * - go through A_WAIT_VRISE
673 * - ... to A_WAIT_BCON.
674 * a_wait_vrise_tmout triggers VBUS_ERROR transitions
675 * NOTE : Spurious SESS_REQ int's detected, which should
676 * be discarded silently.
678 if ((devctl & MUSB_DEVCTL_VBUS)
679 && !(devctl & MUSB_DEVCTL_BDEVICE)) {
680 musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
681 musb->ep0_stage = MUSB_EP0_START;
682 musb->xceiv->state = OTG_STATE_A_IDLE;
684 musb_set_vbus(musb, 1);
686 DBG(5,"discarding SESSREQ INT: VBUS < SessEnd\n");
689 handled = IRQ_HANDLED;
692 if (int_usb & MUSB_INTR_VBUSERROR) {
695 /* During connection as an A-Device, we may see a short
696 * current spikes causing voltage drop, because of cable
697 * and peripheral capacitance combined with vbus draw.
698 * (So: less common with truly self-powered devices, where
699 * vbus doesn't act like a power supply.)
701 * Such spikes are short; usually less than ~500 usec, max
702 * of ~2 msec. That is, they're not sustained overcurrent
703 * errors, though they're reported using VBUSERROR irqs.
705 * Workarounds: (a) hardware: use self powered devices.
706 * (b) software: ignore non-repeated VBUS errors.
708 * REVISIT: do delays from lots of DEBUG_KERNEL checks
709 * make trouble here, keeping VBUS < 4.4V ?
711 switch (musb->xceiv->state) {
712 case OTG_STATE_A_HOST:
713 /* recovery is dicey once we've gotten past the
714 * initial stages of enumeration, but if VBUS
715 * stayed ok at the other end of the link, and
716 * another reset is due (at least for high speed,
717 * to redo the chirp etc), it might work OK...
719 case OTG_STATE_A_WAIT_BCON:
720 case OTG_STATE_A_WAIT_VRISE:
721 if (musb->vbuserr_retry) {
722 musb->vbuserr_retry--;
724 devctl |= MUSB_DEVCTL_SESSION;
725 musb_writeb(mbase, MUSB_DEVCTL, devctl);
727 musb->port1_status |=
728 (1 << USB_PORT_FEAT_OVER_CURRENT)
729 | (1 << USB_PORT_FEAT_C_OVER_CURRENT);
736 DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
737 otg_state_string(musb),
740 switch (devctl & MUSB_DEVCTL_VBUS) {
741 case 0 << MUSB_DEVCTL_VBUS_SHIFT:
742 s = "<SessEnd"; break;
743 case 1 << MUSB_DEVCTL_VBUS_SHIFT:
744 s = "<AValid"; break;
745 case 2 << MUSB_DEVCTL_VBUS_SHIFT:
746 s = "<VBusValid"; break;
747 /* case 3 << MUSB_DEVCTL_VBUS_SHIFT: */
751 VBUSERR_RETRY_COUNT - musb->vbuserr_retry,
754 /* go through A_WAIT_VFALL then start a new session */
756 musb_set_vbus(musb, 0);
757 handled = IRQ_HANDLED;
760 if (int_usb & MUSB_INTR_SUSPEND) {
761 DBG(1, "SUSPEND (%s) devctl %02x power %02x\n",
762 otg_state_string(musb), devctl, power);
763 handled = IRQ_HANDLED;
765 switch (musb->xceiv->state) {
766 #ifdef CONFIG_USB_MUSB_OTG
767 case OTG_STATE_A_PERIPHERAL:
769 * We cannot stop HNP here, devctl BDEVICE might be
774 case OTG_STATE_B_IDLE:
775 if (!musb->is_active)
777 case OTG_STATE_B_PERIPHERAL:
778 musb_g_suspend(musb);
779 musb->is_active = is_otg_enabled(musb)
780 && musb->xceiv->gadget->b_hnp_enable;
781 if (musb->is_active) {
782 #ifdef CONFIG_USB_MUSB_OTG
783 musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
784 DBG(1, "HNP: Setting timer for b_ase0_brst\n");
785 musb_otg_timer.data = (unsigned long)musb;
786 mod_timer(&musb_otg_timer, jiffies
787 + msecs_to_jiffies(TB_ASE0_BRST));
791 case OTG_STATE_A_WAIT_BCON:
792 if (musb->a_wait_bcon != 0)
793 musb_platform_try_idle(musb, jiffies
794 + msecs_to_jiffies(musb->a_wait_bcon));
796 case OTG_STATE_A_HOST:
797 musb->xceiv->state = OTG_STATE_A_SUSPEND;
798 musb->is_active = is_otg_enabled(musb)
799 && musb->xceiv->host->b_hnp_enable;
801 case OTG_STATE_B_HOST:
802 /* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
803 DBG(1, "REVISIT: SUSPEND as B_HOST\n");
806 /* "should not happen" */
812 if (int_usb & MUSB_INTR_CONNECT) {
813 struct usb_hcd *hcd = musb_to_hcd(musb);
815 handled = IRQ_HANDLED;
817 set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
819 musb->ep0_stage = MUSB_EP0_START;
821 #ifdef CONFIG_USB_MUSB_OTG
822 /* flush endpoints when transitioning from Device Mode */
823 if (is_peripheral_active(musb)) {
824 /* REVISIT HNP; just force disconnect */
826 musb_writew(mbase, MUSB_INTRTXE, musb->epmask);
827 musb_writew(mbase, MUSB_INTRRXE, musb->epmask & 0xfffe);
828 musb_writeb(mbase, MUSB_INTRUSBE, 0xf7);
830 musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
831 |USB_PORT_STAT_HIGH_SPEED
832 |USB_PORT_STAT_ENABLE
834 musb->port1_status |= USB_PORT_STAT_CONNECTION
835 |(USB_PORT_STAT_C_CONNECTION << 16);
837 /* high vs full speed is just a guess until after reset */
838 if (devctl & MUSB_DEVCTL_LSDEV)
839 musb->port1_status |= USB_PORT_STAT_LOW_SPEED;
842 usb_hcd_poll_rh_status(hcd);
844 usb_hcd_resume_root_hub(hcd);
848 /* indicate new connection to OTG machine */
849 switch (musb->xceiv->state) {
850 case OTG_STATE_B_PERIPHERAL:
851 if (int_usb & MUSB_INTR_SUSPEND) {
852 DBG(1, "HNP: SUSPEND+CONNECT, now b_host\n");
853 musb->xceiv->state = OTG_STATE_B_HOST;
854 hcd->self.is_b_host = 1;
855 int_usb &= ~MUSB_INTR_SUSPEND;
857 DBG(1, "CONNECT as b_peripheral???\n");
859 case OTG_STATE_B_WAIT_ACON:
860 DBG(1, "HNP: Waiting to switch to b_host state\n");
861 musb->xceiv->state = OTG_STATE_B_HOST;
862 hcd->self.is_b_host = 1;
865 if ((devctl & MUSB_DEVCTL_VBUS)
866 == (3 << MUSB_DEVCTL_VBUS_SHIFT)) {
867 musb->xceiv->state = OTG_STATE_A_HOST;
868 hcd->self.is_b_host = 0;
872 DBG(1, "CONNECT (%s) devctl %02x\n",
873 otg_state_string(musb), devctl);
875 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
877 if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
878 DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n",
879 otg_state_string(musb),
880 MUSB_MODE(musb), devctl);
881 handled = IRQ_HANDLED;
883 switch (musb->xceiv->state) {
884 #ifdef CONFIG_USB_MUSB_HDRC_HCD
885 case OTG_STATE_A_HOST:
886 case OTG_STATE_A_SUSPEND:
887 usb_hcd_resume_root_hub(musb_to_hcd(musb));
888 musb_root_disconnect(musb);
889 if (musb->a_wait_bcon != 0 && is_otg_enabled(musb))
890 musb_platform_try_idle(musb, jiffies
891 + msecs_to_jiffies(musb->a_wait_bcon));
894 #ifdef CONFIG_USB_MUSB_OTG
895 case OTG_STATE_B_HOST:
898 case OTG_STATE_A_PERIPHERAL:
900 musb_root_disconnect(musb);
902 case OTG_STATE_B_WAIT_ACON:
905 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
906 case OTG_STATE_B_PERIPHERAL:
907 case OTG_STATE_B_IDLE:
908 /* Workaround for a problem of Vbus quickly dropping
909 * during Certification tests.
911 * Undo the workaround on disconnect
914 /* Disable suspend so we can write to ULPI */
915 r = musb_readb(musb->mregs, MUSB_POWER);
916 musb_writeb(musb->mregs, MUSB_POWER,
917 r & ~MUSB_POWER_ENSUSPEND);
918 musb_ulpi_writeb(musb->mregs,
919 ISP1704_USB_INTFALL, 0x1f);
920 musb_ulpi_writeb(musb->mregs,
921 ISP1704_USB_INTRISE, 0x1f);
922 musb_writeb(musb->mregs, MUSB_POWER,
923 r | MUSB_POWER_ENSUSPEND);
925 musb_g_disconnect(musb);
926 /** UGLY UGLY HACK: Windows problems with multiple
929 * This is necessary to notify gadget driver this was
930 * a physical disconnection and not only a port reset.
932 if (musb->gadget_driver->vbus_disconnect)
933 musb->gadget_driver->vbus_disconnect(&musb->g);
938 WARNING("unhandled DISCONNECT transition (%s)\n",
939 otg_state_string(musb));
944 /* mentor saves a bit: bus reset and babble share the same irq.
945 * only host sees babble; only peripheral sees bus reset.
947 if (int_usb & MUSB_INTR_RESET) {
948 handled = IRQ_HANDLED;
949 if (is_host_capable() && (devctl & MUSB_DEVCTL_HM) != 0) {
951 * Looks like non-HS BABBLE can be ignored, but
952 * HS BABBLE is an error condition. For HS the solution
953 * is to avoid babble in the first place and fix what
954 * caused BABBLE. When HS BABBLE happens we can only
957 if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
958 DBG(1, "BABBLE devctl: %02x\n", devctl);
960 ERR("Stopping host session -- babble\n");
961 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
963 } else if (is_peripheral_capable()) {
964 DBG(1, "BUS RESET as %s\n", otg_state_string(musb));
965 switch (musb->xceiv->state) {
966 #ifdef CONFIG_USB_OTG
967 case OTG_STATE_A_SUSPEND:
968 /* We need to ignore disconnect on suspend
969 * otherwise tusb 2.0 won't reconnect after a
970 * power cycle, which breaks otg compliance.
972 musb->ignore_disconnect = 1;
975 case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
976 DBG(1, "HNP: Setting timer as %s\n",
977 otg_state_string(musb));
978 musb_otg_timer.data = (unsigned long)musb;
979 mod_timer(&musb_otg_timer, jiffies
980 + msecs_to_jiffies(100));
982 case OTG_STATE_A_PERIPHERAL:
985 case OTG_STATE_B_WAIT_ACON:
986 DBG(1, "HNP: RESET (%s), to b_peripheral\n",
987 otg_state_string(musb));
988 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
992 case OTG_STATE_B_IDLE:
993 /* Workaround the charger detection problems */
994 if ((devctl & MUSB_DEVCTL_VBUS)
995 != (3 << MUSB_DEVCTL_VBUS_SHIFT))
999 musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
1001 case OTG_STATE_B_PERIPHERAL:
1002 /* Workaround for a problem of Vbus quickly dropping
1003 * during Certification tests.
1005 * The guess is that vbus drops due to the circuitry
1006 * for overcurrent protection and that makes transceiver
1007 * think VBUS is not valid anymore. Transceiver will
1008 * then send an RXCMD to PHY which will cause it to
1009 * disconnect from the bus even though we disable the
1012 musb_ulpi_writeb(musb->mregs,
1013 ISP1704_USB_INTFALL, 0x1d);
1014 musb_ulpi_writeb(musb->mregs,
1015 ISP1704_USB_INTRISE, 0x1d);
1020 DBG(1, "Unhandled BUS RESET as %s\n",
1021 otg_state_string(musb));
1027 /* REVISIT ... this would be for multiplexing periodic endpoints, or
1028 * supporting transfer phasing to prevent exceeding ISO bandwidth
1029 * limits of a given frame or microframe.
1031 * It's not needed for peripheral side, which dedicates endpoints;
1032 * though it _might_ use SOF irqs for other purposes.
1034 * And it's not currently needed for host side, which also dedicates
1035 * endpoints, relies on TX/RX interval registers, and isn't claimed
1036 * to support ISO transfers yet.
1038 if (int_usb & MUSB_INTR_SOF) {
1039 void __iomem *mbase = musb->mregs;
1040 struct musb_hw_ep *ep;
1044 DBG(6, "START_OF_FRAME\n");
1045 handled = IRQ_HANDLED;
1047 /* start any periodic Tx transfers waiting for current frame */
1048 frame = musb_readw(mbase, MUSB_FRAME);
1049 ep = musb->endpoints;
1050 for (epnum = 1; (epnum < musb->nr_endpoints)
1051 && (musb->epmask >= (1 << epnum));
1054 * FIXME handle framecounter wraps (12 bits)
1055 * eliminate duplicated StartUrb logic
1057 if (ep->dwWaitFrame >= frame) {
1058 ep->dwWaitFrame = 0;
1059 pr_debug("SOF --> periodic TX%s on %d\n",
1060 ep->tx_channel ? " DMA" : "",
1062 if (!ep->tx_channel)
1063 musb_h_tx_start(musb, epnum);
1065 cppi_hostdma_start(musb, epnum);
1067 } /* end of for loop */
1071 schedule_work(&musb->irq_work);
1076 /*-------------------------------------------------------------------------*/
1079 * Program the HDRC to start (enable interrupts, dma, etc.).
1081 void musb_start(struct musb *musb)
1083 void __iomem *regs = musb->mregs;
1084 u8 devctl = musb_readb(regs, MUSB_DEVCTL);
1087 DBG(2, "<== devctl %02x\n", devctl);
1089 /* Ensure the clocks are on */
1090 if (musb->set_clock)
1091 musb->set_clock(musb->clock, 1);
1093 clk_enable(musb->clock);
1095 /* Set INT enable registers, enable interrupts */
1096 musb_writew(regs, MUSB_INTRTXE, musb->epmask);
1097 musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
1098 musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
1100 musb_writeb(regs, MUSB_TESTMODE, 0);
1102 power = MUSB_POWER_ISOUPDATE | MUSB_POWER_SOFTCONN
1103 | MUSB_POWER_HSENAB;
1105 /* ENSUSPEND wedges tusb */
1107 power |= MUSB_POWER_ENSUSPEND;
1109 /* put into basic highspeed mode and start session */
1110 musb_writeb(regs, MUSB_POWER, power);
1112 musb->is_active = 0;
1113 devctl = musb_readb(regs, MUSB_DEVCTL);
1114 devctl &= ~MUSB_DEVCTL_SESSION;
1116 if (is_otg_enabled(musb)) {
1117 /* session started after:
1118 * (a) ID-grounded irq, host mode;
1119 * (b) vbus present/connect IRQ, peripheral mode;
1120 * (c) peripheral initiates, using SRP
1122 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
1123 musb->is_active = 1;
1125 devctl |= MUSB_DEVCTL_SESSION;
1127 } else if (is_host_enabled(musb)) {
1128 /* assume ID pin is hard-wired to ground */
1129 devctl |= MUSB_DEVCTL_SESSION;
1131 } else /* peripheral is enabled */ {
1132 if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS)
1133 musb->is_active = 1;
1135 musb_platform_enable(musb);
1136 musb_writeb(regs, MUSB_DEVCTL, devctl);
1140 static void musb_generic_disable(struct musb *musb)
1142 void __iomem *mbase = musb->mregs;
1145 /* Clocks need to be turned on with OFF-mode */
1146 if (musb->set_clock)
1147 musb->set_clock(musb->clock, 1);
1149 clk_enable(musb->clock);
1151 /* disable interrupts */
1152 musb_writeb(mbase, MUSB_INTRUSBE, 0);
1153 musb_writew(mbase, MUSB_INTRTXE, 0);
1154 musb_writew(mbase, MUSB_INTRRXE, 0);
1157 musb_writeb(mbase, MUSB_DEVCTL, 0);
1159 /* flush pending interrupts */
1160 temp = musb_readb(mbase, MUSB_INTRUSB);
1161 temp = musb_readw(mbase, MUSB_INTRTX);
1162 temp = musb_readw(mbase, MUSB_INTRRX);
1166 void musb_emergency_stop(void)
1171 musb_stop(the_musb);
1173 EXPORT_SYMBOL_GPL(musb_emergency_stop);
1176 * Make the HDRC stop (disable interrupts, etc.);
1177 * reversible by musb_start
1178 * called on gadget driver unregister
1179 * with controller locked, irqs blocked
1180 * acts as a NOP unless some role activated the hardware
1182 void musb_stop(struct musb *musb)
1184 /* stop IRQs, timers, ... */
1185 musb_platform_disable(musb);
1186 musb_generic_disable(musb);
1187 DBG(3, "HDRC disabled\n");
1190 * - mark host and/or peripheral drivers unusable/inactive
1191 * - disable DMA (and enable it in HdrcStart)
1192 * - make sure we can musb_start() after musb_stop(); with
1193 * OTG mode, gadget driver module rmmod/modprobe cycles that
1196 musb_platform_try_idle(musb, 0);
1199 static void musb_shutdown(struct platform_device *pdev)
1201 struct musb *musb = dev_to_musb(&pdev->dev);
1202 unsigned long flags;
1204 spin_lock_irqsave(&musb->lock, flags);
1205 musb_platform_disable(musb);
1206 musb_generic_disable(musb);
1208 clk_put(musb->clock);
1211 spin_unlock_irqrestore(&musb->lock, flags);
1213 /* FIXME power down */
1217 /*-------------------------------------------------------------------------*/
1220 * The silicon either has hard-wired endpoint configurations, or else
1221 * "dynamic fifo" sizing. The driver has support for both, though at this
1222 * writing only the dynamic sizing is very well tested. Since we switched
1223 * away from compile-time hardware parameters, we can no longer rely on
1224 * dead code elimination to leave only the relevant one in the object file.
1226 * We don't currently use dynamic fifo setup capability to do anything
1227 * more than selecting one of a bunch of predefined configurations.
1229 #if defined(CONFIG_USB_TUSB6010) || \
1230 defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
1231 static ushort __initdata fifo_mode = 4;
1233 static ushort __initdata fifo_mode = 2;
1236 /* "modprobe ... fifo_mode=1" etc */
1237 module_param(fifo_mode, ushort, 0);
1238 MODULE_PARM_DESC(fifo_mode, "initial endpoint configuration");
1241 enum fifo_style { FIFO_RXTX, FIFO_TX, FIFO_RX } __attribute__ ((packed));
1242 enum buf_mode { BUF_SINGLE, BUF_DOUBLE } __attribute__ ((packed));
1246 enum fifo_style style;
1252 * tables defining fifo_mode values. define more if you like.
1253 * for host side, make sure both halves of ep1 are set up.
1256 /* mode 0 - fits in 2KB */
1257 static struct fifo_cfg __initdata mode_0_cfg[] = {
1258 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1259 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1260 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, },
1261 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1262 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1265 /* mode 1 - fits in 4KB */
1266 static struct fifo_cfg __initdata mode_1_cfg[] = {
1267 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1268 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1269 { .hw_ep_num = 2, .style = FIFO_RXTX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1270 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1271 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1274 /* mode 2 - fits in 4KB */
1275 static struct fifo_cfg __initdata mode_2_cfg[] = {
1276 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1277 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1278 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1279 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1280 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1281 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1284 /* mode 3 - fits in 4KB */
1285 static struct fifo_cfg __initdata mode_3_cfg[] = {
1286 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1287 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_DOUBLE, },
1288 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1289 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1290 { .hw_ep_num = 3, .style = FIFO_RXTX, .maxpacket = 256, },
1291 { .hw_ep_num = 4, .style = FIFO_RXTX, .maxpacket = 256, },
1294 /* mode 4 - fits in 16KB */
1295 static struct fifo_cfg __initdata mode_4_cfg[] = {
1296 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
1297 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
1298 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
1299 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
1300 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
1301 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
1302 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
1303 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
1304 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
1305 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
1306 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
1307 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1308 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
1309 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1310 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1311 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 64, },
1312 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1313 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 64, },
1314 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 512, },
1315 { .hw_ep_num = 10, .style = FIFO_RX, .maxpacket = 64, },
1316 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 256, },
1317 { .hw_ep_num = 11, .style = FIFO_RX, .maxpacket = 256, },
1318 { .hw_ep_num = 12, .style = FIFO_TX, .maxpacket = 256, },
1319 { .hw_ep_num = 12, .style = FIFO_RX, .maxpacket = 256, },
1320 { .hw_ep_num = 13, .style = FIFO_TX, .maxpacket = 256, },
1321 { .hw_ep_num = 13, .style = FIFO_RX, .maxpacket = 4096, },
1322 { .hw_ep_num = 14, .style = FIFO_RXTX, .maxpacket = 1024, },
1323 { .hw_ep_num = 15, .style = FIFO_RXTX, .maxpacket = 1024, },
1326 /* mode 5 - fits in 16KB */
1327 static struct fifo_cfg __initdata mode_5_cfg[] = {
1328 /* phonet or mass storage */
1329 { .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_SINGLE, },
1330 { .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_SINGLE, },
1333 { .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_SINGLE, },
1334 { .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_SINGLE, },
1337 { .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_SINGLE, },
1338 { .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_SINGLE, },
1341 { .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_SINGLE, },
1342 { .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_SINGLE, },
1343 { .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 16, },
1346 { .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, .mode = BUF_SINGLE, },
1347 { .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, .mode = BUF_SINGLE, },
1348 { .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 16, },
1351 { .hw_ep_num = 8, .style = FIFO_TX, .maxpacket = 512, },
1352 { .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
1354 { .hw_ep_num = 9, .style = FIFO_TX, .maxpacket = 512, },
1355 { .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
1357 { .hw_ep_num = 10, .style = FIFO_TX, .maxpacket = 512, },
1358 { .hw_ep_num = 8, .style = FIFO_RX, .maxpacket = 512, },
1360 { .hw_ep_num = 11, .style = FIFO_TX, .maxpacket = 512, },
1361 { .hw_ep_num = 9, .style = FIFO_RX, .maxpacket = 512, },
1365 * configure a fifo; for non-shared endpoints, this may be called
1366 * once for a tx fifo and once for an rx fifo.
1368 * returns negative errno or offset for next fifo.
1371 fifo_setup(struct musb *musb, struct musb_hw_ep *hw_ep,
1372 const struct fifo_cfg *cfg, u16 offset)
1374 void __iomem *mbase = musb->mregs;
1376 u16 maxpacket = cfg->maxpacket;
1377 u16 c_off = offset >> 3;
1380 /* expect hw_ep has already been zero-initialized */
1382 size = ffs(max(maxpacket, (u16) 8)) - 1;
1383 maxpacket = 1 << size;
1386 if (cfg->mode == BUF_DOUBLE) {
1387 if ((offset + (maxpacket << 1)) >
1388 (1 << (musb->config->ram_bits + 2)))
1390 c_size |= MUSB_FIFOSZ_DPB;
1392 if ((offset + maxpacket) > (1 << (musb->config->ram_bits + 2)))
1396 /* configure the FIFO */
1397 musb_writeb(mbase, MUSB_INDEX, hw_ep->epnum);
1399 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1400 /* EP0 reserved endpoint for control, bidirectional;
1401 * EP1 reserved for bulk, two unidirection halves.
1403 if (hw_ep->epnum == 1)
1404 musb->bulk_ep = hw_ep;
1405 /* REVISIT error check: be sure ep0 can both rx and tx ... */
1407 switch (cfg->style) {
1409 musb_write_txfifosz(mbase, c_size);
1410 musb_write_txfifoadd(mbase, c_off);
1411 hw_ep->tx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1412 hw_ep->max_packet_sz_tx = maxpacket;
1413 ctx.txfifosz[hw_ep->epnum] = c_size;
1414 ctx.txfifoadd[hw_ep->epnum] = c_off;
1417 musb_write_rxfifosz(mbase, c_size);
1418 musb_write_rxfifoadd(mbase, c_off);
1419 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1420 hw_ep->max_packet_sz_rx = maxpacket;
1421 ctx.rxfifosz[hw_ep->epnum] = c_size;
1422 ctx.rxfifoadd[hw_ep->epnum] = c_off;
1425 musb_write_txfifosz(mbase, c_size);
1426 musb_write_txfifoadd(mbase, c_off);
1427 hw_ep->rx_double_buffered = !!(c_size & MUSB_FIFOSZ_DPB);
1428 hw_ep->max_packet_sz_rx = maxpacket;
1430 musb_write_rxfifosz(mbase, c_size);
1431 musb_write_rxfifoadd(mbase, c_off);
1432 hw_ep->tx_double_buffered = hw_ep->rx_double_buffered;
1433 hw_ep->max_packet_sz_tx = maxpacket;
1435 /* Save the context of endpoints. */
1436 ctx.rxfifosz[hw_ep->epnum] = c_size;
1437 ctx.txfifosz[hw_ep->epnum] = c_size;
1438 ctx.txfifoadd[hw_ep->epnum] = c_off;
1439 ctx.rxfifoadd[hw_ep->epnum] = c_off;
1441 hw_ep->is_shared_fifo = true;
1445 /* NOTE rx and tx endpoint irqs aren't managed separately,
1446 * which happens to be ok
1448 musb->epmask |= (1 << hw_ep->epnum);
1450 return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
1453 static struct fifo_cfg __initdata ep0_cfg = {
1454 .style = FIFO_RXTX, .maxpacket = 64,
1457 static int __init ep_config_from_table(struct musb *musb)
1459 const struct fifo_cfg *cfg;
1462 struct musb_hw_ep *hw_ep = musb->endpoints;
1464 if (machine_is_nokia_rx51())
1467 switch (fifo_mode) {
1473 n = ARRAY_SIZE(mode_0_cfg);
1477 n = ARRAY_SIZE(mode_1_cfg);
1481 n = ARRAY_SIZE(mode_2_cfg);
1485 n = ARRAY_SIZE(mode_3_cfg);
1489 n = ARRAY_SIZE(mode_4_cfg);
1493 n = ARRAY_SIZE(mode_5_cfg);
1497 printk(KERN_DEBUG "%s: setup fifo_mode %d\n",
1498 musb_driver_name, fifo_mode);
1501 offset = fifo_setup(musb, hw_ep, &ep0_cfg, 0);
1502 /* assert(offset > 0) */
1504 /* NOTE: for RTL versions >= 1.400 EPINFO and RAMINFO would
1505 * be better than static musb->config->num_eps and DYN_FIFO_SIZE...
1508 for (i = 0; i < n; i++) {
1509 u8 epn = cfg->hw_ep_num;
1511 if (epn >= musb->config->num_eps) {
1512 pr_debug("%s: invalid ep %d\n",
1513 musb_driver_name, epn);
1516 offset = fifo_setup(musb, hw_ep + epn, cfg++, offset);
1518 pr_debug("%s: mem overrun, ep %d\n",
1519 musb_driver_name, epn);
1523 musb->nr_endpoints = max(epn, musb->nr_endpoints);
1526 printk(KERN_DEBUG "%s: %d/%d max ep, %d/%d memory\n",
1528 n + 1, musb->config->num_eps * 2 - 1,
1529 offset, (1 << (musb->config->ram_bits + 2)));
1531 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1532 if (!musb->bulk_ep) {
1533 pr_debug("%s: missing bulk\n", musb_driver_name);
1543 * ep_config_from_hw - when MUSB_C_DYNFIFO_DEF is false
1544 * @param musb the controller
1546 static int __init ep_config_from_hw(struct musb *musb)
1549 struct musb_hw_ep *hw_ep;
1550 void *mbase = musb->mregs;
1553 DBG(2, "<== static silicon ep config\n");
1555 /* FIXME pick up ep0 maxpacket size */
1557 for (epnum = 1; epnum < musb->config->num_eps; epnum++) {
1558 musb_ep_select(mbase, epnum);
1559 hw_ep = musb->endpoints + epnum;
1561 ret = musb_read_fifosize(musb, hw_ep, epnum);
1565 /* FIXME set up hw_ep->{rx,tx}_double_buffered */
1567 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1568 /* pick an RX/TX endpoint for bulk */
1569 if (hw_ep->max_packet_sz_tx < 512
1570 || hw_ep->max_packet_sz_rx < 512)
1573 /* REVISIT: this algorithm is lazy, we should at least
1574 * try to pick a double buffered endpoint.
1578 musb->bulk_ep = hw_ep;
1582 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1583 if (!musb->bulk_ep) {
1584 pr_debug("%s: missing bulk\n", musb_driver_name);
1592 enum { MUSB_CONTROLLER_MHDRC, MUSB_CONTROLLER_HDRC, };
1594 /* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
1595 * configure endpoints, or take their config from silicon
1597 static int __init musb_core_init(u16 musb_type, struct musb *musb)
1604 u16 hwvers, rev_major, rev_minor;
1605 char aInfo[78], aRevision[32], aDate[12];
1606 void __iomem *mbase = musb->mregs;
1610 /* log core options (read using indexed model) */
1611 musb_ep_select(mbase, 0);
1612 reg = musb_read_configdata(mbase);
1614 strcpy(aInfo, (reg & MUSB_CONFIGDATA_UTMIDW) ? "UTMI-16" : "UTMI-8");
1615 if (reg & MUSB_CONFIGDATA_DYNFIFO)
1616 strcat(aInfo, ", dyn FIFOs");
1617 if (reg & MUSB_CONFIGDATA_MPRXE) {
1618 strcat(aInfo, ", bulk combine");
1620 musb->bulk_combine = true;
1622 strcat(aInfo, " (X)"); /* no driver support */
1625 if (reg & MUSB_CONFIGDATA_MPTXE) {
1626 strcat(aInfo, ", bulk split");
1628 musb->bulk_split = true;
1630 strcat(aInfo, " (X)"); /* no driver support */
1633 if (reg & MUSB_CONFIGDATA_HBRXE) {
1634 strcat(aInfo, ", HB-ISO Rx");
1635 strcat(aInfo, " (X)"); /* no driver support */
1637 if (reg & MUSB_CONFIGDATA_HBTXE) {
1638 strcat(aInfo, ", HB-ISO Tx");
1639 strcat(aInfo, " (X)"); /* no driver support */
1641 if (reg & MUSB_CONFIGDATA_SOFTCONE)
1642 strcat(aInfo, ", SoftConn");
1644 printk(KERN_DEBUG "%s: ConfigData=0x%02x (%s)\n",
1645 musb_driver_name, reg, aInfo);
1648 data = musb_readl(mbase, 0x404);
1649 sprintf(aDate, "%04d-%02x-%02x", (data & 0xffff),
1650 (data >> 16) & 0xff, (data >> 24) & 0xff);
1651 /* FIXME ID2 and ID3 are unused */
1652 data = musb_readl(mbase, 0x408);
1653 printk(KERN_DEBUG "ID2=%lx\n", (long unsigned)data);
1654 data = musb_readl(mbase, 0x40c);
1655 printk(KERN_DEBUG "ID3=%lx\n", (long unsigned)data);
1656 reg = musb_readb(mbase, 0x400);
1657 musb_type = ('M' == reg) ? MUSB_CONTROLLER_MHDRC : MUSB_CONTROLLER_HDRC;
1661 if (MUSB_CONTROLLER_MHDRC == musb_type) {
1662 musb->is_multipoint = 1;
1665 musb->is_multipoint = 0;
1667 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1668 #ifndef CONFIG_USB_OTG_BLACKLIST_HUB
1670 "%s: kernel must blacklist external hubs\n",
1676 /* log release info */
1677 hwvers = musb_read_hwvers(mbase);
1678 rev_major = (hwvers >> 10) & 0x1f;
1679 rev_minor = hwvers & 0x3ff;
1680 snprintf(aRevision, 32, "%d.%d%s", rev_major,
1681 rev_minor, (hwvers & 0x8000) ? "RC" : "");
1682 printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
1683 musb_driver_name, type, aRevision, aDate);
1686 musb_configure_ep0(musb);
1688 /* discover endpoint configuration */
1689 musb->nr_endpoints = 1;
1692 if (reg & MUSB_CONFIGDATA_DYNFIFO) {
1693 if (musb->config->dyn_fifo)
1694 status = ep_config_from_table(musb);
1696 ERR("reconfigure software for Dynamic FIFOs\n");
1700 if (!musb->config->dyn_fifo)
1701 status = ep_config_from_hw(musb);
1703 ERR("reconfigure software for static FIFOs\n");
1711 /* finish init, and print endpoint config */
1712 for (i = 0; i < musb->nr_endpoints; i++) {
1713 struct musb_hw_ep *hw_ep = musb->endpoints + i;
1715 hw_ep->fifo = MUSB_FIFO_OFFSET(i) + mbase;
1716 #ifdef CONFIG_USB_TUSB6010
1717 hw_ep->fifo_async = musb->async + 0x400 + MUSB_FIFO_OFFSET(i);
1718 hw_ep->fifo_sync = musb->sync + 0x400 + MUSB_FIFO_OFFSET(i);
1719 hw_ep->fifo_sync_va =
1720 musb->sync_va + 0x400 + MUSB_FIFO_OFFSET(i);
1723 hw_ep->conf = mbase - 0x400 + TUSB_EP0_CONF;
1725 hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
1728 hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
1729 #ifdef CONFIG_USB_MUSB_HDRC_HCD
1730 /* init list of in and out qhs */
1731 INIT_LIST_HEAD(&hw_ep->in_list);
1732 INIT_LIST_HEAD(&hw_ep->out_list);
1733 hw_ep->target_regs = musb_read_target_reg_base(i, mbase);
1734 hw_ep->rx_reinit = 1;
1735 hw_ep->tx_reinit = 1;
1738 if (hw_ep->max_packet_sz_tx) {
1740 "%s: hw_ep %d%s, %smax %d\n",
1741 musb_driver_name, i,
1742 hw_ep->is_shared_fifo ? "shared" : "tx",
1743 hw_ep->tx_double_buffered
1744 ? "doublebuffer, " : "",
1745 hw_ep->max_packet_sz_tx);
1747 if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
1749 "%s: hw_ep %d%s, %smax %d\n",
1750 musb_driver_name, i,
1752 hw_ep->rx_double_buffered
1753 ? "doublebuffer, " : "",
1754 hw_ep->max_packet_sz_rx);
1756 if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
1757 DBG(1, "hw_ep %d not configured\n", i);
1763 /*-------------------------------------------------------------------------*/
1765 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3430)
1767 static irqreturn_t generic_interrupt(int irq, void *__hci)
1769 unsigned long flags;
1770 irqreturn_t retval = IRQ_NONE;
1771 struct musb *musb = __hci;
1773 spin_lock_irqsave(&musb->lock, flags);
1775 musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
1776 musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
1777 musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
1779 while (musb->int_usb || musb->int_tx || musb->int_rx)
1780 retval |= musb_interrupt(musb);
1782 spin_unlock_irqrestore(&musb->lock, flags);
1784 /* REVISIT we sometimes get spurious IRQs on g_ep0
1787 if (retval != IRQ_HANDLED)
1788 DBG(5, "spurious?\n");
1794 #define generic_interrupt NULL
1798 * handle all the irqs defined by the HDRC core. for now we expect: other
1799 * irq sources (phy, dma, etc) will be handled first, musb->int_* values
1800 * will be assigned, and the irq will already have been acked.
1802 * called in irq context with spinlock held, irqs blocked
1804 irqreturn_t musb_interrupt(struct musb *musb)
1806 irqreturn_t retval = IRQ_NONE;
1807 u8 devctl, power, int_usb;
1811 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1812 power = musb_readb(musb->mregs, MUSB_POWER);
1814 DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n",
1815 (devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
1816 musb->int_usb, musb->int_tx, musb->int_rx);
1818 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
1819 if (is_otg_enabled(musb)|| is_peripheral_enabled(musb))
1820 if (!musb->gadget_driver) {
1821 DBG(5, "No gadget driver loaded\n");
1829 /* the core can interrupt us for multiple reasons; docs have
1830 * a generic interrupt flowchart to follow
1832 int_usb = musb->int_usb;
1834 int_usb &= ~MUSB_INTR_SOF;
1836 retval |= musb_stage0_irq(musb, int_usb, devctl, power);
1838 /* "stage 1" is handling endpoint irqs */
1840 /* handle endpoint 0 first */
1841 if (musb->int_tx & 1) {
1843 if (devctl & MUSB_DEVCTL_HM)
1844 retval |= musb_h_ep0_irq(musb);
1846 retval |= musb_g_ep0_irq(musb);
1849 /* TX on endpoints 1-15 */
1850 reg = musb->int_tx >> 1;
1855 /* musb_ep_select(musb->mregs, ep_num); */
1856 /* REVISIT just retval |= ep->tx_irq(...) */
1857 retval = IRQ_HANDLED;
1858 if (devctl & MUSB_DEVCTL_HM) {
1859 if (is_host_capable())
1860 musb_host_tx(musb, ep_num);
1862 if (is_peripheral_capable())
1863 musb_g_tx(musb, ep_num);
1870 /* RX on endpoints 1-15 */
1871 reg = musb->int_rx >> 1;
1876 /* musb_ep_select(musb->mregs, ep_num); */
1877 /* REVISIT just retval = ep->rx_irq(...) */
1878 retval = IRQ_HANDLED;
1879 if (devctl & MUSB_DEVCTL_HM) {
1880 if (is_host_capable())
1881 musb_host_rx(musb, ep_num);
1883 if (is_peripheral_capable())
1884 musb_g_rx(musb, ep_num, false);
1896 #ifndef CONFIG_MUSB_PIO_ONLY
1897 void musb_dma_completion(struct musb *musb, u8 epnum, u8 transmit)
1899 u8 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
1901 /* called with controller lock already held */
1904 #ifndef CONFIG_USB_TUSB_OMAP_DMA
1905 if (!cppi_ti_dma()) {
1907 if (devctl & MUSB_DEVCTL_HM)
1908 musb_h_ep0_irq(musb);
1910 musb_g_ep0_irq(musb);
1914 /* endpoints 1..15 */
1916 if (devctl & MUSB_DEVCTL_HM) {
1917 if (is_host_capable())
1918 musb_host_tx(musb, epnum);
1920 if (is_peripheral_capable())
1921 musb_g_tx(musb, epnum);
1925 if (devctl & MUSB_DEVCTL_HM) {
1926 if (is_host_capable())
1927 musb_host_rx(musb, epnum);
1929 if (is_peripheral_capable())
1930 musb_g_rx(musb, epnum, true);
1937 /*-------------------------------------------------------------------------*/
1942 musb_charger_show(struct device *dev, struct device_attribute *attr, char *buf)
1944 struct musb *musb = dev_to_musb(dev);
1946 return sprintf(buf, "%d\n", (musb->is_charger ?
1947 musb->is_charger : musb_charger_detect(musb)));
1949 static DEVICE_ATTR(charger, 0444, musb_charger_show, NULL);
1952 musb_amp_show(struct device *dev, struct device_attribute *attr, char *buf)
1954 struct musb *musb = dev_to_musb(dev);
1956 return sprintf(buf, "%d\n", musb->power_draw);
1958 static DEVICE_ATTR(mA, 0444, musb_amp_show, NULL);
1961 musb_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
1963 struct musb *musb = dev_to_musb(dev);
1966 mutex_lock(&musb->mutex);
1967 ret = sprintf(buf, "%s\n", otg_state_string(musb));
1968 mutex_unlock(&musb->mutex);
1974 musb_connect_show(struct device *dev, struct device_attribute *attr, char *buf)
1976 struct musb *musb = dev_to_musb(dev);
1977 unsigned long flags;
1980 spin_lock_irqsave(&musb->lock, flags);
1981 ret = sprintf(buf, "%d\n", musb->softconnect);
1982 spin_unlock_irqrestore(&musb->lock, flags);
1988 musb_connect_store(struct device *dev, struct device_attribute *attr,
1989 const char *buf, size_t n)
1991 struct musb *musb = dev_to_musb(dev);
1992 unsigned long flags;
1997 status = sscanf(buf, "%u", &val);
1999 printk(KERN_ERR "invalid parameter, %d\n", status);
2003 spin_lock_irqsave(&musb->lock, flags);
2005 power = musb_readb(musb->mregs, MUSB_POWER);
2008 power |= MUSB_POWER_SOFTCONN;
2010 power &= ~MUSB_POWER_SOFTCONN;
2012 musb->softconnect = !!val;
2013 musb_writeb(musb->mregs, MUSB_POWER, power);
2015 spin_unlock_irqrestore(&musb->lock, flags);
2019 static DEVICE_ATTR(connect, 0644, musb_connect_show, musb_connect_store);
2022 musb_mode_store(struct device *dev, struct device_attribute *attr,
2023 const char *buf, size_t n)
2025 struct musb *musb = dev_to_musb(dev);
2028 mutex_lock(&musb->mutex);
2029 if (sysfs_streq(buf, "host"))
2030 status = musb_platform_set_mode(musb, MUSB_HOST);
2031 else if (sysfs_streq(buf, "peripheral"))
2032 status = musb_platform_set_mode(musb, MUSB_PERIPHERAL);
2033 else if (sysfs_streq(buf, "otg"))
2034 status = musb_platform_set_mode(musb, MUSB_OTG);
2037 mutex_unlock(&musb->mutex);
2039 return (status == 0) ? n : status;
2041 static DEVICE_ATTR(mode, 0644, musb_mode_show, musb_mode_store);
2044 musb_vbus_store(struct device *dev, struct device_attribute *attr,
2045 const char *buf, size_t n)
2047 struct musb *musb = dev_to_musb(dev);
2048 unsigned long flags;
2051 if (sscanf(buf, "%lu", &val) < 1) {
2052 printk(KERN_ERR "Invalid VBUS timeout ms value\n");
2056 spin_lock_irqsave(&musb->lock, flags);
2057 musb->a_wait_bcon = val;
2058 if (musb->xceiv->state == OTG_STATE_A_WAIT_BCON)
2059 musb->is_active = 0;
2060 musb_platform_try_idle(musb, jiffies + msecs_to_jiffies(val));
2061 spin_unlock_irqrestore(&musb->lock, flags);
2067 musb_vbus_show(struct device *dev, struct device_attribute *attr, char *buf)
2069 struct musb *musb = dev_to_musb(dev);
2070 unsigned long flags;
2074 spin_lock_irqsave(&musb->lock, flags);
2075 val = musb->a_wait_bcon;
2076 vbus = musb_platform_get_vbus_status(musb);
2077 spin_unlock_irqrestore(&musb->lock, flags);
2079 return sprintf(buf, "Vbus %s, timeout %lu\n",
2080 vbus ? "on" : "off", val);
2082 static DEVICE_ATTR(vbus, 0644, musb_vbus_show, musb_vbus_store);
2084 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2087 musb_suspend_show(struct device *dev, struct device_attribute *attr, char *buf)
2089 struct musb *musb = dev_to_musb(dev);
2091 return sprintf(buf, "%d\n", musb->is_suspended);
2093 static DEVICE_ATTR(suspend, 0444, musb_suspend_show, NULL);
2095 /* Gadget drivers can't know that a host is connected so they might want
2096 * to start SRP, but users can. This allows userspace to trigger SRP.
2099 musb_srp_store(struct device *dev, struct device_attribute *attr,
2100 const char *buf, size_t n)
2102 struct musb *musb = dev_to_musb(dev);
2105 if (sscanf(buf, "%hu", &srp) != 1
2107 printk(KERN_ERR "SRP: Value must be 1\n");
2112 musb_g_wakeup(musb);
2116 static DEVICE_ATTR(srp, 0644, NULL, musb_srp_store);
2118 #endif /* CONFIG_USB_GADGET_MUSB_HDRC */
2122 /* Only used to provide driver mode change events */
2123 static void musb_irq_work(struct work_struct *data)
2125 struct musb *musb = container_of(data, struct musb, irq_work);
2126 static int old_state, old_ma, old_suspend;
2128 if (musb->xceiv->state != old_state) {
2129 old_state = musb->xceiv->state;
2130 sysfs_notify(&musb->controller->kobj, NULL, "mode");
2132 if (musb->power_draw != old_ma) {
2133 old_ma = musb->power_draw;
2134 sysfs_notify(&musb->controller->kobj, NULL, "mA");
2136 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2137 if (old_suspend != musb->is_suspended) {
2138 old_suspend = musb->is_suspended;
2139 sysfs_notify(&musb->controller->kobj, NULL, "suspend");
2144 /* --------------------------------------------------------------------------
2148 static struct musb *__init
2149 allocate_instance(struct device *dev,
2150 struct musb_hdrc_config *config, void __iomem *mbase)
2153 struct musb_hw_ep *ep;
2155 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2156 struct usb_hcd *hcd;
2158 hcd = usb_create_hcd(&musb_hc_driver, dev, dev_name(dev));
2161 /* usbcore sets dev->driver_data to hcd, and sometimes uses that... */
2163 musb = hcd_to_musb(hcd);
2165 hcd->uses_new_polling = 1;
2167 musb->vbuserr_retry = VBUSERR_RETRY_COUNT;
2169 musb = kzalloc(sizeof *musb, GFP_KERNEL);
2172 dev_set_drvdata(dev, musb);
2176 musb->mregs = mbase;
2177 musb->ctrl_base = mbase;
2178 musb->nIrq = -ENODEV;
2179 musb->config = config;
2180 BUG_ON(musb->config->num_eps > MUSB_C_NUM_EPS);
2181 for (epnum = 0, ep = musb->endpoints;
2182 epnum < musb->config->num_eps;
2188 musb->controller = dev;
2192 static void musb_free(struct musb *musb)
2194 /* this has multiple entry modes. it handles fault cleanup after
2195 * probe(), where things may be partially set up, as well as rmmod
2196 * cleanup after everything's been de-activated.
2200 device_remove_file(musb->controller, &dev_attr_mA);
2201 device_remove_file(musb->controller, &dev_attr_connect);
2202 device_remove_file(musb->controller, &dev_attr_charger);
2203 device_remove_file(musb->controller, &dev_attr_mode);
2204 device_remove_file(musb->controller, &dev_attr_vbus);
2205 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2206 device_remove_file(musb->controller, &dev_attr_suspend);
2207 device_remove_file(musb->controller, &dev_attr_srp);
2211 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2212 musb_gadget_cleanup(musb);
2215 if (musb->nIrq >= 0) {
2217 disable_irq_wake(musb->nIrq);
2218 free_irq(musb->nIrq, musb);
2220 if (is_dma_capable() && musb->dma_controller) {
2221 struct dma_controller *c = musb->dma_controller;
2224 dma_controller_destroy(c);
2227 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
2228 musb_platform_exit(musb);
2229 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
2232 clk_disable(musb->clock);
2233 clk_put(musb->clock);
2236 #ifdef CONFIG_USB_MUSB_OTG
2237 put_device(musb->xceiv->dev);
2240 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2241 usb_put_hcd(musb_to_hcd(musb));
2248 * Perform generic per-controller initialization.
2250 * @pDevice: the controller (already clocked, etc)
2252 * @mregs: virtual address of controller registers,
2253 * not yet corrected for platform-specific offsets
2256 musb_init_controller(struct device *dev, int nIrq, void __iomem *ctrl)
2260 struct musb_hdrc_platform_data *plat = dev->platform_data;
2262 /* The driver might handle more features than the board; OK.
2263 * Fail when the board needs a feature that's not enabled.
2266 dev_dbg(dev, "no platform_data?\n");
2269 switch (plat->mode) {
2271 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2276 case MUSB_PERIPHERAL:
2277 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2283 #ifdef CONFIG_USB_MUSB_OTG
2289 dev_err(dev, "incompatible Kconfig role setting\n");
2294 musb = allocate_instance(dev, plat->config, ctrl);
2300 spin_lock_init(&musb->lock);
2301 mutex_init(&musb->mutex);
2302 musb->board = plat->board;
2303 musb->board_mode = plat->mode;
2304 musb->board_set_power = plat->set_power;
2305 musb->set_clock = plat->set_clock;
2306 musb->min_power = plat->min_power;
2307 musb->use_dma = use_dma;
2309 /* Clock usage is chip-specific ... functional clock (DaVinci,
2310 * OMAP2430), or PHY ref (some TUSB6010 boards). All this core
2311 * code does is make sure a clock handle is available; platform
2312 * code manages it during start/stop and suspend/resume.
2315 musb->clock = clk_get(dev, plat->clock);
2316 if (IS_ERR(musb->clock)) {
2317 status = PTR_ERR(musb->clock);
2323 /* assume vbus is off */
2325 /* platform adjusts musb->mregs and musb->isr if needed,
2326 * and activates clocks
2328 musb->isr = generic_interrupt;
2329 status = musb_platform_init(musb);
2338 #ifndef CONFIG_MUSB_PIO_ONLY
2339 if (use_dma && dev->dma_mask) {
2340 struct dma_controller *c;
2342 c = dma_controller_create(musb, musb->mregs);
2343 musb->dma_controller = c;
2348 /* ideally this would be abstracted in platform setup */
2349 if (!musb->use_dma || !musb->dma_controller)
2350 dev->dma_mask = NULL;
2352 /* be sure interrupts are disabled before connecting ISR */
2353 musb_platform_disable(musb);
2354 musb_generic_disable(musb);
2356 /* setup musb parts of the core (especially endpoints) */
2357 status = musb_core_init(plat->config->multipoint
2358 ? MUSB_CONTROLLER_MHDRC
2359 : MUSB_CONTROLLER_HDRC, musb);
2363 /* Init IRQ workqueue before request_irq */
2364 INIT_WORK(&musb->irq_work, musb_irq_work);
2366 /* attach to the IRQ */
2367 if (request_irq(nIrq, musb->isr, 0, dev_name(dev), musb)) {
2368 dev_err(dev, "request_irq %d failed!\n", nIrq);
2373 /* FIXME this handles wakeup irqs wrong */
2374 if (enable_irq_wake(nIrq) == 0) {
2376 device_init_wakeup(dev, 1);
2381 pr_info("%s: USB %s mode controller at %p using %s, IRQ %d\n",
2384 switch (musb->board_mode) {
2385 case MUSB_HOST: s = "Host"; break;
2386 case MUSB_PERIPHERAL: s = "Peripheral"; break;
2387 default: s = "OTG"; break;
2390 (is_dma_capable() && musb->dma_controller)
2394 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2395 /* host side needs more setup, except for no-host modes */
2396 if (musb->board_mode != MUSB_PERIPHERAL) {
2397 struct usb_hcd *hcd = musb_to_hcd(musb);
2399 if (musb->board_mode == MUSB_OTG)
2400 hcd->self.otg_port = 1;
2401 musb->xceiv->host = &hcd->self;
2402 hcd->power_budget = 2 * (plat->power ? : 250);
2404 #endif /* CONFIG_USB_MUSB_HDRC_HCD */
2406 /* For the host-only role, we can activate right away.
2407 * (We expect the ID pin to be forcibly grounded!!)
2408 * Otherwise, wait till the gadget driver hooks up.
2410 if (!is_otg_enabled(musb) && is_host_enabled(musb)) {
2411 MUSB_HST_MODE(musb);
2412 musb->xceiv->default_a = 1;
2413 musb->xceiv->state = OTG_STATE_A_IDLE;
2415 status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
2419 DBG(1, "%s mode, status %d, devctl %02x %c\n",
2421 musb_readb(musb->mregs, MUSB_DEVCTL),
2422 (musb_readb(musb->mregs, MUSB_DEVCTL)
2423 & MUSB_DEVCTL_BDEVICE
2426 } else /* peripheral is enabled */ {
2427 MUSB_DEV_MODE(musb);
2428 musb->xceiv->default_a = 0;
2429 musb->xceiv->state = OTG_STATE_B_IDLE;
2431 status = musb_gadget_setup(musb);
2435 DBG(1, "%s mode, status %d, dev%02x\n",
2436 is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
2438 musb_readb(musb->mregs, MUSB_DEVCTL));
2442 if (!(musb_debug_create("driver/musb_hdrc", musb)))
2443 DBG(1, "could not create procfs entry\n");
2446 status = device_create_file(dev, &dev_attr_mA);
2447 status = device_create_file(dev, &dev_attr_connect);
2448 status = device_create_file(dev, &dev_attr_charger);
2449 status = device_create_file(dev, &dev_attr_mode);
2450 status = device_create_file(dev, &dev_attr_vbus);
2451 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2452 status = device_create_file(dev, &dev_attr_suspend);
2453 status = device_create_file(dev, &dev_attr_srp);
2454 #endif /* CONFIG_USB_GADGET_MUSB_HDRC */
2460 /* Resets the controller. Has to be done. Without this, most likely
2461 * the state machine inside the transceiver doesn't get fixed properly
2463 musb_save_ctx_and_suspend(&musb->g, 0);
2464 musb_restore_ctx_and_resume(&musb->g);
2470 device_remove_file(dev, &dev_attr_mA);
2471 device_remove_file(dev, &dev_attr_connect);
2472 device_remove_file(dev, &dev_attr_charger);
2473 device_remove_file(musb->controller, &dev_attr_mode);
2474 device_remove_file(musb->controller, &dev_attr_vbus);
2475 #ifdef CONFIG_USB_GADGET_MUSB_HDRC
2476 device_remove_file(musb->controller, &dev_attr_suspend);
2477 device_remove_file(musb->controller, &dev_attr_srp);
2480 musb_platform_exit(musb);
2482 dev_err(musb->controller,
2483 "musb_init_controller failed with status %d\n", status);
2486 clk_put(musb->clock);
2487 device_init_wakeup(dev, 0);
2494 /*-------------------------------------------------------------------------*/
2496 /* all implementations (PCI bridge to FPGA, VLYNQ, etc) should just
2497 * bridge to a platform device; this driver then suffices.
2500 #ifndef CONFIG_MUSB_PIO_ONLY
2501 static u64 *orig_dma_mask;
2504 static int __init musb_probe(struct platform_device *pdev)
2506 struct device *dev = &pdev->dev;
2507 int irq = platform_get_irq(pdev, 0);
2508 struct resource *iomem;
2511 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2512 if (!iomem || irq == 0)
2515 base = ioremap(iomem->start, iomem->end - iomem->start + 1);
2517 dev_err(dev, "ioremap failed\n");
2521 #ifndef CONFIG_MUSB_PIO_ONLY
2522 /* clobbered by use_dma=n */
2523 orig_dma_mask = dev->dma_mask;
2525 /* Store initial mask for USB interrupts */
2526 ctx.intrusbe = 0xf7;
2528 return musb_init_controller(dev, irq, base);
2531 static int __devexit musb_remove(struct platform_device *pdev)
2533 struct musb *musb = dev_to_musb(&pdev->dev);
2534 void __iomem *ctrl_base = musb->ctrl_base;
2536 /* this gets called on rmmod.
2537 * - Host mode: host may still be active
2538 * - Peripheral mode: peripheral is deactivated (or never-activated)
2539 * - OTG mode: both roles are deactivated (or never-activated)
2541 musb_shutdown(pdev);
2542 musb_debug_delete("driver/musb_hdrc", musb);
2543 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2544 if (musb->board_mode == MUSB_HOST)
2545 usb_remove_hcd(musb_to_hcd(musb));
2549 device_init_wakeup(&pdev->dev, 0);
2550 #ifndef CONFIG_MUSB_PIO_ONLY
2551 pdev->dev.dma_mask = orig_dma_mask;
2558 void musb_save_ctx(struct musb *musb)
2560 ctx.power = musb_readb(musb->mregs, MUSB_POWER);
2561 ctx.intrtxe = musb_readw(musb->mregs, MUSB_INTRTXE);
2562 ctx.intrrxe = musb_readw(musb->mregs, MUSB_INTRRXE);
2563 ctx.intrusbe = musb_readb(musb->mregs, MUSB_INTRUSBE);
2564 ctx.devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
2567 void musb_restore_ctx(struct musb *musb)
2570 musb_writeb(musb->mregs, MUSB_POWER, ctx.power);
2571 musb_writew(musb->mregs, MUSB_INTRTX, 0x00);
2572 musb_writew(musb->mregs, MUSB_INTRTXE, ctx.intrtxe);
2573 musb_writew(musb->mregs, MUSB_INTRRX, 0x00);
2574 musb_writew(musb->mregs, MUSB_INTRRXE, ctx.intrrxe);
2575 musb_writeb(musb->mregs, MUSB_INTRUSB, 0x00);
2576 musb_writeb(musb->mregs, MUSB_INTRUSBE, ctx.intrusbe);
2577 musb_writeb(musb->mregs, MUSB_DEVCTL, ctx.devctl);
2579 /* iterate over every endpoint, select it and restore its context */
2580 for (i = 0; i < musb->config->num_eps; i++) {
2581 musb_writeb(musb->mregs, MUSB_INDEX, i);
2582 musb_writeb(musb->mregs, MUSB_RXFIFOSZ, ctx.rxfifosz[i]);
2583 musb_writeb(musb->mregs, MUSB_TXFIFOSZ, ctx.txfifosz[i]);
2584 musb_writew(musb->mregs, MUSB_TXFIFOADD, ctx.txfifoadd[i]);
2585 musb_writew(musb->mregs, MUSB_RXFIFOADD, ctx.rxfifoadd[i]);
2589 static int musb_suspend(struct platform_device *pdev, pm_message_t message)
2591 unsigned long flags;
2592 struct musb *musb = dev_to_musb(&pdev->dev);
2597 spin_lock_irqsave(&musb->lock, flags);
2599 if (is_peripheral_active(musb)) {
2600 /* FIXME force disconnect unless we know USB will wake
2601 * the system up quickly enough to respond ...
2603 } else if (is_host_active(musb)) {
2604 /* we know all the children are suspended; sometimes
2605 * they will even be wakeup-enabled.
2610 musb_save_ctx(musb);
2612 if (musb->set_clock)
2613 musb->set_clock(musb->clock, 0);
2615 clk_disable(musb->clock);
2617 spin_unlock_irqrestore(&musb->lock, flags);
2621 static int musb_resume(struct platform_device *pdev)
2623 unsigned long flags;
2624 struct musb *musb = dev_to_musb(&pdev->dev);
2629 spin_lock_irqsave(&musb->lock, flags);
2631 if (musb->set_clock)
2632 musb->set_clock(musb->clock, 1);
2634 clk_enable(musb->clock);
2636 /* restore context */
2637 musb_restore_ctx(musb);
2639 /* for static cmos like DaVinci, register values were preserved
2640 * unless for some reason the whole soc powered down and we're
2641 * not treating that as a whole-system restart (e.g. swsusp)
2643 spin_unlock_irqrestore(&musb->lock, flags);
2648 #define musb_suspend NULL
2649 #define musb_resume NULL
2652 static struct platform_driver musb_driver = {
2654 .name = (char *)musb_driver_name,
2655 .bus = &platform_bus_type,
2656 .owner = THIS_MODULE,
2658 .remove = __devexit_p(musb_remove),
2659 .shutdown = musb_shutdown,
2660 .suspend = musb_suspend,
2661 .resume = musb_resume,
2664 /*-------------------------------------------------------------------------*/
2666 static int __init musb_init(void)
2668 #ifdef CONFIG_USB_MUSB_HDRC_HCD
2673 pr_info("%s: version " MUSB_VERSION ", "
2674 #ifdef CONFIG_MUSB_PIO_ONLY
2676 #elif defined(CONFIG_USB_TI_CPPI_DMA)
2678 #elif defined(CONFIG_USB_INVENTRA_DMA)
2680 #elif defined(CONFIG_USB_TUSB_OMAP_DMA)
2686 #ifdef CONFIG_USB_MUSB_OTG
2687 "otg (peripheral+host)"
2688 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
2690 #elif defined(CONFIG_USB_MUSB_HDRC_HCD)
2694 musb_driver_name, musb_debug);
2695 return platform_driver_probe(&musb_driver, musb_probe);
2698 /* make us init after usbcore and before usb
2699 * gadget and host-side drivers start to register
2701 subsys_initcall(musb_init);
2703 static void __exit musb_cleanup(void)
2705 platform_driver_unregister(&musb_driver);
2707 module_exit(musb_cleanup);