2 * i386 emulator main execution loop
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #if !defined(CONFIG_SOFTMMU)
35 #include <sys/ucontext.h>
38 int tb_invalidated_flag;
41 //#define DEBUG_SIGNAL
43 #if defined(TARGET_ARM) || defined(TARGET_SPARC)
44 /* XXX: unify with i386 target */
45 void cpu_loop_exit(void)
47 longjmp(env->jmp_env, 1);
54 /* exit the current TB from a signal handler. The host registers are
55 restored in a state compatible with the CPU emulator
57 void cpu_resume_from_signal(CPUState *env1, void *puc)
59 #if !defined(CONFIG_SOFTMMU)
60 struct ucontext *uc = puc;
65 /* XXX: restore cpu registers saved in host registers */
67 #if !defined(CONFIG_SOFTMMU)
69 /* XXX: use siglongjmp ? */
70 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
73 longjmp(env->jmp_env, 1);
77 static TranslationBlock *tb_find_slow(target_ulong pc,
81 TranslationBlock *tb, **ptb1;
84 target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
89 tb_invalidated_flag = 0;
91 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
93 /* find translated block using physical mappings */
94 phys_pc = get_phys_addr_code(env, pc);
95 phys_page1 = phys_pc & TARGET_PAGE_MASK;
97 h = tb_phys_hash_func(phys_pc);
98 ptb1 = &tb_phys_hash[h];
104 tb->page_addr[0] == phys_page1 &&
105 tb->cs_base == cs_base &&
106 tb->flags == flags) {
107 /* check next page if needed */
108 if (tb->page_addr[1] != -1) {
109 virt_page2 = (pc & TARGET_PAGE_MASK) +
111 phys_page2 = get_phys_addr_code(env, virt_page2);
112 if (tb->page_addr[1] == phys_page2)
118 ptb1 = &tb->phys_hash_next;
121 /* if no translated code available, then translate it now */
124 /* flush must be done */
126 /* cannot fail at this point */
128 /* don't forget to invalidate previous TB info */
131 tc_ptr = code_gen_ptr;
133 tb->cs_base = cs_base;
135 cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
136 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
138 /* check next page if needed */
139 virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
141 if ((pc & TARGET_PAGE_MASK) != virt_page2) {
142 phys_page2 = get_phys_addr_code(env, virt_page2);
144 tb_link_phys(tb, phys_pc, phys_page2);
147 if (tb_invalidated_flag) {
148 /* as some TB could have been invalidated because
149 of memory exceptions while generating the code, we
150 must recompute the hash index here */
153 /* we add the TB in the virtual pc hash table */
154 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
155 spin_unlock(&tb_lock);
159 static inline TranslationBlock *tb_find_fast(void)
161 TranslationBlock *tb;
162 target_ulong cs_base, pc;
165 /* we record a subset of the CPU state. It will
166 always be the same before a given translated block
168 #if defined(TARGET_I386)
170 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
171 cs_base = env->segs[R_CS].base;
172 pc = cs_base + env->eip;
173 #elif defined(TARGET_ARM)
174 flags = env->thumb | (env->vfp.vec_len << 1)
175 | (env->vfp.vec_stride << 4);
176 if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR)
180 #elif defined(TARGET_SPARC)
181 #ifdef TARGET_SPARC64
182 flags = (env->pstate << 2) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
184 flags = env->psrs | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1);
188 #elif defined(TARGET_PPC)
189 flags = (msr_pr << MSR_PR) | (msr_fp << MSR_FP) |
190 (msr_se << MSR_SE) | (msr_le << MSR_LE);
193 #elif defined(TARGET_MIPS)
194 flags = env->hflags & (MIPS_HFLAGS_TMASK | MIPS_HFLAG_BMASK);
198 #error unsupported CPU
200 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
201 if (__builtin_expect(!tb || tb->pc != pc || tb->cs_base != cs_base ||
202 tb->flags != flags, 0)) {
203 tb = tb_find_slow(pc, cs_base, flags);
209 /* main execution loop */
211 int cpu_exec(CPUState *env1)
213 int saved_T0, saved_T1;
218 #if defined(TARGET_I386)
243 #elif defined(TARGET_SPARC)
244 #if defined(reg_REGWPTR)
245 uint32_t *saved_regwptr;
249 int saved_i7, tmp_T0;
251 int ret, interrupt_request;
252 void (*gen_func)(void);
253 TranslationBlock *tb;
256 #if defined(TARGET_I386)
257 /* handle exit of HALTED state */
258 if (env1->hflags & HF_HALTED_MASK) {
259 /* disable halt condition */
260 if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
261 (env1->eflags & IF_MASK)) {
262 env1->hflags &= ~HF_HALTED_MASK;
267 #elif defined(TARGET_PPC)
269 if (env1->msr[MSR_EE] &&
270 (env1->interrupt_request &
271 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER))) {
277 #elif defined(TARGET_SPARC)
279 if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
280 (env1->psret != 0)) {
286 #elif defined(TARGET_ARM)
288 /* An interrupt wakes the CPU even if the I and F CPSR bits are
290 if (env1->interrupt_request
291 & (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD)) {
297 #elif defined(TARGET_MIPS)
299 if (env1->interrupt_request &
300 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) {
308 cpu_single_env = env1;
310 /* first we save global registers */
319 /* we also save i7 because longjmp may not restore it */
320 asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
323 #if defined(TARGET_I386)
350 /* put eflags in CPU temporary format */
351 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
352 DF = 1 - (2 * ((env->eflags >> 10) & 1));
353 CC_OP = CC_OP_EFLAGS;
354 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
355 #elif defined(TARGET_ARM)
356 #elif defined(TARGET_SPARC)
357 #if defined(reg_REGWPTR)
358 saved_regwptr = REGWPTR;
360 #elif defined(TARGET_PPC)
361 #elif defined(TARGET_MIPS)
363 #error unsupported target CPU
365 env->exception_index = -1;
367 /* prepare setjmp context for exception handling */
369 if (setjmp(env->jmp_env) == 0) {
370 env->current_tb = NULL;
371 /* if an exception is pending, we execute it here */
372 if (env->exception_index >= 0) {
373 if (env->exception_index >= EXCP_INTERRUPT) {
374 /* exit request from the cpu execution loop */
375 ret = env->exception_index;
377 } else if (env->user_mode_only) {
378 /* if user mode only, we simulate a fake exception
379 which will be hanlded outside the cpu execution
381 #if defined(TARGET_I386)
382 do_interrupt_user(env->exception_index,
383 env->exception_is_int,
385 env->exception_next_eip);
387 ret = env->exception_index;
390 #if defined(TARGET_I386)
391 /* simulate a real cpu exception. On i386, it can
392 trigger new exceptions, but we do not handle
393 double or triple faults yet. */
394 do_interrupt(env->exception_index,
395 env->exception_is_int,
397 env->exception_next_eip, 0);
398 #elif defined(TARGET_PPC)
400 #elif defined(TARGET_MIPS)
402 #elif defined(TARGET_SPARC)
403 do_interrupt(env->exception_index);
404 #elif defined(TARGET_ARM)
408 env->exception_index = -1;
411 if (kqemu_is_ok(env) && env->interrupt_request == 0) {
413 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
414 ret = kqemu_cpu_exec(env);
415 /* put eflags in CPU temporary format */
416 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
417 DF = 1 - (2 * ((env->eflags >> 10) & 1));
418 CC_OP = CC_OP_EFLAGS;
419 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
422 longjmp(env->jmp_env, 1);
423 } else if (ret == 2) {
424 /* softmmu execution needed */
426 if (env->interrupt_request != 0) {
427 /* hardware interrupt will be executed just after */
429 /* otherwise, we restart */
430 longjmp(env->jmp_env, 1);
436 T0 = 0; /* force lookup of first TB */
439 /* g1 can be modified by some libc? functions */
442 interrupt_request = env->interrupt_request;
443 if (__builtin_expect(interrupt_request, 0)) {
444 #if defined(TARGET_I386)
445 /* if hardware interrupt pending, we execute it */
446 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
447 (env->eflags & IF_MASK) &&
448 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
450 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
451 intno = cpu_get_pic_interrupt(env);
452 if (loglevel & CPU_LOG_TB_IN_ASM) {
453 fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
455 do_interrupt(intno, 0, 0, 0, 1);
456 /* ensure that no TB jump will be modified as
457 the program flow was changed */
464 #elif defined(TARGET_PPC)
466 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
471 if ((interrupt_request & CPU_INTERRUPT_HARD)) {
473 env->exception_index = EXCP_EXTERNAL;
476 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
482 } else if ((interrupt_request & CPU_INTERRUPT_TIMER)) {
484 env->exception_index = EXCP_DECR;
487 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
495 #elif defined(TARGET_MIPS)
496 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
497 (env->CP0_Status & (1 << CP0St_IE)) &&
498 (env->CP0_Status & env->CP0_Cause & 0x0000FF00) &&
499 !(env->hflags & MIPS_HFLAG_EXL) &&
500 !(env->hflags & MIPS_HFLAG_ERL) &&
501 !(env->hflags & MIPS_HFLAG_DM)) {
503 env->exception_index = EXCP_EXT_INTERRUPT;
506 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
513 #elif defined(TARGET_SPARC)
514 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
516 int pil = env->interrupt_index & 15;
517 int type = env->interrupt_index & 0xf0;
519 if (((type == TT_EXTINT) &&
520 (pil == 15 || pil > env->psrpil)) ||
522 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
523 do_interrupt(env->interrupt_index);
524 env->interrupt_index = 0;
531 } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
532 //do_interrupt(0, 0, 0, 0, 0);
533 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
534 } else if (interrupt_request & CPU_INTERRUPT_HALT) {
538 #elif defined(TARGET_ARM)
539 if (interrupt_request & CPU_INTERRUPT_FIQ
540 && !(env->uncached_cpsr & CPSR_F)) {
541 env->exception_index = EXCP_FIQ;
544 if (interrupt_request & CPU_INTERRUPT_HARD
545 && !(env->uncached_cpsr & CPSR_I)) {
546 env->exception_index = EXCP_IRQ;
550 if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
551 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
552 /* ensure that no TB jump will be modified as
553 the program flow was changed */
560 if (interrupt_request & CPU_INTERRUPT_EXIT) {
561 env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
562 env->exception_index = EXCP_INTERRUPT;
567 if ((loglevel & CPU_LOG_TB_CPU)) {
568 #if defined(TARGET_I386)
569 /* restore flags in standard format */
571 env->regs[R_EAX] = EAX;
574 env->regs[R_EBX] = EBX;
577 env->regs[R_ECX] = ECX;
580 env->regs[R_EDX] = EDX;
583 env->regs[R_ESI] = ESI;
586 env->regs[R_EDI] = EDI;
589 env->regs[R_EBP] = EBP;
592 env->regs[R_ESP] = ESP;
594 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
595 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
596 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
597 #elif defined(TARGET_ARM)
598 cpu_dump_state(env, logfile, fprintf, 0);
599 #elif defined(TARGET_SPARC)
600 REGWPTR = env->regbase + (env->cwp * 16);
601 env->regwptr = REGWPTR;
602 cpu_dump_state(env, logfile, fprintf, 0);
603 #elif defined(TARGET_PPC)
604 cpu_dump_state(env, logfile, fprintf, 0);
605 #elif defined(TARGET_MIPS)
606 cpu_dump_state(env, logfile, fprintf, 0);
608 #error unsupported target CPU
614 if ((loglevel & CPU_LOG_EXEC)) {
615 fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
616 (long)tb->tc_ptr, tb->pc,
617 lookup_symbol(tb->pc));
623 /* see if we can patch the calling TB. When the TB
624 spans two pages, we cannot safely do a direct
628 tb->page_addr[1] == -1
629 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
630 && (tb->cflags & CF_CODE_COPY) ==
631 (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
635 tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb);
636 #if defined(USE_CODE_COPY)
637 /* propagates the FP use info */
638 ((TranslationBlock *)(T0 & ~3))->cflags |=
639 (tb->cflags & CF_FP_USED);
641 spin_unlock(&tb_lock);
645 env->current_tb = tb;
646 /* execute the generated code */
647 gen_func = (void *)tc_ptr;
648 #if defined(__sparc__)
649 __asm__ __volatile__("call %0\n\t"
653 : "i0", "i1", "i2", "i3", "i4", "i5");
654 #elif defined(__arm__)
655 asm volatile ("mov pc, %0\n\t"
656 ".global exec_loop\n\t"
660 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
661 #elif defined(TARGET_I386) && defined(USE_CODE_COPY)
663 if (!(tb->cflags & CF_CODE_COPY)) {
664 if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
665 save_native_fp_state(env);
669 if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
670 restore_native_fp_state(env);
672 /* we work with native eflags */
673 CC_SRC = cc_table[CC_OP].compute_all();
674 CC_OP = CC_OP_EFLAGS;
675 asm(".globl exec_loop\n"
680 " fs movl %11, %%eax\n"
681 " andl $0x400, %%eax\n"
682 " fs orl %8, %%eax\n"
685 " fs movl %%esp, %12\n"
686 " fs movl %0, %%eax\n"
687 " fs movl %1, %%ecx\n"
688 " fs movl %2, %%edx\n"
689 " fs movl %3, %%ebx\n"
690 " fs movl %4, %%esp\n"
691 " fs movl %5, %%ebp\n"
692 " fs movl %6, %%esi\n"
693 " fs movl %7, %%edi\n"
696 " fs movl %%esp, %4\n"
697 " fs movl %12, %%esp\n"
698 " fs movl %%eax, %0\n"
699 " fs movl %%ecx, %1\n"
700 " fs movl %%edx, %2\n"
701 " fs movl %%ebx, %3\n"
702 " fs movl %%ebp, %5\n"
703 " fs movl %%esi, %6\n"
704 " fs movl %%edi, %7\n"
707 " movl %%eax, %%ecx\n"
708 " andl $0x400, %%ecx\n"
710 " andl $0x8d5, %%eax\n"
711 " fs movl %%eax, %8\n"
713 " subl %%ecx, %%eax\n"
714 " fs movl %%eax, %11\n"
715 " fs movl %9, %%ebx\n" /* get T0 value */
718 : "m" (*(uint8_t *)offsetof(CPUState, regs[0])),
719 "m" (*(uint8_t *)offsetof(CPUState, regs[1])),
720 "m" (*(uint8_t *)offsetof(CPUState, regs[2])),
721 "m" (*(uint8_t *)offsetof(CPUState, regs[3])),
722 "m" (*(uint8_t *)offsetof(CPUState, regs[4])),
723 "m" (*(uint8_t *)offsetof(CPUState, regs[5])),
724 "m" (*(uint8_t *)offsetof(CPUState, regs[6])),
725 "m" (*(uint8_t *)offsetof(CPUState, regs[7])),
726 "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
727 "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
729 "m" (*(uint8_t *)offsetof(CPUState, df)),
730 "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
735 #elif defined(__ia64)
742 fp.gp = code_gen_buffer + 2 * (1 << 20);
743 (*(void (*)(void)) &fp)();
747 env->current_tb = NULL;
748 /* reset soft MMU for next block (it can currently
749 only be set by a memory fault) */
750 #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
751 if (env->hflags & HF_SOFTMMU_MASK) {
752 env->hflags &= ~HF_SOFTMMU_MASK;
753 /* do not allow linking to another block */
764 #if defined(TARGET_I386)
765 #if defined(USE_CODE_COPY)
766 if (env->native_fp_regs) {
767 save_native_fp_state(env);
770 /* restore flags in standard format */
771 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
773 /* restore global registers */
798 #elif defined(TARGET_ARM)
799 /* XXX: Save/restore host fpu exception state?. */
800 #elif defined(TARGET_SPARC)
801 #if defined(reg_REGWPTR)
802 REGWPTR = saved_regwptr;
804 #elif defined(TARGET_PPC)
805 #elif defined(TARGET_MIPS)
807 #error unsupported target CPU
810 asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
818 /* fail safe : never use cpu_single_env outside cpu_exec() */
819 cpu_single_env = NULL;
823 /* must only be called from the generated code as an exception can be
825 void tb_invalidate_page_range(target_ulong start, target_ulong end)
827 /* XXX: cannot enable it yet because it yields to MMU exception
828 where NIP != read address on PowerPC */
830 target_ulong phys_addr;
831 phys_addr = get_phys_addr_code(env, start);
832 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
836 #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
838 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
840 CPUX86State *saved_env;
844 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
846 cpu_x86_load_seg_cache(env, seg_reg, selector,
847 (selector << 4), 0xffff, 0);
849 load_seg(seg_reg, selector);
854 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
856 CPUX86State *saved_env;
861 helper_fsave((target_ulong)ptr, data32);
866 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
868 CPUX86State *saved_env;
873 helper_frstor((target_ulong)ptr, data32);
878 #endif /* TARGET_I386 */
880 #if !defined(CONFIG_SOFTMMU)
882 #if defined(TARGET_I386)
884 /* 'pc' is the host PC at which the exception was raised. 'address' is
885 the effective address of the memory exception. 'is_write' is 1 if a
886 write caused the exception and otherwise 0'. 'old_set' is the
887 signal set which should be restored */
888 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
889 int is_write, sigset_t *old_set,
892 TranslationBlock *tb;
896 env = cpu_single_env; /* XXX: find a correct solution for multithread */
897 #if defined(DEBUG_SIGNAL)
898 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
899 pc, address, is_write, *(unsigned long *)old_set);
901 /* XXX: locking issue */
902 if (is_write && page_unprotect(address, pc, puc)) {
906 /* see if it is an MMU fault */
907 ret = cpu_x86_handle_mmu_fault(env, address, is_write,
908 ((env->hflags & HF_CPL_MASK) == 3), 0);
910 return 0; /* not an MMU fault */
912 return 1; /* the MMU fault was handled without causing real CPU fault */
913 /* now we have a real cpu fault */
916 /* the PC is inside the translated code. It means that we have
917 a virtual CPU fault */
918 cpu_restore_state(tb, env, pc, puc);
922 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
923 env->eip, env->cr[2], env->error_code);
925 /* we restore the process signal mask as the sigreturn should
926 do it (XXX: use sigsetjmp) */
927 sigprocmask(SIG_SETMASK, old_set, NULL);
928 raise_exception_err(env->exception_index, env->error_code);
930 /* activate soft MMU for this block */
931 env->hflags |= HF_SOFTMMU_MASK;
932 cpu_resume_from_signal(env, puc);
934 /* never comes here */
938 #elif defined(TARGET_ARM)
939 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
940 int is_write, sigset_t *old_set,
943 TranslationBlock *tb;
947 env = cpu_single_env; /* XXX: find a correct solution for multithread */
948 #if defined(DEBUG_SIGNAL)
949 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
950 pc, address, is_write, *(unsigned long *)old_set);
952 /* XXX: locking issue */
953 if (is_write && page_unprotect(address, pc, puc)) {
956 /* see if it is an MMU fault */
957 ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0);
959 return 0; /* not an MMU fault */
961 return 1; /* the MMU fault was handled without causing real CPU fault */
962 /* now we have a real cpu fault */
965 /* the PC is inside the translated code. It means that we have
966 a virtual CPU fault */
967 cpu_restore_state(tb, env, pc, puc);
969 /* we restore the process signal mask as the sigreturn should
970 do it (XXX: use sigsetjmp) */
971 sigprocmask(SIG_SETMASK, old_set, NULL);
974 #elif defined(TARGET_SPARC)
975 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
976 int is_write, sigset_t *old_set,
979 TranslationBlock *tb;
983 env = cpu_single_env; /* XXX: find a correct solution for multithread */
984 #if defined(DEBUG_SIGNAL)
985 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
986 pc, address, is_write, *(unsigned long *)old_set);
988 /* XXX: locking issue */
989 if (is_write && page_unprotect(address, pc, puc)) {
992 /* see if it is an MMU fault */
993 ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0);
995 return 0; /* not an MMU fault */
997 return 1; /* the MMU fault was handled without causing real CPU fault */
998 /* now we have a real cpu fault */
1001 /* the PC is inside the translated code. It means that we have
1002 a virtual CPU fault */
1003 cpu_restore_state(tb, env, pc, puc);
1005 /* we restore the process signal mask as the sigreturn should
1006 do it (XXX: use sigsetjmp) */
1007 sigprocmask(SIG_SETMASK, old_set, NULL);
1010 #elif defined (TARGET_PPC)
1011 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1012 int is_write, sigset_t *old_set,
1015 TranslationBlock *tb;
1019 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1020 #if defined(DEBUG_SIGNAL)
1021 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1022 pc, address, is_write, *(unsigned long *)old_set);
1024 /* XXX: locking issue */
1025 if (is_write && page_unprotect(address, pc, puc)) {
1029 /* see if it is an MMU fault */
1030 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
1032 return 0; /* not an MMU fault */
1034 return 1; /* the MMU fault was handled without causing real CPU fault */
1036 /* now we have a real cpu fault */
1037 tb = tb_find_pc(pc);
1039 /* the PC is inside the translated code. It means that we have
1040 a virtual CPU fault */
1041 cpu_restore_state(tb, env, pc, puc);
1045 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1046 env->nip, env->error_code, tb);
1048 /* we restore the process signal mask as the sigreturn should
1049 do it (XXX: use sigsetjmp) */
1050 sigprocmask(SIG_SETMASK, old_set, NULL);
1051 do_raise_exception_err(env->exception_index, env->error_code);
1053 /* activate soft MMU for this block */
1054 cpu_resume_from_signal(env, puc);
1056 /* never comes here */
1060 #elif defined (TARGET_MIPS)
1061 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1062 int is_write, sigset_t *old_set,
1065 TranslationBlock *tb;
1069 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1070 #if defined(DEBUG_SIGNAL)
1071 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1072 pc, address, is_write, *(unsigned long *)old_set);
1074 /* XXX: locking issue */
1075 if (is_write && page_unprotect(address, pc, puc)) {
1079 /* see if it is an MMU fault */
1080 ret = cpu_mips_handle_mmu_fault(env, address, is_write, 1, 0);
1082 return 0; /* not an MMU fault */
1084 return 1; /* the MMU fault was handled without causing real CPU fault */
1086 /* now we have a real cpu fault */
1087 tb = tb_find_pc(pc);
1089 /* the PC is inside the translated code. It means that we have
1090 a virtual CPU fault */
1091 cpu_restore_state(tb, env, pc, puc);
1095 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1096 env->nip, env->error_code, tb);
1098 /* we restore the process signal mask as the sigreturn should
1099 do it (XXX: use sigsetjmp) */
1100 sigprocmask(SIG_SETMASK, old_set, NULL);
1101 do_raise_exception_err(env->exception_index, env->error_code);
1103 /* activate soft MMU for this block */
1104 cpu_resume_from_signal(env, puc);
1106 /* never comes here */
1111 #error unsupported target CPU
1114 #if defined(__i386__)
1116 #if defined(USE_CODE_COPY)
1117 static void cpu_send_trap(unsigned long pc, int trap,
1118 struct ucontext *uc)
1120 TranslationBlock *tb;
1123 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1124 /* now we have a real cpu fault */
1125 tb = tb_find_pc(pc);
1127 /* the PC is inside the translated code. It means that we have
1128 a virtual CPU fault */
1129 cpu_restore_state(tb, env, pc, uc);
1131 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
1132 raise_exception_err(trap, env->error_code);
1136 int cpu_signal_handler(int host_signum, struct siginfo *info,
1139 struct ucontext *uc = puc;
1147 #define REG_TRAPNO TRAPNO
1149 pc = uc->uc_mcontext.gregs[REG_EIP];
1150 trapno = uc->uc_mcontext.gregs[REG_TRAPNO];
1151 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
1152 if (trapno == 0x00 || trapno == 0x05) {
1153 /* send division by zero or bound exception */
1154 cpu_send_trap(pc, trapno, uc);
1158 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1160 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1161 &uc->uc_sigmask, puc);
1164 #elif defined(__x86_64__)
1166 int cpu_signal_handler(int host_signum, struct siginfo *info,
1169 struct ucontext *uc = puc;
1172 pc = uc->uc_mcontext.gregs[REG_RIP];
1173 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1174 uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
1175 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1176 &uc->uc_sigmask, puc);
1179 #elif defined(__powerpc__)
1181 /***********************************************************************
1182 * signal context platform-specific definitions
1186 /* All Registers access - only for local access */
1187 # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
1188 /* Gpr Registers access */
1189 # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
1190 # define IAR_sig(context) REG_sig(nip, context) /* Program counter */
1191 # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
1192 # define CTR_sig(context) REG_sig(ctr, context) /* Count register */
1193 # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
1194 # define LR_sig(context) REG_sig(link, context) /* Link register */
1195 # define CR_sig(context) REG_sig(ccr, context) /* Condition register */
1196 /* Float Registers access */
1197 # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
1198 # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
1199 /* Exception Registers access */
1200 # define DAR_sig(context) REG_sig(dar, context)
1201 # define DSISR_sig(context) REG_sig(dsisr, context)
1202 # define TRAP_sig(context) REG_sig(trap, context)
1206 # include <sys/ucontext.h>
1207 typedef struct ucontext SIGCONTEXT;
1208 /* All Registers access - only for local access */
1209 # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
1210 # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
1211 # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
1212 # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
1213 /* Gpr Registers access */
1214 # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
1215 # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
1216 # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
1217 # define CTR_sig(context) REG_sig(ctr, context)
1218 # define XER_sig(context) REG_sig(xer, context) /* Link register */
1219 # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
1220 # define CR_sig(context) REG_sig(cr, context) /* Condition register */
1221 /* Float Registers access */
1222 # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
1223 # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
1224 /* Exception Registers access */
1225 # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
1226 # define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
1227 # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1228 #endif /* __APPLE__ */
1230 int cpu_signal_handler(int host_signum, struct siginfo *info,
1233 struct ucontext *uc = puc;
1241 if (DSISR_sig(uc) & 0x00800000)
1244 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
1247 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1248 is_write, &uc->uc_sigmask, puc);
1251 #elif defined(__alpha__)
1253 int cpu_signal_handler(int host_signum, struct siginfo *info,
1256 struct ucontext *uc = puc;
1257 uint32_t *pc = uc->uc_mcontext.sc_pc;
1258 uint32_t insn = *pc;
1261 /* XXX: need kernel patch to get write flag faster */
1262 switch (insn >> 26) {
1277 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1278 is_write, &uc->uc_sigmask, puc);
1280 #elif defined(__sparc__)
1282 int cpu_signal_handler(int host_signum, struct siginfo *info,
1285 uint32_t *regs = (uint32_t *)(info + 1);
1286 void *sigmask = (regs + 20);
1291 /* XXX: is there a standard glibc define ? */
1293 /* XXX: need kernel patch to get write flag faster */
1295 insn = *(uint32_t *)pc;
1296 if ((insn >> 30) == 3) {
1297 switch((insn >> 19) & 0x3f) {
1309 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1310 is_write, sigmask, NULL);
1313 #elif defined(__arm__)
1315 int cpu_signal_handler(int host_signum, struct siginfo *info,
1318 struct ucontext *uc = puc;
1322 pc = uc->uc_mcontext.gregs[R15];
1323 /* XXX: compute is_write */
1325 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1330 #elif defined(__mc68000)
1332 int cpu_signal_handler(int host_signum, struct siginfo *info,
1335 struct ucontext *uc = puc;
1339 pc = uc->uc_mcontext.gregs[16];
1340 /* XXX: compute is_write */
1342 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1344 &uc->uc_sigmask, puc);
1347 #elif defined(__ia64)
1350 /* This ought to be in <bits/siginfo.h>... */
1351 # define __ISR_VALID 1
1352 # define si_flags _sifields._sigfault._si_pad0
1355 int cpu_signal_handler(int host_signum, struct siginfo *info, void *puc)
1357 struct ucontext *uc = puc;
1361 ip = uc->uc_mcontext.sc_ip;
1362 switch (host_signum) {
1368 if (info->si_code && (info->si_flags & __ISR_VALID))
1369 /* ISR.W (write-access) is bit 33: */
1370 is_write = (info->si_isr >> 33) & 1;
1376 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1378 &uc->uc_sigmask, puc);
1381 #elif defined(__s390__)
1383 int cpu_signal_handler(int host_signum, struct siginfo *info,
1386 struct ucontext *uc = puc;
1390 pc = uc->uc_mcontext.psw.addr;
1391 /* XXX: compute is_write */
1393 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1395 &uc->uc_sigmask, puc);
1400 #error host CPU specific signal handler needed
1404 #endif /* !defined(CONFIG_SOFTMMU) */