2 * i386 emulator main execution loop
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #if !defined(CONFIG_SOFTMMU)
35 #include <sys/ucontext.h>
38 int tb_invalidated_flag;
41 //#define DEBUG_SIGNAL
43 #if defined(TARGET_ARM) || defined(TARGET_SPARC)
44 /* XXX: unify with i386 target */
45 void cpu_loop_exit(void)
47 longjmp(env->jmp_env, 1);
50 #if !(defined(TARGET_SPARC) || defined(TARGET_SH4))
54 /* exit the current TB from a signal handler. The host registers are
55 restored in a state compatible with the CPU emulator
57 void cpu_resume_from_signal(CPUState *env1, void *puc)
59 #if !defined(CONFIG_SOFTMMU)
60 struct ucontext *uc = puc;
65 /* XXX: restore cpu registers saved in host registers */
67 #if !defined(CONFIG_SOFTMMU)
69 /* XXX: use siglongjmp ? */
70 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
73 longjmp(env->jmp_env, 1);
77 static TranslationBlock *tb_find_slow(target_ulong pc,
81 TranslationBlock *tb, **ptb1;
84 target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
89 tb_invalidated_flag = 0;
91 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
93 /* find translated block using physical mappings */
94 phys_pc = get_phys_addr_code(env, pc);
95 phys_page1 = phys_pc & TARGET_PAGE_MASK;
97 h = tb_phys_hash_func(phys_pc);
98 ptb1 = &tb_phys_hash[h];
104 tb->page_addr[0] == phys_page1 &&
105 tb->cs_base == cs_base &&
106 tb->flags == flags) {
107 /* check next page if needed */
108 if (tb->page_addr[1] != -1) {
109 virt_page2 = (pc & TARGET_PAGE_MASK) +
111 phys_page2 = get_phys_addr_code(env, virt_page2);
112 if (tb->page_addr[1] == phys_page2)
118 ptb1 = &tb->phys_hash_next;
121 /* if no translated code available, then translate it now */
124 /* flush must be done */
126 /* cannot fail at this point */
128 /* don't forget to invalidate previous TB info */
129 tb_invalidated_flag = 1;
131 tc_ptr = code_gen_ptr;
133 tb->cs_base = cs_base;
135 cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
136 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
138 /* check next page if needed */
139 virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
141 if ((pc & TARGET_PAGE_MASK) != virt_page2) {
142 phys_page2 = get_phys_addr_code(env, virt_page2);
144 tb_link_phys(tb, phys_pc, phys_page2);
147 /* we add the TB in the virtual pc hash table */
148 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
149 spin_unlock(&tb_lock);
153 static inline TranslationBlock *tb_find_fast(void)
155 TranslationBlock *tb;
156 target_ulong cs_base, pc;
159 /* we record a subset of the CPU state. It will
160 always be the same before a given translated block
162 #if defined(TARGET_I386)
164 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
165 cs_base = env->segs[R_CS].base;
166 pc = cs_base + env->eip;
167 #elif defined(TARGET_ARM)
168 flags = env->thumb | (env->vfp.vec_len << 1)
169 | (env->vfp.vec_stride << 4);
170 if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR)
172 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30))
176 #elif defined(TARGET_SPARC)
177 #ifdef TARGET_SPARC64
178 // Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
179 flags = (((env->pstate & PS_PEF) >> 1) | ((env->fprs & FPRS_FEF) << 2))
180 | (env->pstate & PS_PRIV) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
182 // FPU enable . MMU enabled . MMU no-fault . Supervisor
183 flags = (env->psref << 3) | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1)
188 #elif defined(TARGET_PPC)
189 flags = (msr_pr << MSR_PR) | (msr_fp << MSR_FP) |
190 (msr_se << MSR_SE) | (msr_le << MSR_LE);
193 #elif defined(TARGET_MIPS)
194 flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
197 #elif defined(TARGET_SH4)
198 flags = env->sr & (SR_MD | SR_RB);
199 cs_base = 0; /* XXXXX */
202 #error unsupported CPU
204 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
205 if (__builtin_expect(!tb || tb->pc != pc || tb->cs_base != cs_base ||
206 tb->flags != flags, 0)) {
207 tb = tb_find_slow(pc, cs_base, flags);
208 /* Note: we do it here to avoid a gcc bug on Mac OS X when
209 doing it in tb_find_slow */
210 if (tb_invalidated_flag) {
211 /* as some TB could have been invalidated because
212 of memory exceptions while generating the code, we
213 must recompute the hash index here */
221 /* main execution loop */
223 int cpu_exec(CPUState *env1)
225 int saved_T0, saved_T1;
230 #if defined(TARGET_I386)
255 #elif defined(TARGET_SPARC)
256 #if defined(reg_REGWPTR)
257 uint32_t *saved_regwptr;
260 #if defined(__sparc__) && !defined(HOST_SOLARIS)
261 int saved_i7, tmp_T0;
263 int ret, interrupt_request;
264 void (*gen_func)(void);
265 TranslationBlock *tb;
268 #if defined(TARGET_I386)
269 /* handle exit of HALTED state */
270 if (env1->hflags & HF_HALTED_MASK) {
271 /* disable halt condition */
272 if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
273 (env1->eflags & IF_MASK)) {
274 env1->hflags &= ~HF_HALTED_MASK;
279 #elif defined(TARGET_PPC)
281 if (env1->msr[MSR_EE] &&
282 (env1->interrupt_request &
283 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER))) {
289 #elif defined(TARGET_SPARC)
291 if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
292 (env1->psret != 0)) {
298 #elif defined(TARGET_ARM)
300 /* An interrupt wakes the CPU even if the I and F CPSR bits are
302 if (env1->interrupt_request
303 & (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD)) {
309 #elif defined(TARGET_MIPS)
311 if (env1->interrupt_request &
312 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) {
320 cpu_single_env = env1;
322 /* first we save global registers */
330 #if defined(__sparc__) && !defined(HOST_SOLARIS)
331 /* we also save i7 because longjmp may not restore it */
332 asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
335 #if defined(TARGET_I386)
362 /* put eflags in CPU temporary format */
363 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
364 DF = 1 - (2 * ((env->eflags >> 10) & 1));
365 CC_OP = CC_OP_EFLAGS;
366 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
367 #elif defined(TARGET_ARM)
368 #elif defined(TARGET_SPARC)
369 #if defined(reg_REGWPTR)
370 saved_regwptr = REGWPTR;
372 #elif defined(TARGET_PPC)
373 #elif defined(TARGET_MIPS)
374 #elif defined(TARGET_SH4)
377 #error unsupported target CPU
379 env->exception_index = -1;
381 /* prepare setjmp context for exception handling */
383 if (setjmp(env->jmp_env) == 0) {
384 env->current_tb = NULL;
385 /* if an exception is pending, we execute it here */
386 if (env->exception_index >= 0) {
387 if (env->exception_index >= EXCP_INTERRUPT) {
388 /* exit request from the cpu execution loop */
389 ret = env->exception_index;
391 } else if (env->user_mode_only) {
392 /* if user mode only, we simulate a fake exception
393 which will be hanlded outside the cpu execution
395 #if defined(TARGET_I386)
396 do_interrupt_user(env->exception_index,
397 env->exception_is_int,
399 env->exception_next_eip);
401 ret = env->exception_index;
404 #if defined(TARGET_I386)
405 /* simulate a real cpu exception. On i386, it can
406 trigger new exceptions, but we do not handle
407 double or triple faults yet. */
408 do_interrupt(env->exception_index,
409 env->exception_is_int,
411 env->exception_next_eip, 0);
412 #elif defined(TARGET_PPC)
414 #elif defined(TARGET_MIPS)
416 #elif defined(TARGET_SPARC)
417 do_interrupt(env->exception_index);
418 #elif defined(TARGET_ARM)
420 #elif defined(TARGET_SH4)
424 env->exception_index = -1;
427 if (kqemu_is_ok(env) && env->interrupt_request == 0) {
429 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
430 ret = kqemu_cpu_exec(env);
431 /* put eflags in CPU temporary format */
432 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
433 DF = 1 - (2 * ((env->eflags >> 10) & 1));
434 CC_OP = CC_OP_EFLAGS;
435 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
438 longjmp(env->jmp_env, 1);
439 } else if (ret == 2) {
440 /* softmmu execution needed */
442 if (env->interrupt_request != 0) {
443 /* hardware interrupt will be executed just after */
445 /* otherwise, we restart */
446 longjmp(env->jmp_env, 1);
452 T0 = 0; /* force lookup of first TB */
454 #if defined(__sparc__) && !defined(HOST_SOLARIS)
455 /* g1 can be modified by some libc? functions */
458 interrupt_request = env->interrupt_request;
459 if (__builtin_expect(interrupt_request, 0)) {
460 #if defined(TARGET_I386)
461 /* if hardware interrupt pending, we execute it */
462 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
463 (env->eflags & IF_MASK) &&
464 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
466 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
467 intno = cpu_get_pic_interrupt(env);
468 if (loglevel & CPU_LOG_TB_IN_ASM) {
469 fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
471 do_interrupt(intno, 0, 0, 0, 1);
472 /* ensure that no TB jump will be modified as
473 the program flow was changed */
474 #if defined(__sparc__) && !defined(HOST_SOLARIS)
480 #elif defined(TARGET_PPC)
482 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
487 if ((interrupt_request & CPU_INTERRUPT_HARD)) {
489 env->exception_index = EXCP_EXTERNAL;
492 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
493 #if defined(__sparc__) && !defined(HOST_SOLARIS)
498 } else if ((interrupt_request & CPU_INTERRUPT_TIMER)) {
500 env->exception_index = EXCP_DECR;
503 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
504 #if defined(__sparc__) && !defined(HOST_SOLARIS)
511 #elif defined(TARGET_MIPS)
512 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
513 (env->CP0_Status & (1 << CP0St_IE)) &&
514 (env->CP0_Status & env->CP0_Cause & 0x0000FF00) &&
515 !(env->hflags & MIPS_HFLAG_EXL) &&
516 !(env->hflags & MIPS_HFLAG_ERL) &&
517 !(env->hflags & MIPS_HFLAG_DM)) {
519 env->exception_index = EXCP_EXT_INTERRUPT;
522 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
523 #if defined(__sparc__) && !defined(HOST_SOLARIS)
529 #elif defined(TARGET_SPARC)
530 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
532 int pil = env->interrupt_index & 15;
533 int type = env->interrupt_index & 0xf0;
535 if (((type == TT_EXTINT) &&
536 (pil == 15 || pil > env->psrpil)) ||
538 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
539 do_interrupt(env->interrupt_index);
540 env->interrupt_index = 0;
541 #if defined(__sparc__) && !defined(HOST_SOLARIS)
547 } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
548 //do_interrupt(0, 0, 0, 0, 0);
549 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
550 } else if (interrupt_request & CPU_INTERRUPT_HALT) {
554 #elif defined(TARGET_ARM)
555 if (interrupt_request & CPU_INTERRUPT_FIQ
556 && !(env->uncached_cpsr & CPSR_F)) {
557 env->exception_index = EXCP_FIQ;
560 if (interrupt_request & CPU_INTERRUPT_HARD
561 && !(env->uncached_cpsr & CPSR_I)) {
562 env->exception_index = EXCP_IRQ;
565 #elif defined(TARGET_SH4)
568 /* Don't use the cached interupt_request value,
569 do_interrupt may have updated the EXITTB flag. */
570 if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
571 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
572 /* ensure that no TB jump will be modified as
573 the program flow was changed */
574 #if defined(__sparc__) && !defined(HOST_SOLARIS)
580 if (interrupt_request & CPU_INTERRUPT_EXIT) {
581 env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
582 env->exception_index = EXCP_INTERRUPT;
587 if ((loglevel & CPU_LOG_TB_CPU)) {
588 #if defined(TARGET_I386)
589 /* restore flags in standard format */
591 env->regs[R_EAX] = EAX;
594 env->regs[R_EBX] = EBX;
597 env->regs[R_ECX] = ECX;
600 env->regs[R_EDX] = EDX;
603 env->regs[R_ESI] = ESI;
606 env->regs[R_EDI] = EDI;
609 env->regs[R_EBP] = EBP;
612 env->regs[R_ESP] = ESP;
614 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
615 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
616 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
617 #elif defined(TARGET_ARM)
618 cpu_dump_state(env, logfile, fprintf, 0);
619 #elif defined(TARGET_SPARC)
620 REGWPTR = env->regbase + (env->cwp * 16);
621 env->regwptr = REGWPTR;
622 cpu_dump_state(env, logfile, fprintf, 0);
623 #elif defined(TARGET_PPC)
624 cpu_dump_state(env, logfile, fprintf, 0);
625 #elif defined(TARGET_MIPS)
626 cpu_dump_state(env, logfile, fprintf, 0);
627 #elif defined(TARGET_SH4)
628 cpu_dump_state(env, logfile, fprintf, 0);
630 #error unsupported target CPU
636 if ((loglevel & CPU_LOG_EXEC)) {
637 fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
638 (long)tb->tc_ptr, tb->pc,
639 lookup_symbol(tb->pc));
642 #if defined(__sparc__) && !defined(HOST_SOLARIS)
645 /* see if we can patch the calling TB. When the TB
646 spans two pages, we cannot safely do a direct
651 (env->kqemu_enabled != 2) &&
653 tb->page_addr[1] == -1
654 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
655 && (tb->cflags & CF_CODE_COPY) ==
656 (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
660 tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb);
661 #if defined(USE_CODE_COPY)
662 /* propagates the FP use info */
663 ((TranslationBlock *)(T0 & ~3))->cflags |=
664 (tb->cflags & CF_FP_USED);
666 spin_unlock(&tb_lock);
670 env->current_tb = tb;
671 /* execute the generated code */
672 gen_func = (void *)tc_ptr;
673 #if defined(__sparc__)
674 __asm__ __volatile__("call %0\n\t"
678 : "i0", "i1", "i2", "i3", "i4", "i5",
679 "l0", "l1", "l2", "l3", "l4", "l5",
681 #elif defined(__arm__)
682 asm volatile ("mov pc, %0\n\t"
683 ".global exec_loop\n\t"
687 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
688 #elif defined(TARGET_I386) && defined(USE_CODE_COPY)
690 if (!(tb->cflags & CF_CODE_COPY)) {
691 if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
692 save_native_fp_state(env);
696 if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
697 restore_native_fp_state(env);
699 /* we work with native eflags */
700 CC_SRC = cc_table[CC_OP].compute_all();
701 CC_OP = CC_OP_EFLAGS;
702 asm(".globl exec_loop\n"
707 " fs movl %11, %%eax\n"
708 " andl $0x400, %%eax\n"
709 " fs orl %8, %%eax\n"
712 " fs movl %%esp, %12\n"
713 " fs movl %0, %%eax\n"
714 " fs movl %1, %%ecx\n"
715 " fs movl %2, %%edx\n"
716 " fs movl %3, %%ebx\n"
717 " fs movl %4, %%esp\n"
718 " fs movl %5, %%ebp\n"
719 " fs movl %6, %%esi\n"
720 " fs movl %7, %%edi\n"
723 " fs movl %%esp, %4\n"
724 " fs movl %12, %%esp\n"
725 " fs movl %%eax, %0\n"
726 " fs movl %%ecx, %1\n"
727 " fs movl %%edx, %2\n"
728 " fs movl %%ebx, %3\n"
729 " fs movl %%ebp, %5\n"
730 " fs movl %%esi, %6\n"
731 " fs movl %%edi, %7\n"
734 " movl %%eax, %%ecx\n"
735 " andl $0x400, %%ecx\n"
737 " andl $0x8d5, %%eax\n"
738 " fs movl %%eax, %8\n"
740 " subl %%ecx, %%eax\n"
741 " fs movl %%eax, %11\n"
742 " fs movl %9, %%ebx\n" /* get T0 value */
745 : "m" (*(uint8_t *)offsetof(CPUState, regs[0])),
746 "m" (*(uint8_t *)offsetof(CPUState, regs[1])),
747 "m" (*(uint8_t *)offsetof(CPUState, regs[2])),
748 "m" (*(uint8_t *)offsetof(CPUState, regs[3])),
749 "m" (*(uint8_t *)offsetof(CPUState, regs[4])),
750 "m" (*(uint8_t *)offsetof(CPUState, regs[5])),
751 "m" (*(uint8_t *)offsetof(CPUState, regs[6])),
752 "m" (*(uint8_t *)offsetof(CPUState, regs[7])),
753 "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
754 "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
756 "m" (*(uint8_t *)offsetof(CPUState, df)),
757 "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
762 #elif defined(__ia64)
769 fp.gp = code_gen_buffer + 2 * (1 << 20);
770 (*(void (*)(void)) &fp)();
774 env->current_tb = NULL;
775 /* reset soft MMU for next block (it can currently
776 only be set by a memory fault) */
777 #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
778 if (env->hflags & HF_SOFTMMU_MASK) {
779 env->hflags &= ~HF_SOFTMMU_MASK;
780 /* do not allow linking to another block */
784 #if defined(USE_KQEMU)
785 #define MIN_CYCLE_BEFORE_SWITCH (100 * 1000)
786 if (kqemu_is_ok(env) &&
787 (cpu_get_time_fast() - env->last_io_time) >= MIN_CYCLE_BEFORE_SWITCH) {
798 #if defined(TARGET_I386)
799 #if defined(USE_CODE_COPY)
800 if (env->native_fp_regs) {
801 save_native_fp_state(env);
804 /* restore flags in standard format */
805 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
807 /* restore global registers */
832 #elif defined(TARGET_ARM)
833 /* XXX: Save/restore host fpu exception state?. */
834 #elif defined(TARGET_SPARC)
835 #if defined(reg_REGWPTR)
836 REGWPTR = saved_regwptr;
838 #elif defined(TARGET_PPC)
839 #elif defined(TARGET_MIPS)
840 #elif defined(TARGET_SH4)
843 #error unsupported target CPU
845 #if defined(__sparc__) && !defined(HOST_SOLARIS)
846 asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
854 /* fail safe : never use cpu_single_env outside cpu_exec() */
855 cpu_single_env = NULL;
859 /* must only be called from the generated code as an exception can be
861 void tb_invalidate_page_range(target_ulong start, target_ulong end)
863 /* XXX: cannot enable it yet because it yields to MMU exception
864 where NIP != read address on PowerPC */
866 target_ulong phys_addr;
867 phys_addr = get_phys_addr_code(env, start);
868 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
872 #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
874 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
876 CPUX86State *saved_env;
880 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
882 cpu_x86_load_seg_cache(env, seg_reg, selector,
883 (selector << 4), 0xffff, 0);
885 load_seg(seg_reg, selector);
890 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
892 CPUX86State *saved_env;
897 helper_fsave((target_ulong)ptr, data32);
902 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
904 CPUX86State *saved_env;
909 helper_frstor((target_ulong)ptr, data32);
914 #endif /* TARGET_I386 */
916 #if !defined(CONFIG_SOFTMMU)
918 #if defined(TARGET_I386)
920 /* 'pc' is the host PC at which the exception was raised. 'address' is
921 the effective address of the memory exception. 'is_write' is 1 if a
922 write caused the exception and otherwise 0'. 'old_set' is the
923 signal set which should be restored */
924 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
925 int is_write, sigset_t *old_set,
928 TranslationBlock *tb;
932 env = cpu_single_env; /* XXX: find a correct solution for multithread */
933 #if defined(DEBUG_SIGNAL)
934 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
935 pc, address, is_write, *(unsigned long *)old_set);
937 /* XXX: locking issue */
938 if (is_write && page_unprotect(h2g(address), pc, puc)) {
942 /* see if it is an MMU fault */
943 ret = cpu_x86_handle_mmu_fault(env, address, is_write,
944 ((env->hflags & HF_CPL_MASK) == 3), 0);
946 return 0; /* not an MMU fault */
948 return 1; /* the MMU fault was handled without causing real CPU fault */
949 /* now we have a real cpu fault */
952 /* the PC is inside the translated code. It means that we have
953 a virtual CPU fault */
954 cpu_restore_state(tb, env, pc, puc);
958 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
959 env->eip, env->cr[2], env->error_code);
961 /* we restore the process signal mask as the sigreturn should
962 do it (XXX: use sigsetjmp) */
963 sigprocmask(SIG_SETMASK, old_set, NULL);
964 raise_exception_err(env->exception_index, env->error_code);
966 /* activate soft MMU for this block */
967 env->hflags |= HF_SOFTMMU_MASK;
968 cpu_resume_from_signal(env, puc);
970 /* never comes here */
974 #elif defined(TARGET_ARM)
975 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
976 int is_write, sigset_t *old_set,
979 TranslationBlock *tb;
983 env = cpu_single_env; /* XXX: find a correct solution for multithread */
984 #if defined(DEBUG_SIGNAL)
985 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
986 pc, address, is_write, *(unsigned long *)old_set);
988 /* XXX: locking issue */
989 if (is_write && page_unprotect(h2g(address), pc, puc)) {
992 /* see if it is an MMU fault */
993 ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0);
995 return 0; /* not an MMU fault */
997 return 1; /* the MMU fault was handled without causing real CPU fault */
998 /* now we have a real cpu fault */
1001 /* the PC is inside the translated code. It means that we have
1002 a virtual CPU fault */
1003 cpu_restore_state(tb, env, pc, puc);
1005 /* we restore the process signal mask as the sigreturn should
1006 do it (XXX: use sigsetjmp) */
1007 sigprocmask(SIG_SETMASK, old_set, NULL);
1010 #elif defined(TARGET_SPARC)
1011 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1012 int is_write, sigset_t *old_set,
1015 TranslationBlock *tb;
1019 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1020 #if defined(DEBUG_SIGNAL)
1021 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1022 pc, address, is_write, *(unsigned long *)old_set);
1024 /* XXX: locking issue */
1025 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1028 /* see if it is an MMU fault */
1029 ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0);
1031 return 0; /* not an MMU fault */
1033 return 1; /* the MMU fault was handled without causing real CPU fault */
1034 /* now we have a real cpu fault */
1035 tb = tb_find_pc(pc);
1037 /* the PC is inside the translated code. It means that we have
1038 a virtual CPU fault */
1039 cpu_restore_state(tb, env, pc, puc);
1041 /* we restore the process signal mask as the sigreturn should
1042 do it (XXX: use sigsetjmp) */
1043 sigprocmask(SIG_SETMASK, old_set, NULL);
1046 #elif defined (TARGET_PPC)
1047 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1048 int is_write, sigset_t *old_set,
1051 TranslationBlock *tb;
1055 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1056 #if defined(DEBUG_SIGNAL)
1057 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1058 pc, address, is_write, *(unsigned long *)old_set);
1060 /* XXX: locking issue */
1061 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1065 /* see if it is an MMU fault */
1066 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
1068 return 0; /* not an MMU fault */
1070 return 1; /* the MMU fault was handled without causing real CPU fault */
1072 /* now we have a real cpu fault */
1073 tb = tb_find_pc(pc);
1075 /* the PC is inside the translated code. It means that we have
1076 a virtual CPU fault */
1077 cpu_restore_state(tb, env, pc, puc);
1081 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1082 env->nip, env->error_code, tb);
1084 /* we restore the process signal mask as the sigreturn should
1085 do it (XXX: use sigsetjmp) */
1086 sigprocmask(SIG_SETMASK, old_set, NULL);
1087 do_raise_exception_err(env->exception_index, env->error_code);
1089 /* activate soft MMU for this block */
1090 cpu_resume_from_signal(env, puc);
1092 /* never comes here */
1096 #elif defined (TARGET_MIPS)
1097 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1098 int is_write, sigset_t *old_set,
1101 TranslationBlock *tb;
1105 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1106 #if defined(DEBUG_SIGNAL)
1107 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1108 pc, address, is_write, *(unsigned long *)old_set);
1110 /* XXX: locking issue */
1111 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1115 /* see if it is an MMU fault */
1116 ret = cpu_mips_handle_mmu_fault(env, address, is_write, 1, 0);
1118 return 0; /* not an MMU fault */
1120 return 1; /* the MMU fault was handled without causing real CPU fault */
1122 /* now we have a real cpu fault */
1123 tb = tb_find_pc(pc);
1125 /* the PC is inside the translated code. It means that we have
1126 a virtual CPU fault */
1127 cpu_restore_state(tb, env, pc, puc);
1131 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1132 env->nip, env->error_code, tb);
1134 /* we restore the process signal mask as the sigreturn should
1135 do it (XXX: use sigsetjmp) */
1136 sigprocmask(SIG_SETMASK, old_set, NULL);
1137 do_raise_exception_err(env->exception_index, env->error_code);
1139 /* activate soft MMU for this block */
1140 cpu_resume_from_signal(env, puc);
1142 /* never comes here */
1146 #elif defined (TARGET_SH4)
1147 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1148 int is_write, sigset_t *old_set,
1151 TranslationBlock *tb;
1155 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1156 #if defined(DEBUG_SIGNAL)
1157 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1158 pc, address, is_write, *(unsigned long *)old_set);
1160 /* XXX: locking issue */
1161 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1165 /* see if it is an MMU fault */
1166 ret = cpu_sh4_handle_mmu_fault(env, address, is_write, 1, 0);
1168 return 0; /* not an MMU fault */
1170 return 1; /* the MMU fault was handled without causing real CPU fault */
1172 /* now we have a real cpu fault */
1173 tb = tb_find_pc(pc);
1175 /* the PC is inside the translated code. It means that we have
1176 a virtual CPU fault */
1177 cpu_restore_state(tb, env, pc, puc);
1180 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1181 env->nip, env->error_code, tb);
1183 /* we restore the process signal mask as the sigreturn should
1184 do it (XXX: use sigsetjmp) */
1185 sigprocmask(SIG_SETMASK, old_set, NULL);
1187 /* never comes here */
1191 #error unsupported target CPU
1194 #if defined(__i386__)
1196 #if defined(USE_CODE_COPY)
1197 static void cpu_send_trap(unsigned long pc, int trap,
1198 struct ucontext *uc)
1200 TranslationBlock *tb;
1203 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1204 /* now we have a real cpu fault */
1205 tb = tb_find_pc(pc);
1207 /* the PC is inside the translated code. It means that we have
1208 a virtual CPU fault */
1209 cpu_restore_state(tb, env, pc, uc);
1211 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
1212 raise_exception_err(trap, env->error_code);
1216 int cpu_signal_handler(int host_signum, struct siginfo *info,
1219 struct ucontext *uc = puc;
1227 #define REG_TRAPNO TRAPNO
1229 pc = uc->uc_mcontext.gregs[REG_EIP];
1230 trapno = uc->uc_mcontext.gregs[REG_TRAPNO];
1231 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
1232 if (trapno == 0x00 || trapno == 0x05) {
1233 /* send division by zero or bound exception */
1234 cpu_send_trap(pc, trapno, uc);
1238 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1240 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1241 &uc->uc_sigmask, puc);
1244 #elif defined(__x86_64__)
1246 int cpu_signal_handler(int host_signum, struct siginfo *info,
1249 struct ucontext *uc = puc;
1252 pc = uc->uc_mcontext.gregs[REG_RIP];
1253 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1254 uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
1255 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1256 &uc->uc_sigmask, puc);
1259 #elif defined(__powerpc__)
1261 /***********************************************************************
1262 * signal context platform-specific definitions
1266 /* All Registers access - only for local access */
1267 # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
1268 /* Gpr Registers access */
1269 # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
1270 # define IAR_sig(context) REG_sig(nip, context) /* Program counter */
1271 # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
1272 # define CTR_sig(context) REG_sig(ctr, context) /* Count register */
1273 # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
1274 # define LR_sig(context) REG_sig(link, context) /* Link register */
1275 # define CR_sig(context) REG_sig(ccr, context) /* Condition register */
1276 /* Float Registers access */
1277 # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
1278 # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
1279 /* Exception Registers access */
1280 # define DAR_sig(context) REG_sig(dar, context)
1281 # define DSISR_sig(context) REG_sig(dsisr, context)
1282 # define TRAP_sig(context) REG_sig(trap, context)
1286 # include <sys/ucontext.h>
1287 typedef struct ucontext SIGCONTEXT;
1288 /* All Registers access - only for local access */
1289 # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
1290 # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
1291 # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
1292 # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
1293 /* Gpr Registers access */
1294 # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
1295 # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
1296 # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
1297 # define CTR_sig(context) REG_sig(ctr, context)
1298 # define XER_sig(context) REG_sig(xer, context) /* Link register */
1299 # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
1300 # define CR_sig(context) REG_sig(cr, context) /* Condition register */
1301 /* Float Registers access */
1302 # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
1303 # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
1304 /* Exception Registers access */
1305 # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
1306 # define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
1307 # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1308 #endif /* __APPLE__ */
1310 int cpu_signal_handler(int host_signum, struct siginfo *info,
1313 struct ucontext *uc = puc;
1321 if (DSISR_sig(uc) & 0x00800000)
1324 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
1327 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1328 is_write, &uc->uc_sigmask, puc);
1331 #elif defined(__alpha__)
1333 int cpu_signal_handler(int host_signum, struct siginfo *info,
1336 struct ucontext *uc = puc;
1337 uint32_t *pc = uc->uc_mcontext.sc_pc;
1338 uint32_t insn = *pc;
1341 /* XXX: need kernel patch to get write flag faster */
1342 switch (insn >> 26) {
1357 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1358 is_write, &uc->uc_sigmask, puc);
1360 #elif defined(__sparc__)
1362 int cpu_signal_handler(int host_signum, struct siginfo *info,
1365 uint32_t *regs = (uint32_t *)(info + 1);
1366 void *sigmask = (regs + 20);
1371 /* XXX: is there a standard glibc define ? */
1373 /* XXX: need kernel patch to get write flag faster */
1375 insn = *(uint32_t *)pc;
1376 if ((insn >> 30) == 3) {
1377 switch((insn >> 19) & 0x3f) {
1389 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1390 is_write, sigmask, NULL);
1393 #elif defined(__arm__)
1395 int cpu_signal_handler(int host_signum, struct siginfo *info,
1398 struct ucontext *uc = puc;
1402 pc = uc->uc_mcontext.gregs[R15];
1403 /* XXX: compute is_write */
1405 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1410 #elif defined(__mc68000)
1412 int cpu_signal_handler(int host_signum, struct siginfo *info,
1415 struct ucontext *uc = puc;
1419 pc = uc->uc_mcontext.gregs[16];
1420 /* XXX: compute is_write */
1422 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1424 &uc->uc_sigmask, puc);
1427 #elif defined(__ia64)
1430 /* This ought to be in <bits/siginfo.h>... */
1431 # define __ISR_VALID 1
1434 int cpu_signal_handler(int host_signum, struct siginfo *info, void *puc)
1436 struct ucontext *uc = puc;
1440 ip = uc->uc_mcontext.sc_ip;
1441 switch (host_signum) {
1447 if (info->si_code && (info->si_segvflags & __ISR_VALID))
1448 /* ISR.W (write-access) is bit 33: */
1449 is_write = (info->si_isr >> 33) & 1;
1455 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1457 &uc->uc_sigmask, puc);
1460 #elif defined(__s390__)
1462 int cpu_signal_handler(int host_signum, struct siginfo *info,
1465 struct ucontext *uc = puc;
1469 pc = uc->uc_mcontext.psw.addr;
1470 /* XXX: compute is_write */
1472 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1474 &uc->uc_sigmask, puc);
1479 #error host CPU specific signal handler needed
1483 #endif /* !defined(CONFIG_SOFTMMU) */