/* Fixed */
#define BLOCK_SHIFT (PAGE_SHIFT + 6)
-struct onenand_s {
- uint32_t id;
+typedef struct {
+ struct {
+ uint16_t man;
+ uint16_t dev;
+ uint16_t ver;
+ } id;
int shift;
target_phys_addr_t base;
qemu_irq intr;
uint16_t intstatus;
uint16_t wpstatus;
- struct ecc_state_s ecc;
+ ECCState ecc;
int density_mask;
int secs;
int secs_cur;
int blocks;
uint8_t *blockwp;
-};
+} OneNANDState;
enum {
ONEN_BUF_BLOCK = 0,
void onenand_base_update(void *opaque, target_phys_addr_t new)
{
- struct onenand_s *s = (struct onenand_s *) opaque;
+ OneNANDState *s = (OneNANDState *) opaque;
s->base = new;
void onenand_base_unmap(void *opaque)
{
- struct onenand_s *s = (struct onenand_s *) opaque;
+ OneNANDState *s = (OneNANDState *) opaque;
cpu_register_physical_memory(s->base,
0x10000 << s->shift, IO_MEM_UNASSIGNED);
}
-static void onenand_intr_update(struct onenand_s *s)
+static void onenand_intr_update(OneNANDState *s)
{
qemu_set_irq(s->intr, ((s->intstatus >> 15) ^ (~s->config[0] >> 6)) & 1);
}
static void onenand_save_state(QEMUFile *f, void *opaque)
{
- struct onenand_s *s = (struct onenand_s *)opaque;
+ OneNANDState *s = (OneNANDState *)opaque;
int i;
if (s->current == s->otp)
static int onenand_load_state(QEMUFile *f, void *opaque, int version_id)
{
- struct onenand_s *s = (struct onenand_s *)opaque;
+ OneNANDState *s = (OneNANDState *)opaque;
int i;
if (version_id)
}
/* Hot reset (Reset OneNAND command) or warm reset (RP pin low) */
-static void onenand_reset(struct onenand_s *s, int cold)
+static void onenand_reset(OneNANDState *s, int cold)
{
memset(&s->addr, 0, sizeof(s->addr));
s->command = 0;
memset(s->blockwp, ONEN_LOCK_LOCKED, s->blocks);
if (s->bdrv && bdrv_read(s->bdrv, 0, s->boot[0], 8) < 0)
- cpu_abort(cpu_single_env, "%s: Loading the BootRAM failed.\n",
- __FUNCTION__);
+ hw_error("%s: Loading the BootRAM failed.\n", __FUNCTION__);
}
}
-static inline int onenand_load_main(struct onenand_s *s, int sec, int secn,
+static inline int onenand_load_main(OneNANDState *s, int sec, int secn,
void *dest)
{
if (s->bdrv_cur)
return 0;
}
-static inline int onenand_prog_main(struct onenand_s *s, int sec, int secn,
+static inline int onenand_prog_main(OneNANDState *s, int sec, int secn,
void *src)
{
- if (s->bdrv_cur)
- return bdrv_write(s->bdrv_cur, sec, src, secn) < 0;
- else if (sec + secn > s->secs_cur)
- return 1;
-
- memcpy(s->current + (sec << 9), src, secn << 9);
+ int result = 0;
+
+ if (secn > 0) {
+ uint32_t size = (uint32_t)secn * 512;
+ const uint8_t *sp = (const uint8_t *)src;
+ uint8_t *dp = 0;
+ if (s->bdrv_cur) {
+ dp = qemu_malloc(size);
+ if (!dp || bdrv_read(s->bdrv_cur, sec, dp, secn) < 0) {
+ result = 1;
+ }
+ } else {
+ if (sec + secn > s->secs_cur) {
+ result = 1;
+ } else {
+ dp = (uint8_t *)s->current + (sec << 9);
+ }
+ }
+ if (!result) {
+ uint32_t i;
+ for (i = 0; i < size; i++) {
+ dp[i] &= sp[i];
+ }
+ if (s->bdrv_cur) {
+ result = bdrv_write(s->bdrv_cur, sec, dp, secn) < 0;
+ }
+ }
+ if (dp && s->bdrv_cur) {
+ qemu_free(dp);
+ }
+ }
- return 0;
+ return result;
}
-static inline int onenand_load_spare(struct onenand_s *s, int sec, int secn,
+static inline int onenand_load_spare(OneNANDState *s, int sec, int secn,
void *dest)
{
uint8_t buf[512];
return 0;
}
-static inline int onenand_prog_spare(struct onenand_s *s, int sec, int secn,
+static inline int onenand_prog_spare(OneNANDState *s, int sec, int secn,
void *src)
{
- uint8_t buf[512];
-
- if (s->bdrv_cur) {
- if (bdrv_read(s->bdrv_cur, s->secs_cur + (sec >> 5), buf, 1) < 0)
- return 1;
- memcpy(buf + ((sec & 31) << 4), src, secn << 4);
- return bdrv_write(s->bdrv_cur, s->secs_cur + (sec >> 5), buf, 1) < 0;
- } else if (sec + secn > s->secs_cur)
- return 1;
-
- memcpy(s->current + (s->secs_cur << 9) + (sec << 4), src, secn << 4);
-
- return 0;
+ int result = 0;
+ if (secn > 0) {
+ const uint8_t *sp = (const uint8_t *)src;
+ uint8_t *dp = 0, *dpp = 0;
+ if (s->bdrv_cur) {
+ dp = qemu_malloc(512);
+ if (!dp || bdrv_read(s->bdrv_cur,
+ s->secs_cur + (sec >> 5),
+ dp, 1) < 0) {
+ result = 1;
+ } else {
+ dpp = dp + ((sec & 31) << 4);
+ }
+ } else {
+ if (sec + secn > s->secs_cur) {
+ result = 1;
+ } else {
+ dpp = s->current + (s->secs_cur << 9) + (sec << 4);
+ }
+ }
+ if (!result) {
+ uint32_t i;
+ for (i = 0; i < (secn << 4); i++) {
+ dpp[i] &= sp[i];
+ }
+ if (s->bdrv_cur) {
+ result = bdrv_write(s->bdrv_cur, s->secs_cur + (sec >> 5),
+ dp, 1) < 0;
+ }
+ }
+ if (dp) {
+ qemu_free(dp);
+ }
+ }
+ return result;
}
-static inline int onenand_erase(struct onenand_s *s, int sec, int num)
+static inline int onenand_erase(OneNANDState *s, int sec, int num)
{
- /* TODO: optimise */
- uint8_t buf[512];
-
- memset(buf, 0xff, sizeof(buf));
- for (; num > 0; num --, sec ++) {
- if (onenand_prog_main(s, sec, 1, buf))
- return 1;
- if (onenand_prog_spare(s, sec, 1, buf))
- return 1;
+ int result = 0;
+
+ uint8_t *buf, *buf2;
+ buf = qemu_malloc(512);
+ if (buf) {
+ buf2 = qemu_malloc(512);
+ if (buf2) {
+ memset(buf, 0xff, 512);
+ for (; !result && num > 0; num--, sec++) {
+ if (s->bdrv_cur) {
+ result = bdrv_write(s->bdrv_cur, sec, buf, 1);
+ if (!result) {
+ result = bdrv_read(s->bdrv_cur,
+ s->secs_cur + (sec >> 5),
+ buf2, 1) < 0;
+ if (!result) {
+ memcpy(buf2 + ((sec & 31) << 4), buf, 1 << 4);
+ result = bdrv_write(s->bdrv_cur,
+ s->secs_cur + (sec >> 5),
+ buf2, 1) < 0;
+ }
+ }
+ } else {
+ if (sec + 1 > s->secs_cur) {
+ result = 1;
+ } else {
+ memcpy(s->current + (sec << 9), buf, 512);
+ memcpy(s->current + (s->secs_cur << 9) + (sec << 4),
+ buf, 1 << 4);
+ }
+ }
+ }
+ qemu_free(buf2);
+ } else {
+ result = 1;
+ }
+ qemu_free(buf);
+ } else {
+ result = 1;
}
-
- return 0;
+
+ return result;
}
-static void onenand_command(struct onenand_s *s, int cmd)
+static void onenand_command(OneNANDState *s, int cmd)
{
int b;
int sec;
SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE)
SETBUF_M()
+
if (onenand_prog_main(s, sec, s->count, buf))
s->status |= ONEN_ERR_CMD | ONEN_ERR_PROG;
static uint32_t onenand_read(void *opaque, target_phys_addr_t addr)
{
- struct onenand_s *s = (struct onenand_s *) opaque;
+ OneNANDState *s = (OneNANDState *) opaque;
int offset = addr >> s->shift;
switch (offset) {
return lduw_le_p(s->boot[0] + addr);
case 0xf000: /* Manufacturer ID */
- return (s->id >> 16) & 0xff;
+ return s->id.man;
case 0xf001: /* Device ID */
- return (s->id >> 8) & 0xff;
- /* TODO: get the following values from a real chip! */
+ return s->id.dev;
case 0xf002: /* Version ID */
- return (s->id >> 0) & 0xff;
+ return s->id.ver;
+ /* TODO: get the following values from a real chip! */
case 0xf003: /* Data Buffer size */
return 1 << PAGE_SHIFT;
case 0xf004: /* Boot Buffer size */
case 0xff02: /* ECC Result of spare area data */
case 0xff03: /* ECC Result of main area data */
case 0xff04: /* ECC Result of spare area data */
- cpu_abort(cpu_single_env, "%s: imeplement ECC\n", __FUNCTION__);
+ hw_error("%s: imeplement ECC\n", __FUNCTION__);
return 0x0000;
}
static void onenand_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
- struct onenand_s *s = (struct onenand_s *) opaque;
+ OneNANDState *s = (OneNANDState *) opaque;
int offset = addr >> s->shift;
int sec;
case 0x0090: /* Read Identification Data */
memset(s->boot[0], 0, 3 << s->shift);
- s->boot[0][0 << s->shift] = (s->id >> 16) & 0xff;
- s->boot[0][1 << s->shift] = (s->id >> 8) & 0xff;
+ s->boot[0][0 << s->shift] = s->id.man & 0xff;
+ s->boot[0][1 << s->shift] = s->id.dev & 0xff;
s->boot[0][2 << s->shift] = s->wpstatus & 0xff;
break;
onenand_write,
};
-void *onenand_init(uint32_t id, int regshift, qemu_irq irq)
+void *onenand_init(uint16_t man_id, uint16_t dev_id, uint16_t ver_id,
+ int regshift, qemu_irq irq, BlockDriverState *bs)
{
- struct onenand_s *s = (struct onenand_s *) qemu_mallocz(sizeof(*s));
- int bdrv_index = drive_get_index(IF_MTD, 0, 0);
- uint32_t size = 1 << (24 + ((id >> 12) & 7));
+ OneNANDState *s = (OneNANDState *) qemu_mallocz(sizeof(*s));
+ uint32_t size = 1 << (24 + ((dev_id >> 4) & 7));
void *ram;
s->shift = regshift;
s->intr = irq;
s->rdy = 0;
- s->id = id;
+ s->id.man = man_id;
+ s->id.dev = dev_id;
+ s->id.ver = ver_id;
s->blocks = size >> BLOCK_SHIFT;
s->secs = size >> 9;
s->blockwp = qemu_malloc(s->blocks);
- s->density_mask = (id & (1 << 11)) ? (1 << (6 + ((id >> 12) & 7))) : 0;
+ s->density_mask = (dev_id & 0x08) ? (1 << (6 + ((dev_id >> 4) & 7))) : 0;
s->iomemtype = cpu_register_io_memory(0, onenand_readfn,
onenand_writefn, s);
- if (bdrv_index == -1)
+ if (!bs)
s->image = memset(qemu_malloc(size + (size >> 5)),
0xff, size + (size >> 5));
else
- s->bdrv = drives_table[bdrv_index].bdrv;
+ s->bdrv = bs;
s->otp = memset(qemu_malloc((64 + 2) << PAGE_SHIFT),
0xff, (64 + 2) << PAGE_SHIFT);
s->ram = qemu_ram_alloc(0xc000 << s->shift);
onenand_reset(s, 1);
- register_savevm("onenand", id | ((regshift & 0x7f) << 24), 0,
+ register_savevm("onenand",
+ ((regshift & 0x7f) << 24)
+ | ((man_id & 0xff) << 16)
+ | ((dev_id & 0xff) << 8)
+ | (ver_id & 0xff),
+ 0,
onenand_save_state, onenand_load_state, s);
return s;
void *onenand_raw_otp(void *opaque)
{
- struct onenand_s *s = (struct onenand_s *) opaque;
+ OneNANDState *s = (OneNANDState *) opaque;
return s->otp;
}
projects / qemu / blobdiff