Maemo patchset 20101501+0m5

[h-e-n] / drivers / serial / 8250.c

diff --git a/drivers/serial/8250.c b/drivers/serial/8250.c
index 303272a..55ef629 100644 (file)
--- a/drivers/serial/8250.c
+++ b/drivers/serial/8250.c
@@ -1456,6 +1456,16 @@ static void serial8250_handle_port(struct uart_8250_port *up)
        if (status & UART_LSR_THRE)
                transmit_chars(up);
 
+#ifdef CONFIG_ARCH_OMAP
+       /*
+        * OMAP3 UART has a special RX_FIFO_STATUS bit that will stall
+        * RX transfer on FIFO overflow until the RX fifo is cleared.
+        */
+       if (cpu_is_omap34xx() && is_omap_port(up) &&
+                                       status & UART_LSR_RX_FIFO_STS)
+               serial_outp(up, UART_FCR, uart_config[up->port.type].fcr |
+                                       UART_FCR_CLEAR_RCVR);
+#endif
        spin_unlock_irqrestore(&up->port.lock, flags);
 }
 
@@ -1527,7 +1537,11 @@ static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
 
        DEBUG_INTR("end.\n");
 
+#ifdef CONFIG_ARCH_OMAP15XX
+       return IRQ_HANDLED;     /* FIXME: iir status not ready on 1510 */
+#else
        return IRQ_RETVAL(handled);
+#endif
 }
 
 /*
@@ -2303,6 +2317,19 @@ serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
                        /* emulated UARTs (Lucent Venus 167x) need two steps */
                        serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
                }
+
+               /* Note that we need to set ECB to access write water mark
+                * bits. First allow FCR tx fifo write, then set fcr with
+                * possible TX fifo settings. */
+               if (uart_config[up->port.type].flags & UART_CAP_EFR) {
+                       serial_outp(up, UART_LCR, 0xbf);        /* Access EFR */
+                       serial_outp(up, UART_EFR, UART_EFR_ECB);
+                       serial_outp(up, UART_LCR, 0x0);         /* Access FCR */
+                       serial_outp(up, UART_FCR, fcr);
+                       serial_outp(up, UART_LCR, 0xbf);        /* Access EFR */
+                       serial_outp(up, UART_EFR, 0);
+                       serial_outp(up, UART_LCR, cval);        /* Access FCR */
+        } else
                serial_outp(up, UART_FCR, fcr);         /* set fcr */
        }
        serial8250_set_mctrl(&up->port, up->port.mctrl);