}
mst_irq = mst_irq_init(cpu, MST_FPGA_PHYS, PXA2XX_PIC_GPIO_0);
+
+ /* MMC/SD host */
+ pxa2xx_mmci_handlers(cpu->mmc, mst_irq[MMC_IRQ], mst_irq[MMC_IRQ]);
+
smc91c111_init(&nd_table[0], MST_ETH_PHYS, mst_irq[ETHERNET_IRQ]);
arm_load_kernel(cpu->env, mainstone_ram, kernel_filename, kernel_cmdline,
#define MST_FLASH_1 0x04000000
/* IRQ definitions */
-#define ETHERNET_IRQ 3
+#define MMC_IRQ 0
+#define USIM_IRQ 1
+#define USBC_IRQ 2
+#define ETHERNET_IRQ 3
+#define AC97_IRQ 4
+#define PEN_IRQ 5
+#define MSINS_IRQ 6
+#define EXBRD_IRQ 7
+#define S0_CD_IRQ 9
+#define S0_STSCHG_IRQ 10
+#define S0_IRQ 11
+#define S1_CD_IRQ 13
+#define S1_STSCHG_IRQ 14
+#define S1_IRQ 15
extern qemu_irq
*mst_irq_init(struct pxa2xx_state_s *cpu, uint32_t base, int irq);