Replace patch overclock_smartreflex_805.diff with overclock_smartreflex_900.diff

Patch overclock_smartreflex_900.diff by freemangordon and his changelog:

1. VDD1 efuse calibration values support up to 900MHz

2. Fixed bug (introduced by me) causing incorrect efuse calibration value to be used for VDD1 SR (i.e. instead calibration value for OPP(n), calibration value for OPP(n-1) was used)

3. efuse calibration values for all VDD1 OPPs recalculated as stock ones(for 125MHz and 250MHz) were keeping too high voltages

4. added several entries under /sys/power
    sr_vdd1_voltage
    sr_vdd2_voltage
    efuse_vdd2

    sr_vdd1_voltage, sr_vdd2_voltage reflect current voltages for VDD1 and VDD2 respectively when SmartReflex is active

5. /sys/power/Efuse renamed to efuse_vdd1

6. When SmartReflex is active, current calculated voltage is stored as default for current frequency when frequency switch occurs. That way next time this frequency becomes active, AVS starts from last voltage(+1 to be on a safe side) instead from profile value(no overvoltage happens on frequency switch).

7. In case DSP is overclocked for a particular frequency a little voltage boost is added to SR calibration for that frequency(12.5 mV if 430<freq<=520 and 25mV if freq>520).

8. SmartReflex AVS step reduced to 1(12.5mV) from 4(50mV) to prevent undervoltage