written */ \
target_ulong mem_write_vaddr; /* target virtual addr at which the \
memory was written */ \
+ int halted; /* TRUE if the CPU is in suspend state */ \
/* The meaning of the MMU modes is defined in the target code. */ \
CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \
struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \
static void apic_startup(APICState *s, int vector_num)
{
CPUState *env = s->cpu_env;
- if (!(env->hflags & HF_HALTED_MASK))
+ if (!env->halted)
return;
env->eip = 0;
cpu_x86_load_seg_cache(env, R_CS, vector_num << 8, vector_num << 12,
0xffff, 0);
- env->hflags &= ~HF_HALTED_MASK;
+ env->halted = 0;
}
static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode,
exit(1);
}
if (i != 0)
- env->hflags |= HF_HALTED_MASK;
+ env->halted = 1;
if (smp_cpus > 1) {
/* XXX: enable it in all cases */
env->cpuid_features |= CPUID_APIC;
env->cpu_index);
#if defined(TARGET_I386)
term_printf(" pc=0x" TARGET_FMT_lx, env->eip + env->segs[R_CS].base);
- if (env->hflags & HF_HALTED_MASK)
- term_printf(" (halted)");
#elif defined(TARGET_PPC)
term_printf(" nip=0x" TARGET_FMT_lx, env->nip);
- if (env->halted)
- term_printf(" (halted)");
#elif defined(TARGET_SPARC)
term_printf(" pc=0x" TARGET_FMT_lx " npc=0x" TARGET_FMT_lx, env->pc, env->npc);
- if (env->halted)
- term_printf(" (halted)");
#elif defined(TARGET_MIPS)
term_printf(" PC=0x" TARGET_FMT_lx, env->PC[env->current_tc]);
+#endif
if (env->halted)
term_printf(" (halted)");
-#endif
term_printf("\n");
}
}
jmp_buf jmp_env;
int user_mode_only; /* user mode only simulation */
uint32_t hflags;
- int halted;
int exception_index;
int error_code;
int exception_index;
int interrupt_request;
int user_mode_only;
- int halted;
/* VFP coprocessor state. */
struct {
int features;
int user_mode_only;
- int halted;
jmp_buf jmp_env;
CPU_COMMON
#define ID_MASK 0x00200000
/* hidden flags - used internally by qemu to represent additional cpu
- states. Only the CPL, INHIBIT_IRQ and HALTED are not redundant. We avoid
+ states. Only the CPL and INHIBIT_IRQ are not redundant. We avoid
using the IOPL_MASK, TF_MASK and VM_MASK bit position to ease oring
with eflags. */
/* current cpl */
#define HF_CS64_SHIFT 15 /* only used on x86_64: 64 bit code segment */
#define HF_OSFXSR_SHIFT 16 /* CR4.OSFXSR */
#define HF_VM_SHIFT 17 /* must be same as eflags */
-#define HF_HALTED_SHIFT 18 /* CPU halted */
#define HF_SMM_SHIFT 19 /* CPU in SMM mode */
#define HF_GIF_SHIFT 20 /* if set CPU takes interrupts */
#define HF_HIF_SHIFT 21 /* shadow copy of IF_MASK when in SVM */
#define HF_LMA_MASK (1 << HF_LMA_SHIFT)
#define HF_CS64_MASK (1 << HF_CS64_SHIFT)
#define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT)
-#define HF_HALTED_MASK (1 << HF_HALTED_SHIFT)
#define HF_SMM_MASK (1 << HF_SMM_SHIFT)
#define HF_GIF_MASK (1 << HF_GIF_SHIFT)
#define HF_HIF_MASK (1 << HF_HIF_SHIFT)
static inline int cpu_halted(CPUState *env) {
/* handle exit of HALTED state */
- if (!(env->hflags & HF_HALTED_MASK))
+ if (!env->halted)
return 0;
/* disable halt condition */
if (((env->interrupt_request & CPU_INTERRUPT_HARD) &&
(env->eflags & IF_MASK)) ||
(env->interrupt_request & CPU_INTERRUPT_NMI)) {
- env->hflags &= ~HF_HALTED_MASK;
+ env->halted = 0;
return 0;
}
return EXCP_HALTED;
(env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
(int)(env->a20_mask >> 20) & 1,
(env->hflags >> HF_SMM_SHIFT) & 1,
- (env->hflags >> HF_HALTED_SHIFT) & 1);
+ env->halted);
} else
#endif
{
(env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
(int)(env->a20_mask >> 20) & 1,
(env->hflags >> HF_SMM_SHIFT) & 1,
- (env->hflags >> HF_HALTED_SHIFT) & 1);
+ env->halted);
}
#ifdef TARGET_X86_64
helper_svm_check_intercept_param(SVM_EXIT_HLT, 0);
env->hflags &= ~HF_INHIBIT_IRQ_MASK; /* needed if sti is just before */
- env->hflags |= HF_HALTED_MASK;
+ env->halted = 1;
env->exception_index = EXCP_HLT;
cpu_loop_exit();
}
int exception_index;
int interrupt_request;
int user_mode_only;
- uint32_t halted;
int pending_vector;
int pending_level;
target_ulong btarget; /* Jump / branch target */
int bcond; /* Branch condition (if needed) */
- int halted; /* TRUE if the CPU is in suspend state */
-
int SYNCI_Step; /* Address step size for SYNCI */
int CCRes; /* Cycle count resolution/divisor */
uint32_t CP0_Status_rw_bitmask; /* Read/write bits in CP0_Status */
CPU_COMMON
- int halted; /* TRUE if the CPU is in suspend state */
-
int access_type; /* when a memory exception occurs, the access
type is stored here */
jmp_buf jmp_env;
int user_mode_only;
int interrupt_request;
- int halted;
int exception_index;
CPU_COMMON tlb_t utlb[UTLB_SIZE]; /* unified translation table */
tlb_t itlb[ITLB_SIZE]; /* instruction translation table */
int exception_index;
int interrupt_index;
int interrupt_request;
- int halted;
uint32_t mmu_bm;
uint32_t mmu_ctpr_mask;
uint32_t mmu_cxr_mask;