void helper_memalign(uint32_t addr, uint32_t dr, uint32_t wr, uint32_t mask)
{
if (addr & mask) {
- qemu_log("unaligned access addr=%x mask=%x, wr=%d\n",
- addr, mask, wr);
- if (!(env->sregs[SR_MSR] & MSR_EE)) {
- return;
- }
-
+ qemu_log_mask(CPU_LOG_INT,
+ "unaligned access addr=%x mask=%x, wr=%d dr=r%d\n",
+ addr, mask, wr, dr);
+ env->sregs[SR_EAR] = addr;
env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA | (wr << 10) \
| (dr & 31) << 5;
if (mask == 3) {
env->sregs[SR_ESR] |= 1 << 11;
}
+ if (!(env->sregs[SR_MSR] & MSR_EE)) {
+ return;
+ }
helper_raise_exception(EXCP_HW_EXCP);
}
}
generated code */
saved_env = env;
env = cpu_single_env;
- qemu_log("Unassigned " TARGET_FMT_plx " wr=%d exe=%d\n",
+ qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=%d exe=%d\n",
addr, is_write, is_exec);
if (!(env->sregs[SR_MSR] & MSR_EE)) {
return;
}
+ env->sregs[SR_EAR] = addr;
if (is_exec) {
- if (!(env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) {
+ if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) {
env->sregs[SR_ESR] = ESR_EC_INSN_BUS;
helper_raise_exception(EXCP_HW_EXCP);
}
} else {
- if (!(env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) {
+ if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) {
env->sregs[SR_ESR] = ESR_EC_DATA_BUS;
helper_raise_exception(EXCP_HW_EXCP);
}
int l1;
if ((dc->tb_flags & MSR_EE_FLAG)
- && !(dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
+ && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
&& !((dc->env->pvr.regs[2] & PVR2_USE_PCMP_INSTR))) {
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
t_gen_raise_exception(dc, EXCP_HW_EXCP);
unsigned int subcode;
if ((dc->tb_flags & MSR_EE_FLAG)
- && !(dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
+ && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
&& !(dc->env->pvr.regs[0] & PVR0_USE_HW_MUL_MASK)) {
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
t_gen_raise_exception(dc, EXCP_HW_EXCP);
u = dc->imm & 2;
LOG_DIS("div\n");
- if (!(dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
+ if ((dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
&& !((dc->env->pvr.regs[0] & PVR0_USE_DIV_MASK))) {
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
t_gen_raise_exception(dc, EXCP_HW_EXCP);
unsigned int s, t;
if ((dc->tb_flags & MSR_EE_FLAG)
- && !(dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
+ && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
&& !(dc->env->pvr.regs[0] & PVR0_USE_BARREL_MASK)) {
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
t_gen_raise_exception(dc, EXCP_HW_EXCP);
size = 1 << (dc->opcode & 3);
if (size > 4 && (dc->tb_flags & MSR_EE_FLAG)
- && !(dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
+ && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
t_gen_raise_exception(dc, EXCP_HW_EXCP);
return;
size = 1 << (dc->opcode & 3);
if (size > 4 && (dc->tb_flags & MSR_EE_FLAG)
- && !(dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
+ && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) {
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
t_gen_raise_exception(dc, EXCP_HW_EXCP);
return;
static void dec_fpu(DisasContext *dc)
{
if ((dc->tb_flags & MSR_EE_FLAG)
- && !(dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
+ && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
&& !((dc->env->pvr.regs[2] & PVR2_USE_FPU_MASK))) {
- tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
+ tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_FPU);
t_gen_raise_exception(dc, EXCP_HW_EXCP);
return;
}
dc->nr_nops = 0;
else {
if ((dc->tb_flags & MSR_EE_FLAG)
- && !(dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
- && !(dc->env->pvr.regs[2] & PVR2_OPCODE_0x0_ILL_MASK)) {
+ && (dc->env->pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
+ && (dc->env->pvr.regs[2] & PVR2_OPCODE_0x0_ILL_MASK)) {
tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
t_gen_raise_exception(dc, EXCP_HW_EXCP);
return;