void op_rdhwr_cpunum(void)
{
if (!(env->hflags & MIPS_HFLAG_UM) ||
- (env->CP0_HWREna & (1 << 0)) ||
+ (env->CP0_HWREna & (1 << 0)) ||
(env->CP0_Status & (1 << CP0St_CU0)))
T0 = env->CP0_EBase & 0x3ff;
else
void op_rdhwr_synci_step(void)
{
if (!(env->hflags & MIPS_HFLAG_UM) ||
- (env->CP0_HWREna & (1 << 1)) ||
+ (env->CP0_HWREna & (1 << 1)) ||
(env->CP0_Status & (1 << CP0St_CU0)))
T0 = env->SYNCI_Step;
else
void op_rdhwr_cc(void)
{
if (!(env->hflags & MIPS_HFLAG_UM) ||
- (env->CP0_HWREna & (1 << 2)) ||
+ (env->CP0_HWREna & (1 << 2)) ||
(env->CP0_Status & (1 << CP0St_CU0)))
T0 = env->CP0_Count;
else
void op_rdhwr_ccres(void)
{
if (!(env->hflags & MIPS_HFLAG_UM) ||
- (env->CP0_HWREna & (1 << 3)) ||
+ (env->CP0_HWREna & (1 << 3)) ||
(env->CP0_Status & (1 << CP0St_CU0)))
T0 = env->CCRes;
else
RETURN();
}
-void op_rdhwr_unimpl30(void)
-{
- if (!(env->hflags & MIPS_HFLAG_UM) ||
- (env->CP0_HWREna & (1 << 30)) ||
- (env->CP0_Status & (1 << CP0St_CU0)))
- T0 = 0;
- else
- CALL_FROM_TB1(do_raise_exception, EXCP_RI);
- RETURN();
-}
-
-void op_rdhwr_unimpl31(void)
-{
- if (!(env->hflags & MIPS_HFLAG_UM) ||
- (env->CP0_HWREna & (1 << 31)) ||
- (env->CP0_Status & (1 << CP0St_CU0)))
- T0 = 0;
- else
- CALL_FROM_TB1(do_raise_exception, EXCP_RI);
- RETURN();
-}
-
void op_save_state (void)
{
env->hflags = PARAM1;
case OPC_RDHWR:
switch (rd) {
case 0:
+ save_cpu_state(ctx, 1);
gen_op_rdhwr_cpunum();
break;
case 1:
+ save_cpu_state(ctx, 1);
gen_op_rdhwr_synci_step();
break;
case 2:
+ save_cpu_state(ctx, 1);
gen_op_rdhwr_cc();
break;
case 3:
+ save_cpu_state(ctx, 1);
gen_op_rdhwr_ccres();
break;
case 29:
#if defined (CONFIG_USER_ONLY)
gen_op_tls_value ();
-#else
- generate_exception(ctx, EXCP_RI);
-#endif
- break;
- case 30:
- /* Implementation dependent */;
- gen_op_rdhwr_unimpl30();
- break;
- case 31:
- /* Implementation dependent */;
- gen_op_rdhwr_unimpl31();
break;
+#endif
default: /* Invalid */
MIPS_INVAL("rdhwr");
generate_exception(ctx, EXCP_RI);