sh4: fix tas.b @Rn instruction

(Shin-ichiro KAWASAKI, based on a patch from Andrzej Zaborowski)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5074 c046a42c-6fe2-441c-8c8c-71466251a162

diff --git a/target-sh4/op.c b/target-sh4/op.c
index 37ac930..54a5c7b 100644 (file)
--- a/target-sh4/op.c
+++ b/target-sh4/op.c
@@ -592,13 +592,6 @@ void OPPROTO op_shlr16_Rn(void)
     RETURN();
 }
 
-void OPPROTO op_tasb_rN(void)
-{
-    cond_t((env->gregs[PARAM1] & 0xff) == 0);
-    *(int8_t *) &env->gregs[PARAM1] |= 0x80;
-    RETURN();
-}
-
 void OPPROTO op_movl_T0_rN(void)
 {
     env->gregs[PARAM1] = T0;

diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 2403515..9ea6b3e 100644 (file)
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -1100,7 +1100,12 @@ void _decode_opc(DisasContext * ctx)
        gen_op_shlr16_Rn(REG(B11_8));
        return;
     case 0x401b:               /* tas.b @Rn */
-       gen_op_tasb_rN(REG(B11_8));
+       gen_op_movl_rN_T0(REG(B11_8));
+       gen_op_movl_T0_T1();
+       gen_op_ldub_T0_T0(ctx);
+       gen_op_cmp_eq_imm_T0(0);
+       gen_op_or_imm_T0(0x80);
+       gen_op_stb_T0_T1(ctx);
        return;
     case 0xf00d: /* fsts FPUL,FRn - FPSCR: Nothing */
        gen_op_movl_fpul_FT0();