target-ppc: convert dcbz instruction to TCG

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5826 c046a42c-6fe2-441c-8c8c-71466251a162

diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index a3e5ea0..471188f 100644 (file)
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -9,6 +9,8 @@ DEF_HELPER_3(td, void, tl, tl, i32)
 
 DEF_HELPER_2(lmw, void, tl, i32)
 DEF_HELPER_2(stmw, void, tl, i32)
+DEF_HELPER_1(dcbz, void, tl)
+DEF_HELPER_1(dcbz_970, void, tl)
 
 DEF_HELPER_2(fcmpo, i32, i64, i64)
 DEF_HELPER_2(fcmpu, i32, i64, i64)

diff --git a/target-ppc/op.c b/target-ppc/op.c
index 16ab589..03ba0d7 100644 (file)
--- a/target-ppc/op.c
+++ b/target-ppc/op.c
@@ -273,23 +273,6 @@ void OPPROTO op_srli_T1 (void)
 #include "op_mem.h"
 #endif
 
-/* Special op to check and maybe clear reservation */
-void OPPROTO op_check_reservation (void)
-{
-    if ((uint32_t)env->reserve == (uint32_t)(T0 & ~0x00000003))
-        env->reserve = (target_ulong)-1ULL;
-    RETURN();
-}
-
-#if defined(TARGET_PPC64)
-void OPPROTO op_check_reservation_64 (void)
-{
-    if ((uint64_t)env->reserve == (uint64_t)(T0 & ~0x00000003))
-        env->reserve = (target_ulong)-1ULL;
-    RETURN();
-}
-#endif
-
 /* Return from interrupt */
 #if !defined(CONFIG_USER_ONLY)
 void OPPROTO op_rfi (void)

diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index 4796e60..6f6f1ec 100644 (file)
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -56,7 +56,6 @@ void helper_raise_debug (void)
     raise_exception(env, EXCP_DEBUG);
 }
 
-
 /*****************************************************************************/
 /* Registers load and stores */
 target_ulong helper_load_cr (void)
@@ -171,6 +170,46 @@ void helper_stmw (target_ulong addr, uint32_t reg)
     }
 }
 
+static void do_dcbz(target_ulong addr, int dcache_line_size)
+{
+    target_long mask = get_addr(~(dcache_line_size - 1));
+    int i;
+#ifdef CONFIG_USER_ONLY
+#define stfun stl_raw
+#else
+    void (*stfun)(target_ulong, int);
+
+    switch (env->mmu_idx) {
+    default:
+    case 0: stfun = stl_user;
+        break;
+    case 1: stfun = stl_kernel;
+        break;
+    case 2: stfun = stl_hypv;
+        break;
+    }
+#endif
+    addr &= mask;
+    for (i = 0 ; i < dcache_line_size ; i += 4) {
+        stfun(addr + i , 0);
+    }
+    if ((env->reserve & mask) == addr)
+        env->reserve = (target_ulong)-1ULL;
+}
+
+void helper_dcbz(target_ulong addr)
+{
+    do_dcbz(addr, env->dcache_line_size);
+}
+
+void helper_dcbz_970(target_ulong addr)
+{
+    if (((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1)
+        do_dcbz(addr, 32);
+    else
+        do_dcbz(addr, env->dcache_line_size);
+}
+
 /*****************************************************************************/
 /* Fixed point operations helpers */
 #if defined(TARGET_PPC64)
@@ -1219,7 +1258,6 @@ uint64_t helper_fnmsub (uint64_t arg1, uint64_t arg2, uint64_t arg3)
     return farg1.ll;
 }
 
-
 /* frsp - frsp. */
 uint64_t helper_frsp (uint64_t arg)
 {

diff --git a/target-ppc/op_helper.h b/target-ppc/op_helper.h
index 675292f..9c0413e 100644 (file)
--- a/target-ppc/op_helper.h
+++ b/target-ppc/op_helper.h
@@ -24,7 +24,6 @@
 void glue(do_lsw, MEMSUFFIX) (int dst);
 void glue(do_stsw, MEMSUFFIX) (int src);
 void glue(do_icbi, MEMSUFFIX) (void);
-void glue(do_dcbz, MEMSUFFIX) (void);
 void glue(do_POWER_lscbx, MEMSUFFIX) (int dest, int ra, int rb);
 void glue(do_POWER2_lfq, MEMSUFFIX) (void);
 void glue(do_POWER2_lfq_le, MEMSUFFIX) (void);
@@ -35,7 +34,6 @@ void glue(do_POWER2_stfq_le, MEMSUFFIX) (void);
 void glue(do_lsw_64, MEMSUFFIX) (int dst);
 void glue(do_stsw_64, MEMSUFFIX) (int src);
 void glue(do_icbi_64, MEMSUFFIX) (void);
-void glue(do_dcbz_64, MEMSUFFIX) (void);
 #endif
 
 #else

diff --git a/target-ppc/op_helper_mem.h b/target-ppc/op_helper_mem.h
index cb61e96..2c3d5fa 100644 (file)
--- a/target-ppc/op_helper_mem.h
+++ b/target-ppc/op_helper_mem.h
@@ -123,100 +123,6 @@ void glue(do_icbi_64, MEMSUFFIX) (void)
 }
 #endif
 
-void glue(do_dcbz, MEMSUFFIX) (void)
-{
-    int dcache_line_size = env->dcache_line_size;
-
-    /* XXX: should be 970 specific (?) */
-    if (((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1)
-        dcache_line_size = 32;
-    T0 &= ~(uint32_t)(dcache_line_size - 1);
-    glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x00), 0);
-    glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x04), 0);
-    glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x08), 0);
-    glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x0C), 0);
-    glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x10), 0);
-    glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x14), 0);
-    glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x18), 0);
-    glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x1C), 0);
-    if (dcache_line_size >= 64) {
-        glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x20UL), 0);
-        glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x24UL), 0);
-        glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x28UL), 0);
-        glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x2CUL), 0);
-        glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x30UL), 0);
-        glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x34UL), 0);
-        glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x38UL), 0);
-        glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x3CUL), 0);
-        if (dcache_line_size >= 128) {
-            glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x40UL), 0);
-            glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x44UL), 0);
-            glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x48UL), 0);
-            glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x4CUL), 0);
-            glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x50UL), 0);
-            glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x54UL), 0);
-            glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x58UL), 0);
-            glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x5CUL), 0);
-            glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x60UL), 0);
-            glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x64UL), 0);
-            glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x68UL), 0);
-            glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x6CUL), 0);
-            glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x70UL), 0);
-            glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x74UL), 0);
-            glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x78UL), 0);
-            glue(stl, MEMSUFFIX)((uint32_t)(T0 + 0x7CUL), 0);
-        }
-    }
-}
-
-#if defined(TARGET_PPC64)
-void glue(do_dcbz_64, MEMSUFFIX) (void)
-{
-    int dcache_line_size = env->dcache_line_size;
-
-    /* XXX: should be 970 specific (?) */
-    if (((env->spr[SPR_970_HID5] >> 6) & 0x3) == 0x2)
-        dcache_line_size = 32;
-    T0 &= ~(uint64_t)(dcache_line_size - 1);
-    glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x00), 0);
-    glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x04), 0);
-    glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x08), 0);
-    glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x0C), 0);
-    glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x10), 0);
-    glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x14), 0);
-    glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x18), 0);
-    glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x1C), 0);
-    if (dcache_line_size >= 64) {
-        glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x20UL), 0);
-        glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x24UL), 0);
-        glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x28UL), 0);
-        glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x2CUL), 0);
-        glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x30UL), 0);
-        glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x34UL), 0);
-        glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x38UL), 0);
-        glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x3CUL), 0);
-        if (dcache_line_size >= 128) {
-            glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x40UL), 0);
-            glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x44UL), 0);
-            glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x48UL), 0);
-            glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x4CUL), 0);
-            glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x50UL), 0);
-            glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x54UL), 0);
-            glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x58UL), 0);
-            glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x5CUL), 0);
-            glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x60UL), 0);
-            glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x64UL), 0);
-            glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x68UL), 0);
-            glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x6CUL), 0);
-            glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x70UL), 0);
-            glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x74UL), 0);
-            glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x78UL), 0);
-            glue(stl, MEMSUFFIX)((uint64_t)(T0 + 0x7CUL), 0);
-        }
-    }
-}
-#endif
-
 /* PowerPC 601 specific instructions (POWER bridge) */
 // XXX: to be tested
 void glue(do_POWER_lscbx, MEMSUFFIX) (int dest, int ra, int rb)

diff --git a/target-ppc/op_mem.h b/target-ppc/op_mem.h
index 40120db..6f9eb20 100644 (file)
--- a/target-ppc/op_mem.h
+++ b/target-ppc/op_mem.h
@@ -314,168 +314,6 @@ void OPPROTO glue(op_stdcx_le_64, MEMSUFFIX) (void)
 }
 #endif
 
-void OPPROTO glue(op_dcbz_l32, MEMSUFFIX) (void)
-{
-    T0 &= ~((uint32_t)31);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x00), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x04), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x08), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x0C), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x10), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x14), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x18), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x1C), 0);
-    RETURN();
-}
-
-void OPPROTO glue(op_dcbz_l64, MEMSUFFIX) (void)
-{
-    T0 &= ~((uint32_t)63);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x00), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x04), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x08), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x0C), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x10), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x14), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x18), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x1C), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x20UL), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x24UL), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x28UL), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x2CUL), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x30UL), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x34UL), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x38UL), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x3CUL), 0);
-    RETURN();
-}
-
-void OPPROTO glue(op_dcbz_l128, MEMSUFFIX) (void)
-{
-    T0 &= ~((uint32_t)127);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x00), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x04), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x08), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x0C), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x10), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x14), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x18), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x1C), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x20UL), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x24UL), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x28UL), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x2CUL), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x30UL), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x34UL), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x38UL), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x3CUL), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x40UL), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x44UL), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x48UL), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x4CUL), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x50UL), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x54UL), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x58UL), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x5CUL), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x60UL), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x64UL), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x68UL), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x6CUL), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x70UL), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x74UL), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x78UL), 0);
-    glue(st32, MEMSUFFIX)((uint32_t)(T0 + 0x7CUL), 0);
-    RETURN();
-}
-
-void OPPROTO glue(op_dcbz, MEMSUFFIX) (void)
-{
-    glue(do_dcbz, MEMSUFFIX)();
-    RETURN();
-}
-
-#if defined(TARGET_PPC64)
-void OPPROTO glue(op_dcbz_l32_64, MEMSUFFIX) (void)
-{
-    T0 &= ~((uint64_t)31);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x00), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x04), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x08), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x0C), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x10), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x14), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x18), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x1C), 0);
-    RETURN();
-}
-
-void OPPROTO glue(op_dcbz_l64_64, MEMSUFFIX) (void)
-{
-    T0 &= ~((uint64_t)63);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x00), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x04), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x08), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x0C), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x10), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x14), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x18), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x1C), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x20UL), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x24UL), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x28UL), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x2CUL), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x30UL), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x34UL), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x38UL), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x3CUL), 0);
-    RETURN();
-}
-
-void OPPROTO glue(op_dcbz_l128_64, MEMSUFFIX) (void)
-{
-    T0 &= ~((uint64_t)127);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x00), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x04), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x08), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x0C), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x10), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x14), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x18), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x1C), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x20UL), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x24UL), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x28UL), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x2CUL), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x30UL), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x34UL), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x38UL), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x3CUL), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x40UL), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x44UL), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x48UL), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x4CUL), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x50UL), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x54UL), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x58UL), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x5CUL), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x60UL), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x64UL), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x68UL), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x6CUL), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x70UL), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x74UL), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x78UL), 0);
-    glue(st32, MEMSUFFIX)((uint64_t)(T0 + 0x7CUL), 0);
-    RETURN();
-}
-
-void OPPROTO glue(op_dcbz_64, MEMSUFFIX) (void)
-{
-    glue(do_dcbz_64, MEMSUFFIX)();
-    RETURN();
-}
-#endif
-
 /* Instruction cache block invalidate */
 void OPPROTO glue(op_icbi, MEMSUFFIX) (void)
 {

diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index fe4a745..b429a5d 100644 (file)
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -199,7 +199,6 @@ typedef struct DisasContext {
     int spe_enabled;
     ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
     int singlestep_enabled;
-    int dcache_line_size;
 } DisasContext;
 
 struct opc_handler_t {
@@ -4142,95 +4141,27 @@ GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE)
 }
 
 /* dcbz */
-#define op_dcbz(n) (*gen_op_dcbz[n][ctx->mem_idx])()
-static GenOpFunc *gen_op_dcbz[4][NB_MEM_FUNCS] = {
-    /* 32 bytes cache line size */
-    {
-#define gen_op_dcbz_l32_le_raw        gen_op_dcbz_l32_raw
-#define gen_op_dcbz_l32_le_user       gen_op_dcbz_l32_user
-#define gen_op_dcbz_l32_le_kernel     gen_op_dcbz_l32_kernel
-#define gen_op_dcbz_l32_le_hypv       gen_op_dcbz_l32_hypv
-#define gen_op_dcbz_l32_le_64_raw     gen_op_dcbz_l32_64_raw
-#define gen_op_dcbz_l32_le_64_user    gen_op_dcbz_l32_64_user
-#define gen_op_dcbz_l32_le_64_kernel  gen_op_dcbz_l32_64_kernel
-#define gen_op_dcbz_l32_le_64_hypv    gen_op_dcbz_l32_64_hypv
-        GEN_MEM_FUNCS(dcbz_l32),
-    },
-    /* 64 bytes cache line size */
-    {
-#define gen_op_dcbz_l64_le_raw        gen_op_dcbz_l64_raw
-#define gen_op_dcbz_l64_le_user       gen_op_dcbz_l64_user
-#define gen_op_dcbz_l64_le_kernel     gen_op_dcbz_l64_kernel
-#define gen_op_dcbz_l64_le_hypv       gen_op_dcbz_l64_hypv
-#define gen_op_dcbz_l64_le_64_raw     gen_op_dcbz_l64_64_raw
-#define gen_op_dcbz_l64_le_64_user    gen_op_dcbz_l64_64_user
-#define gen_op_dcbz_l64_le_64_kernel  gen_op_dcbz_l64_64_kernel
-#define gen_op_dcbz_l64_le_64_hypv    gen_op_dcbz_l64_64_hypv
-        GEN_MEM_FUNCS(dcbz_l64),
-    },
-    /* 128 bytes cache line size */
-    {
-#define gen_op_dcbz_l128_le_raw       gen_op_dcbz_l128_raw
-#define gen_op_dcbz_l128_le_user      gen_op_dcbz_l128_user
-#define gen_op_dcbz_l128_le_kernel    gen_op_dcbz_l128_kernel
-#define gen_op_dcbz_l128_le_hypv      gen_op_dcbz_l128_hypv
-#define gen_op_dcbz_l128_le_64_raw    gen_op_dcbz_l128_64_raw
-#define gen_op_dcbz_l128_le_64_user   gen_op_dcbz_l128_64_user
-#define gen_op_dcbz_l128_le_64_kernel gen_op_dcbz_l128_64_kernel
-#define gen_op_dcbz_l128_le_64_hypv   gen_op_dcbz_l128_64_hypv
-        GEN_MEM_FUNCS(dcbz_l128),
-    },
-    /* tunable cache line size */
-    {
-#define gen_op_dcbz_le_raw            gen_op_dcbz_raw
-#define gen_op_dcbz_le_user           gen_op_dcbz_user
-#define gen_op_dcbz_le_kernel         gen_op_dcbz_kernel
-#define gen_op_dcbz_le_hypv           gen_op_dcbz_hypv
-#define gen_op_dcbz_le_64_raw         gen_op_dcbz_64_raw
-#define gen_op_dcbz_le_64_user        gen_op_dcbz_64_user
-#define gen_op_dcbz_le_64_kernel      gen_op_dcbz_64_kernel
-#define gen_op_dcbz_le_64_hypv        gen_op_dcbz_64_hypv
-        GEN_MEM_FUNCS(dcbz),
-    },
-};
-
-static always_inline void handler_dcbz (DisasContext *ctx,
-                                        int dcache_line_size)
-{
-    int n;
-
-    switch (dcache_line_size) {
-    case 32:
-        n = 0;
-        break;
-    case 64:
-        n = 1;
-        break;
-    case 128:
-        n = 2;
-        break;
-    default:
-        n = 3;
-        break;
-    }
-    op_dcbz(n);
-}
-
 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ)
 {
-    gen_addr_reg_index(cpu_T[0], ctx);
-    handler_dcbz(ctx, ctx->dcache_line_size);
-    gen_op_check_reservation();
+    TCGv t0 = tcg_temp_new();
+    gen_addr_reg_index(t0, ctx);
+    /* NIP cannot be restored if the memory exception comes from an helper */
+    gen_update_nip(ctx, ctx->nip - 4);
+    gen_helper_dcbz(t0);
+    tcg_temp_free(t0);
 }
 
 GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT)
 {
-    gen_addr_reg_index(cpu_T[0], ctx);
+    TCGv t0 = tcg_temp_new();
+    gen_addr_reg_index(t0, ctx);
+    /* NIP cannot be restored if the memory exception comes from an helper */
+    gen_update_nip(ctx, ctx->nip - 4);
     if (ctx->opcode & 0x00200000)
-        handler_dcbz(ctx, ctx->dcache_line_size);
+        gen_helper_dcbz(t0);
     else
-        handler_dcbz(ctx, -1);
-    gen_op_check_reservation();
+        gen_helper_dcbz_970(t0);
+    tcg_temp_free(t0);
 }
 
 /* icbi */
@@ -7563,7 +7494,6 @@ static always_inline void gen_intermediate_code_internal (CPUState *env,
 #else
     ctx.mem_idx = (supervisor << 1) | little_endian;
 #endif
-    ctx.dcache_line_size = env->dcache_line_size;
     ctx.fpu_enabled = msr_fp;
     if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
         ctx.spe_enabled = msr_spe;