done_init = 1;
}
-static always_inline void gen_excp (DisasContext *ctx,
- int exception, int error_code)
+static inline void gen_excp(DisasContext *ctx, int exception, int error_code)
{
TCGv_i32 tmp1, tmp2;
tcg_temp_free_i32(tmp1);
}
-static always_inline void gen_invalid (DisasContext *ctx)
+static inline void gen_invalid(DisasContext *ctx)
{
gen_excp(ctx, EXCP_OPCDEC, 0);
}
-static always_inline void gen_qemu_ldf (TCGv t0, TCGv t1, int flags)
+static inline void gen_qemu_ldf(TCGv t0, TCGv t1, int flags)
{
TCGv tmp = tcg_temp_new();
TCGv_i32 tmp32 = tcg_temp_new_i32();
tcg_temp_free(tmp);
}
-static always_inline void gen_qemu_ldg (TCGv t0, TCGv t1, int flags)
+static inline void gen_qemu_ldg(TCGv t0, TCGv t1, int flags)
{
TCGv tmp = tcg_temp_new();
tcg_gen_qemu_ld64(tmp, t1, flags);
tcg_temp_free(tmp);
}
-static always_inline void gen_qemu_lds (TCGv t0, TCGv t1, int flags)
+static inline void gen_qemu_lds(TCGv t0, TCGv t1, int flags)
{
TCGv tmp = tcg_temp_new();
TCGv_i32 tmp32 = tcg_temp_new_i32();
tcg_temp_free(tmp);
}
-static always_inline void gen_qemu_ldl_l (TCGv t0, TCGv t1, int flags)
+static inline void gen_qemu_ldl_l(TCGv t0, TCGv t1, int flags)
{
tcg_gen_mov_i64(cpu_lock, t1);
tcg_gen_qemu_ld32s(t0, t1, flags);
}
-static always_inline void gen_qemu_ldq_l (TCGv t0, TCGv t1, int flags)
+static inline void gen_qemu_ldq_l(TCGv t0, TCGv t1, int flags)
{
tcg_gen_mov_i64(cpu_lock, t1);
tcg_gen_qemu_ld64(t0, t1, flags);
}
-static always_inline void gen_load_mem (DisasContext *ctx,
- void (*tcg_gen_qemu_load)(TCGv t0, TCGv t1, int flags),
- int ra, int rb, int32_t disp16,
- int fp, int clear)
+static inline void gen_load_mem(DisasContext *ctx,
+ void (*tcg_gen_qemu_load)(TCGv t0, TCGv t1,
+ int flags),
+ int ra, int rb, int32_t disp16, int fp,
+ int clear)
{
TCGv addr;
tcg_temp_free(addr);
}
-static always_inline void gen_qemu_stf (TCGv t0, TCGv t1, int flags)
+static inline void gen_qemu_stf(TCGv t0, TCGv t1, int flags)
{
TCGv_i32 tmp32 = tcg_temp_new_i32();
TCGv tmp = tcg_temp_new();
tcg_temp_free_i32(tmp32);
}
-static always_inline void gen_qemu_stg (TCGv t0, TCGv t1, int flags)
+static inline void gen_qemu_stg(TCGv t0, TCGv t1, int flags)
{
TCGv tmp = tcg_temp_new();
gen_helper_g_to_memory(tmp, t0);
tcg_temp_free(tmp);
}
-static always_inline void gen_qemu_sts (TCGv t0, TCGv t1, int flags)
+static inline void gen_qemu_sts(TCGv t0, TCGv t1, int flags)
{
TCGv_i32 tmp32 = tcg_temp_new_i32();
TCGv tmp = tcg_temp_new();
tcg_temp_free_i32(tmp32);
}
-static always_inline void gen_qemu_stl_c (TCGv t0, TCGv t1, int flags)
+static inline void gen_qemu_stl_c(TCGv t0, TCGv t1, int flags)
{
int l1, l2;
tcg_gen_movi_i64(cpu_lock, -1);
}
-static always_inline void gen_qemu_stq_c (TCGv t0, TCGv t1, int flags)
+static inline void gen_qemu_stq_c(TCGv t0, TCGv t1, int flags)
{
int l1, l2;
tcg_gen_movi_i64(cpu_lock, -1);
}
-static always_inline void gen_store_mem (DisasContext *ctx,
- void (*tcg_gen_qemu_store)(TCGv t0, TCGv t1, int flags),
- int ra, int rb, int32_t disp16,
- int fp, int clear, int local)
+static inline void gen_store_mem(DisasContext *ctx,
+ void (*tcg_gen_qemu_store)(TCGv t0, TCGv t1,
+ int flags),
+ int ra, int rb, int32_t disp16, int fp,
+ int clear, int local)
{
TCGv addr;
if (local)
tcg_temp_free(addr);
}
-static always_inline void gen_bcond (DisasContext *ctx,
- TCGCond cond,
- int ra, int32_t disp, int mask)
+static inline void gen_bcond(DisasContext *ctx, TCGCond cond, int ra,
+ int32_t disp, int mask)
{
int l1, l2;
gen_set_label(l2);
}
-static always_inline void gen_fbcond (DisasContext *ctx, int opc,
- int ra, int32_t disp16)
+static inline void gen_fbcond(DisasContext *ctx, int opc, int ra,
+ int32_t disp16)
{
int l1, l2;
TCGv tmp;
gen_set_label(l2);
}
-static always_inline void gen_cmov (TCGCond inv_cond,
- int ra, int rb, int rc,
- int islit, uint8_t lit, int mask)
+static inline void gen_cmov(TCGCond inv_cond, int ra, int rb, int rc,
+ int islit, uint8_t lit, int mask)
{
int l1;
}
#define FARITH2(name) \
-static always_inline void glue(gen_f, name)(int rb, int rc) \
+static inline void glue(gen_f, name)(int rb, int rc) \
{ \
if (unlikely(rc == 31)) \
return; \
FARITH2(cvtqlsv)
#define FARITH3(name) \
-static always_inline void glue(gen_f, name) (int ra, int rb, int rc) \
+static inline void glue(gen_f, name)(int ra, int rb, int rc) \
{ \
if (unlikely(rc == 31)) \
return; \
FARITH3(cpyse)
#define FCMOV(name) \
-static always_inline void glue(gen_f, name) (int ra, int rb, int rc) \
+static inline void glue(gen_f, name)(int ra, int rb, int rc) \
{ \
int l1; \
TCGv tmp; \
FCMOV(cmpfgt)
/* EXTWH, EXTWH, EXTLH, EXTQH */
-static always_inline void gen_ext_h(void (*tcg_gen_ext_i64)(TCGv t0, TCGv t1),
- int ra, int rb, int rc,
- int islit, uint8_t lit)
+static inline void gen_ext_h(void(*tcg_gen_ext_i64)(TCGv t0, TCGv t1),
+ int ra, int rb, int rc, int islit, uint8_t lit)
{
if (unlikely(rc == 31))
return;
}
/* EXTBL, EXTWL, EXTWL, EXTLL, EXTQL */
-static always_inline void gen_ext_l(void (*tcg_gen_ext_i64)(TCGv t0, TCGv t1),
- int ra, int rb, int rc,
- int islit, uint8_t lit)
+static inline void gen_ext_l(void(*tcg_gen_ext_i64)(TCGv t0, TCGv t1),
+ int ra, int rb, int rc, int islit, uint8_t lit)
{
if (unlikely(rc == 31))
return;
/* Code to call arith3 helpers */
#define ARITH3(name) \
-static always_inline void glue(gen_, name) (int ra, int rb, int rc, \
- int islit, uint8_t lit) \
+static inline void glue(gen_, name)(int ra, int rb, int rc, int islit,\
+ uint8_t lit) \
{ \
if (unlikely(rc == 31)) \
return; \
ARITH3(mullv)
ARITH3(mulqv)
-static always_inline void gen_cmp(TCGCond cond,
- int ra, int rb, int rc,
- int islit, uint8_t lit)
+static inline void gen_cmp(TCGCond cond, int ra, int rb, int rc, int islit,
+ uint8_t lit)
{
int l1, l2;
TCGv tmp;
gen_set_label(l2);
}
-static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
+static inline int translate_one(DisasContext *ctx, uint32_t insn)
{
uint32_t palcode;
int32_t disp21, disp16, disp12;
return ret;
}
-static always_inline void gen_intermediate_code_internal (CPUState *env,
- TranslationBlock *tb,
- int search_pc)
+static inline void gen_intermediate_code_internal(CPUState *env,
+ TranslationBlock *tb,
+ int search_pc)
{
#if defined ALPHA_DEBUG_DISAS
static int insn_count;
#else
/* Common routines used by software and hardware TLBs emulation */
-static always_inline int pte_is_valid (target_ulong pte0)
+static inline int pte_is_valid(target_ulong pte0)
{
return pte0 & 0x80000000 ? 1 : 0;
}
-static always_inline void pte_invalidate (target_ulong *pte0)
+static inline void pte_invalidate(target_ulong *pte0)
{
*pte0 &= ~0x80000000;
}
#if defined(TARGET_PPC64)
-static always_inline int pte64_is_valid (target_ulong pte0)
+static inline int pte64_is_valid(target_ulong pte0)
{
return pte0 & 0x0000000000000001ULL ? 1 : 0;
}
-static always_inline void pte64_invalidate (target_ulong *pte0)
+static inline void pte64_invalidate(target_ulong *pte0)
{
*pte0 &= ~0x0000000000000001ULL;
}
#define PTE64_CHECK_MASK (TARGET_PAGE_MASK | 0x7F)
#endif
-static always_inline int pp_check (int key, int pp, int nx)
+static inline int pp_check(int key, int pp, int nx)
{
int access;
return access;
}
-static always_inline int check_prot (int prot, int rw, int access_type)
+static inline int check_prot(int prot, int rw, int access_type)
{
int ret;
return ret;
}
-static always_inline int _pte_check (mmu_ctx_t *ctx, int is_64b,
- target_ulong pte0, target_ulong pte1,
- int h, int rw, int type)
+static inline int _pte_check(mmu_ctx_t *ctx, int is_64b, target_ulong pte0,
+ target_ulong pte1, int h, int rw, int type)
{
target_ulong ptem, mmask;
int access, ret, pteh, ptev, pp;
return ret;
}
-static always_inline int pte32_check (mmu_ctx_t *ctx,
- target_ulong pte0, target_ulong pte1,
- int h, int rw, int type)
+static inline int pte32_check(mmu_ctx_t *ctx, target_ulong pte0,
+ target_ulong pte1, int h, int rw, int type)
{
return _pte_check(ctx, 0, pte0, pte1, h, rw, type);
}
#if defined(TARGET_PPC64)
-static always_inline int pte64_check (mmu_ctx_t *ctx,
- target_ulong pte0, target_ulong pte1,
- int h, int rw, int type)
+static inline int pte64_check(mmu_ctx_t *ctx, target_ulong pte0,
+ target_ulong pte1, int h, int rw, int type)
{
return _pte_check(ctx, 1, pte0, pte1, h, rw, type);
}
#endif
-static always_inline int pte_update_flags (mmu_ctx_t *ctx, target_ulong *pte1p,
- int ret, int rw)
+static inline int pte_update_flags(mmu_ctx_t *ctx, target_ulong *pte1p,
+ int ret, int rw)
{
int store = 0;
}
/* Software driven TLB helpers */
-static always_inline int ppc6xx_tlb_getnum (CPUState *env, target_ulong eaddr,
- int way, int is_code)
+static inline int ppc6xx_tlb_getnum(CPUState *env, target_ulong eaddr, int way,
+ int is_code)
{
int nr;
return nr;
}
-static always_inline void ppc6xx_tlb_invalidate_all (CPUState *env)
+static inline void ppc6xx_tlb_invalidate_all(CPUState *env)
{
ppc6xx_tlb_t *tlb;
int nr, max;
tlb_flush(env, 1);
}
-static always_inline void __ppc6xx_tlb_invalidate_virt (CPUState *env,
- target_ulong eaddr,
- int is_code,
- int match_epn)
+static inline void __ppc6xx_tlb_invalidate_virt(CPUState *env,
+ target_ulong eaddr,
+ int is_code, int match_epn)
{
#if !defined(FLUSH_ALL_TLBS)
ppc6xx_tlb_t *tlb;
#endif
}
-static always_inline void ppc6xx_tlb_invalidate_virt (CPUState *env,
- target_ulong eaddr,
- int is_code)
+static inline void ppc6xx_tlb_invalidate_virt(CPUState *env,
+ target_ulong eaddr, int is_code)
{
__ppc6xx_tlb_invalidate_virt(env, eaddr, is_code, 0);
}
env->last_way = way;
}
-static always_inline int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx,
- target_ulong eaddr, int rw,
- int access_type)
+static inline int ppc6xx_tlb_check(CPUState *env, mmu_ctx_t *ctx,
+ target_ulong eaddr, int rw, int access_type)
{
ppc6xx_tlb_t *tlb;
int nr, best, way;
}
/* Perform BAT hit & translation */
-static always_inline void bat_size_prot (CPUState *env, target_ulong *blp,
- int *validp, int *protp,
- target_ulong *BATu, target_ulong *BATl)
+static inline void bat_size_prot(CPUState *env, target_ulong *blp, int *validp,
+ int *protp, target_ulong *BATu,
+ target_ulong *BATl)
{
target_ulong bl;
int pp, valid, prot;
*protp = prot;
}
-static always_inline void bat_601_size_prot (CPUState *env,target_ulong *blp,
- int *validp, int *protp,
- target_ulong *BATu,
- target_ulong *BATl)
+static inline void bat_601_size_prot(CPUState *env, target_ulong *blp,
+ int *validp, int *protp,
+ target_ulong *BATu, target_ulong *BATl)
{
target_ulong bl;
int key, pp, valid, prot;
*protp = prot;
}
-static always_inline int get_bat (CPUState *env, mmu_ctx_t *ctx,
- target_ulong virtual, int rw, int type)
+static inline int get_bat(CPUState *env, mmu_ctx_t *ctx, target_ulong virtual,
+ int rw, int type)
{
target_ulong *BATlt, *BATut, *BATu, *BATl;
target_ulong base, BEPIl, BEPIu, bl;
}
/* PTE table lookup */
-static always_inline int _find_pte (mmu_ctx_t *ctx, int is_64b, int h,
- int rw, int type,
- int target_page_bits)
+static inline int _find_pte(mmu_ctx_t *ctx, int is_64b, int h, int rw,
+ int type, int target_page_bits)
{
target_ulong base, pte0, pte1;
int i, good = -1;
return ret;
}
-static always_inline int find_pte32 (mmu_ctx_t *ctx, int h, int rw,
- int type, int target_page_bits)
+static inline int find_pte32(mmu_ctx_t *ctx, int h, int rw, int type,
+ int target_page_bits)
{
return _find_pte(ctx, 0, h, rw, type, target_page_bits);
}
#if defined(TARGET_PPC64)
-static always_inline int find_pte64 (mmu_ctx_t *ctx, int h, int rw,
- int type, int target_page_bits)
+static inline int find_pte64(mmu_ctx_t *ctx, int h, int rw, int type,
+ int target_page_bits)
{
return _find_pte(ctx, 1, h, rw, type, target_page_bits);
}
#endif
-static always_inline int find_pte (CPUState *env, mmu_ctx_t *ctx,
- int h, int rw, int type,
- int target_page_bits)
+static inline int find_pte(CPUState *env, mmu_ctx_t *ctx, int h, int rw,
+ int type, int target_page_bits)
{
#if defined(TARGET_PPC64)
if (env->mmu_model & POWERPC_MMU_64)
entry->tmp = slb->tmp;
}
-static always_inline int slb_is_valid (ppc_slb_t *slb)
+static inline int slb_is_valid(ppc_slb_t *slb)
{
return (int)(slb->tmp64 & 0x0000000008000000ULL);
}
-static always_inline void slb_invalidate (ppc_slb_t *slb)
+static inline void slb_invalidate(ppc_slb_t *slb)
{
slb->tmp64 &= ~0x0000000008000000ULL;
}
-static always_inline int slb_lookup (CPUPPCState *env, target_ulong eaddr,
- target_ulong *vsid,
- target_ulong *page_mask, int *attr,
- int *target_page_bits)
+static inline int slb_lookup(CPUPPCState *env, target_ulong eaddr,
+ target_ulong *vsid, target_ulong *page_mask,
+ int *attr, int *target_page_bits)
{
target_ulong mask;
int n, ret;
#endif /* defined(TARGET_PPC64) */
/* Perform segment based translation */
-static always_inline target_phys_addr_t get_pgaddr (target_phys_addr_t sdr1,
- int sdr_sh,
- target_phys_addr_t hash,
- target_phys_addr_t mask)
+static inline target_phys_addr_t get_pgaddr(target_phys_addr_t sdr1,
+ int sdr_sh,
+ target_phys_addr_t hash,
+ target_phys_addr_t mask)
{
return (sdr1 & ((target_phys_addr_t)(-1ULL) << sdr_sh)) | (hash & mask);
}
-static always_inline int get_segment (CPUState *env, mmu_ctx_t *ctx,
- target_ulong eaddr, int rw, int type)
+static inline int get_segment(CPUState *env, mmu_ctx_t *ctx,
+ target_ulong eaddr, int rw, int type)
{
target_phys_addr_t sdr, hash, mask, sdr_mask, htab_mask;
target_ulong sr, vsid, vsid_mask, pgidx, page_mask;
}
/* Generic TLB check function for embedded PowerPC implementations */
-static always_inline int ppcemb_tlb_check (CPUState *env, ppcemb_tlb_t *tlb,
- target_phys_addr_t *raddrp,
- target_ulong address,
- uint32_t pid, int ext, int i)
+static inline int ppcemb_tlb_check(CPUState *env, ppcemb_tlb_t *tlb,
+ target_phys_addr_t *raddrp,
+ target_ulong address, uint32_t pid, int ext,
+ int i)
{
target_ulong mask;
}
/* Helpers specific to PowerPC 40x implementations */
-static always_inline void ppc4xx_tlb_invalidate_all (CPUState *env)
+static inline void ppc4xx_tlb_invalidate_all(CPUState *env)
{
ppcemb_tlb_t *tlb;
int i;
tlb_flush(env, 1);
}
-static always_inline void ppc4xx_tlb_invalidate_virt (CPUState *env,
- target_ulong eaddr,
- uint32_t pid)
+static inline void ppc4xx_tlb_invalidate_virt(CPUState *env,
+ target_ulong eaddr, uint32_t pid)
{
#if !defined(FLUSH_ALL_TLBS)
ppcemb_tlb_t *tlb;
return ret;
}
-static always_inline int check_physical (CPUState *env, mmu_ctx_t *ctx,
- target_ulong eaddr, int rw)
+static inline int check_physical(CPUState *env, mmu_ctx_t *ctx,
+ target_ulong eaddr, int rw)
{
int in_plb, ret;
/*****************************************************************************/
/* BATs management */
#if !defined(FLUSH_ALL_TLBS)
-static always_inline void do_invalidate_BAT (CPUPPCState *env,
- target_ulong BATu,
- target_ulong mask)
+static inline void do_invalidate_BAT(CPUPPCState *env, target_ulong BATu,
+ target_ulong mask)
{
target_ulong base, end, page;
}
#endif
-static always_inline void dump_store_bat (CPUPPCState *env, char ID,
- int ul, int nr, target_ulong value)
+static inline void dump_store_bat(CPUPPCState *env, char ID, int ul, int nr,
+ target_ulong value)
{
LOG_BATS("Set %cBAT%d%c to " ADDRX " (" ADDRX ")\n",
ID, nr, ul == 0 ? 'u' : 'l', value, env->nip);
env->error_code = 0;
}
#else /* defined (CONFIG_USER_ONLY) */
-static always_inline void dump_syscall (CPUState *env)
+static inline void dump_syscall(CPUState *env)
{
qemu_log_mask(CPU_LOG_INT, "syscall r0=" REGX " r3=" REGX " r4=" REGX
" r5=" REGX " r6=" REGX " nip=" ADDRX "\n",
/* Note that this function should be greatly optimized
* when called with a constant excp, from ppc_hw_interrupt
*/
-static always_inline void powerpc_excp (CPUState *env,
- int excp_model, int excp)
+static inline void powerpc_excp(CPUState *env, int excp_model, int excp)
{
target_ulong msr, new_msr, vector;
int srr0, srr1, asrr0, asrr1;
#endif
};
-static always_inline void gen_reset_fpstatus (void)
+static inline void gen_reset_fpstatus(void)
{
#ifdef CONFIG_SOFTFLOAT
gen_helper_reset_fpstatus();
#endif
}
-static always_inline void gen_compute_fprf (TCGv_i64 arg, int set_fprf, int set_rc)
+static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
{
TCGv_i32 t0 = tcg_temp_new_i32();
tcg_temp_free_i32(t0);
}
-static always_inline void gen_set_access_type (DisasContext *ctx, int access_type)
+static inline void gen_set_access_type(DisasContext *ctx, int access_type)
{
if (ctx->access_type != access_type) {
tcg_gen_movi_i32(cpu_access_type, access_type);
}
}
-static always_inline void gen_update_nip (DisasContext *ctx, target_ulong nip)
+static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
{
#if defined(TARGET_PPC64)
if (ctx->sf_mode)
tcg_gen_movi_tl(cpu_nip, (uint32_t)nip);
}
-static always_inline void gen_exception_err (DisasContext *ctx, uint32_t excp, uint32_t error)
+static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
{
TCGv_i32 t0, t1;
if (ctx->exception == POWERPC_EXCP_NONE) {
ctx->exception = (excp);
}
-static always_inline void gen_exception (DisasContext *ctx, uint32_t excp)
+static inline void gen_exception(DisasContext *ctx, uint32_t excp)
{
TCGv_i32 t0;
if (ctx->exception == POWERPC_EXCP_NONE) {
ctx->exception = (excp);
}
-static always_inline void gen_debug_exception (DisasContext *ctx)
+static inline void gen_debug_exception(DisasContext *ctx)
{
TCGv_i32 t0;
tcg_temp_free_i32(t0);
}
-static always_inline void gen_inval_exception (DisasContext *ctx, uint32_t error)
+static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
{
gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
}
/* Stop translation */
-static always_inline void gen_stop_exception (DisasContext *ctx)
+static inline void gen_stop_exception(DisasContext *ctx)
{
gen_update_nip(ctx, ctx->nip);
ctx->exception = POWERPC_EXCP_STOP;
}
/* No need to update nip here, as execution flow will change */
-static always_inline void gen_sync_exception (DisasContext *ctx)
+static inline void gen_sync_exception(DisasContext *ctx)
{
ctx->exception = POWERPC_EXCP_SYNC;
}
/*****************************************************************************/
/*** Instruction decoding ***/
#define EXTRACT_HELPER(name, shift, nb) \
-static always_inline uint32_t name (uint32_t opcode) \
+static inline uint32_t name(uint32_t opcode) \
{ \
return (opcode >> (shift)) & ((1 << (nb)) - 1); \
}
#define EXTRACT_SHELPER(name, shift, nb) \
-static always_inline int32_t name (uint32_t opcode) \
+static inline int32_t name(uint32_t opcode) \
{ \
return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
}
EXTRACT_HELPER(crbB, 11, 5);
/* SPR / TBL */
EXTRACT_HELPER(_SPR, 11, 10);
-static always_inline uint32_t SPR (uint32_t opcode)
+static inline uint32_t SPR(uint32_t opcode)
{
uint32_t sprn = _SPR(opcode);
/* Displacement */
EXTRACT_SHELPER(d, 0, 16);
/* Immediate address */
-static always_inline target_ulong LI (uint32_t opcode)
+static inline target_ulong LI(uint32_t opcode)
{
return (opcode >> 0) & 0x03FFFFFC;
}
-static always_inline uint32_t BD (uint32_t opcode)
+static inline uint32_t BD(uint32_t opcode)
{
return (opcode >> 0) & 0xFFFC;
}
EXTRACT_HELPER(LK, 0, 1);
/* Create a mask between <start> and <end> bits */
-static always_inline target_ulong MASK (uint32_t start, uint32_t end)
+static inline target_ulong MASK(uint32_t start, uint32_t end)
{
target_ulong ret;
#endif
/* SPR load/store helpers */
-static always_inline void gen_load_spr(TCGv t, int reg)
+static inline void gen_load_spr(TCGv t, int reg)
{
tcg_gen_ld_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
}
-static always_inline void gen_store_spr(int reg, TCGv t)
+static inline void gen_store_spr(int reg, TCGv t)
{
tcg_gen_st_tl(t, cpu_env, offsetof(CPUState, spr[reg]));
}
/*** Integer comparison ***/
-static always_inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
+static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
{
int l1, l2, l3;
gen_set_label(l3);
}
-static always_inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
+static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
{
TCGv t0 = tcg_const_local_tl(arg1);
gen_op_cmp(arg0, t0, s, crf);
}
#if defined(TARGET_PPC64)
-static always_inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
+static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
{
TCGv t0, t1;
t0 = tcg_temp_local_new();
tcg_temp_free(t0);
}
-static always_inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
+static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
{
TCGv t0 = tcg_const_local_tl(arg1);
gen_op_cmp32(arg0, t0, s, crf);
}
#endif
-static always_inline void gen_set_Rc0 (DisasContext *ctx, TCGv reg)
+static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
{
#if defined(TARGET_PPC64)
if (!(ctx->sf_mode))
/*** Integer arithmetic ***/
-static always_inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0, TCGv arg1, TCGv arg2, int sub)
+static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
+ TCGv arg1, TCGv arg2, int sub)
{
int l1;
TCGv t0;
tcg_temp_free(t0);
}
-static always_inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1, TCGv arg2, int sub)
+static inline void gen_op_arith_compute_ca(DisasContext *ctx, TCGv arg1,
+ TCGv arg2, int sub)
{
int l1 = gen_new_label();
}
/* Common add function */
-static always_inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
- int add_ca, int compute_ca, int compute_ov)
+static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
+ TCGv arg2, int add_ca, int compute_ca,
+ int compute_ov)
{
TCGv t0, t1;
}
}
/* addic addic.*/
-static always_inline void gen_op_addic (DisasContext *ctx, TCGv ret, TCGv arg1,
- int compute_Rc0)
+static inline void gen_op_addic(DisasContext *ctx, TCGv ret, TCGv arg1,
+ int compute_Rc0)
{
target_long simm = SIMM(ctx->opcode);
}
}
-static always_inline void gen_op_arith_divw (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
- int sign, int compute_ov)
+static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
+ TCGv arg2, int sign, int compute_ov)
{
int l1 = gen_new_label();
int l2 = gen_new_label();
GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
#if defined(TARGET_PPC64)
-static always_inline void gen_op_arith_divd (DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
- int sign, int compute_ov)
+static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
+ TCGv arg2, int sign, int compute_ov)
{
int l1 = gen_new_label();
int l2 = gen_new_label();
#endif
/* neg neg. nego nego. */
-static always_inline void gen_op_arith_neg (DisasContext *ctx, TCGv ret, TCGv arg1, int ov_check)
+static inline void gen_op_arith_neg(DisasContext *ctx, TCGv ret, TCGv arg1,
+ int ov_check)
{
int l1 = gen_new_label();
int l2 = gen_new_label();
}
/* Common subf function */
-static always_inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2,
- int add_ca, int compute_ca, int compute_ov)
+static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
+ TCGv arg2, int add_ca, int compute_ca,
+ int compute_ov)
{
TCGv t0, t1;
gen_##name(ctx, 1, 1); \
}
-static always_inline void gen_rldinm (DisasContext *ctx, uint32_t mb,
- uint32_t me, uint32_t sh)
+static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
+ uint32_t sh)
{
if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
}
/* rldicl - rldicl. */
-static always_inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
+static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
{
uint32_t sh, mb;
}
GEN_PPC64_R4(rldicl, 0x1E, 0x00);
/* rldicr - rldicr. */
-static always_inline void gen_rldicr (DisasContext *ctx, int men, int shn)
+static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
{
uint32_t sh, me;
}
GEN_PPC64_R4(rldicr, 0x1E, 0x02);
/* rldic - rldic. */
-static always_inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
+static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
{
uint32_t sh, mb;
}
GEN_PPC64_R4(rldic, 0x1E, 0x04);
-static always_inline void gen_rldnm (DisasContext *ctx, uint32_t mb,
- uint32_t me)
+static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
{
TCGv t0;
}
/* rldcl - rldcl. */
-static always_inline void gen_rldcl (DisasContext *ctx, int mbn)
+static inline void gen_rldcl(DisasContext *ctx, int mbn)
{
uint32_t mb;
}
GEN_PPC64_R2(rldcl, 0x1E, 0x08);
/* rldcr - rldcr. */
-static always_inline void gen_rldcr (DisasContext *ctx, int men)
+static inline void gen_rldcr(DisasContext *ctx, int men)
{
uint32_t me;
}
GEN_PPC64_R2(rldcr, 0x1E, 0x09);
/* rldimi - rldimi. */
-static always_inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
+static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
{
uint32_t sh, mb, me;
gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
}
/* sradi & sradi. */
-static always_inline void gen_sradi (DisasContext *ctx, int n)
+static inline void gen_sradi(DisasContext *ctx, int n)
{
int sh = SH(ctx->opcode) + (n << 5);
if (sh != 0) {
/*** Addressing modes ***/
/* Register indirect with immediate index : EA = (rA|0) + SIMM */
-static always_inline void gen_addr_imm_index (DisasContext *ctx, TCGv EA, target_long maskl)
+static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
+ target_long maskl)
{
target_long simm = SIMM(ctx->opcode);
}
}
-static always_inline void gen_addr_reg_index (DisasContext *ctx, TCGv EA)
+static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
{
if (rA(ctx->opcode) == 0) {
#if defined(TARGET_PPC64)
}
}
-static always_inline void gen_addr_register (DisasContext *ctx, TCGv EA)
+static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
{
if (rA(ctx->opcode) == 0) {
tcg_gen_movi_tl(EA, 0);
}
}
-static always_inline void gen_addr_add (DisasContext *ctx, TCGv ret, TCGv arg1, target_long val)
+static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
+ target_long val)
{
tcg_gen_addi_tl(ret, arg1, val);
#if defined(TARGET_PPC64)
#endif
}
-static always_inline void gen_check_align (DisasContext *ctx, TCGv EA, int mask)
+static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
{
int l1 = gen_new_label();
TCGv t0 = tcg_temp_new();
}
/*** Integer load ***/
-static always_inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
+static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
{
tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
}
-static always_inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
+static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
{
tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
}
-static always_inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
+static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
{
tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
if (unlikely(ctx->le_mode)) {
}
}
-static always_inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
+static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
{
if (unlikely(ctx->le_mode)) {
tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
}
}
-static always_inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
+static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
{
tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
if (unlikely(ctx->le_mode)) {
}
#if defined(TARGET_PPC64)
-static always_inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
+static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
{
if (unlikely(ctx->le_mode)) {
tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
}
#endif
-static always_inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
+static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
{
tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
if (unlikely(ctx->le_mode)) {
}
}
-static always_inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
+static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
{
tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
}
-static always_inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
+static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
{
if (unlikely(ctx->le_mode)) {
TCGv t0 = tcg_temp_new();
}
}
-static always_inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
+static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
{
if (unlikely(ctx->le_mode)) {
TCGv t0 = tcg_temp_new();
}
}
-static always_inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
+static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
{
if (unlikely(ctx->le_mode)) {
TCGv_i64 t0 = tcg_temp_new_i64();
#endif
/*** Integer load and store with byte reverse ***/
/* lhbrx */
-static void always_inline gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
+static void inline gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
{
tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
if (likely(!ctx->le_mode)) {
GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
/* lwbrx */
-static void always_inline gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
+static void inline gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
{
tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
if (likely(!ctx->le_mode)) {
GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
/* sthbrx */
-static void always_inline gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
+static void inline gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
{
if (likely(!ctx->le_mode)) {
TCGv t0 = tcg_temp_new();
GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
/* stwbrx */
-static void always_inline gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
+static void inline gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
{
if (likely(!ctx->le_mode)) {
TCGv t0 = tcg_temp_new();
GEN_LDUXF(name, ldop, op | 0x01, type); \
GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
-static always_inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
+static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
{
TCGv t0 = tcg_temp_new();
TCGv_i32 t1 = tcg_temp_new_i32();
GEN_STUXF(name, stop, op | 0x01, type); \
GEN_STXF(name, stop, 0x17, op | 0x00, type)
-static always_inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
+static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
{
TCGv_i32 t0 = tcg_temp_new_i32();
TCGv t1 = tcg_temp_new();
GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
/* Optional: */
-static always_inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
+static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
{
TCGv t0 = tcg_temp_new();
tcg_gen_trunc_i64_tl(t0, arg1),
GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
/*** Branch ***/
-static always_inline void gen_goto_tb (DisasContext *ctx, int n,
- target_ulong dest)
+static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
{
TranslationBlock *tb;
tb = ctx->tb;
}
}
-static always_inline void gen_setlr (DisasContext *ctx, target_ulong nip)
+static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
{
#if defined(TARGET_PPC64)
if (ctx->sf_mode == 0)
#define BCOND_LR 1
#define BCOND_CTR 2
-static always_inline void gen_bcond (DisasContext *ctx, int type)
+static inline void gen_bcond(DisasContext *ctx, int type)
{
uint32_t bo = BO(ctx->opcode);
int l1 = gen_new_label();
#endif
/* mfspr */
-static always_inline void gen_op_mfspr (DisasContext *ctx)
+static inline void gen_op_mfspr(DisasContext *ctx)
{
void (*read_cb)(void *opaque, int gprn, int sprn);
uint32_t sprn = SPR(ctx->opcode);
}
/* All 405 MAC instructions are translated here */
-static always_inline void gen_405_mulladd_insn (DisasContext *ctx,
- int opc2, int opc3,
- int ra, int rb, int rt, int Rc)
+static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
+ int ra, int rb, int rt, int Rc)
{
TCGv t0, t1;
/*** Altivec vector extension ***/
/* Altivec registers moves */
-static always_inline TCGv_ptr gen_avr_ptr(int reg)
+static inline TCGv_ptr gen_avr_ptr(int reg)
{
TCGv_ptr r = tcg_temp_new_ptr();
tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
/*** SPE extension ***/
/* Register moves */
-static always_inline void gen_load_gpr64(TCGv_i64 t, int reg) {
+static inline void gen_load_gpr64(TCGv_i64 t, int reg)
+{
#if defined(TARGET_PPC64)
tcg_gen_mov_i64(t, cpu_gpr[reg]);
#else
#endif
}
-static always_inline void gen_store_gpr64(int reg, TCGv_i64 t) {
+static inline void gen_store_gpr64(int reg, TCGv_i64 t)
+{
#if defined(TARGET_PPC64)
tcg_gen_mov_i64(cpu_gpr[reg], t);
#else
}
/* Handler for undefined SPE opcodes */
-static always_inline void gen_speundef (DisasContext *ctx)
+static inline void gen_speundef(DisasContext *ctx)
{
gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
}
/* SPE logic */
#if defined(TARGET_PPC64)
#define GEN_SPEOP_LOGIC2(name, tcg_op) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \
}
#else
#define GEN_SPEOP_LOGIC2(name, tcg_op) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \
/* SPE logic immediate */
#if defined(TARGET_PPC64)
#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \
}
#else
#define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \
/* SPE arithmetic */
#if defined(TARGET_PPC64)
#define GEN_SPEOP_ARITH1(name, tcg_op) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \
}
#else
#define GEN_SPEOP_ARITH1(name, tcg_op) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \
}
#endif
-static always_inline void gen_op_evabs (TCGv_i32 ret, TCGv_i32 arg1)
+static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
{
int l1 = gen_new_label();
int l2 = gen_new_label();
GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
-static always_inline void gen_op_evrndw (TCGv_i32 ret, TCGv_i32 arg1)
+static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
{
tcg_gen_addi_i32(ret, arg1, 0x8000);
tcg_gen_ext16u_i32(ret, ret);
#if defined(TARGET_PPC64)
#define GEN_SPEOP_ARITH2(name, tcg_op) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \
}
#else
#define GEN_SPEOP_ARITH2(name, tcg_op) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \
}
#endif
-static always_inline void gen_op_evsrwu (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
+static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{
TCGv_i32 t0;
int l1, l2;
tcg_temp_free_i32(t0);
}
GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
-static always_inline void gen_op_evsrws (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
+static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{
TCGv_i32 t0;
int l1, l2;
tcg_temp_free_i32(t0);
}
GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
-static always_inline void gen_op_evslw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
+static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{
TCGv_i32 t0;
int l1, l2;
tcg_temp_free_i32(t0);
}
GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
-static always_inline void gen_op_evrlw (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
+static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{
TCGv_i32 t0 = tcg_temp_new_i32();
tcg_gen_andi_i32(t0, arg2, 0x1F);
tcg_temp_free_i32(t0);
}
GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
-static always_inline void gen_evmergehi (DisasContext *ctx)
+static inline void gen_evmergehi(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
gen_exception(ctx, POWERPC_EXCP_APU);
#endif
}
GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
-static always_inline void gen_op_evsubf (TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
+static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{
tcg_gen_sub_i32(ret, arg2, arg1);
}
/* SPE arithmetic immediate */
#if defined(TARGET_PPC64)
#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \
}
#else
#define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \
/* SPE comparison */
#if defined(TARGET_PPC64)
#define GEN_SPEOP_COMP(name, tcg_cond) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \
}
#else
#define GEN_SPEOP_COMP(name, tcg_cond) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \
GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
/* SPE misc */
-static always_inline void gen_brinc (DisasContext *ctx)
+static inline void gen_brinc(DisasContext *ctx)
{
/* Note: brinc is usable even if SPE is disabled */
gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
}
-static always_inline void gen_evmergelo (DisasContext *ctx)
+static inline void gen_evmergelo(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
gen_exception(ctx, POWERPC_EXCP_APU);
tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
#endif
}
-static always_inline void gen_evmergehilo (DisasContext *ctx)
+static inline void gen_evmergehilo(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
gen_exception(ctx, POWERPC_EXCP_APU);
tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
#endif
}
-static always_inline void gen_evmergelohi (DisasContext *ctx)
+static inline void gen_evmergelohi(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
gen_exception(ctx, POWERPC_EXCP_APU);
}
#endif
}
-static always_inline void gen_evsplati (DisasContext *ctx)
+static inline void gen_evsplati(DisasContext *ctx)
{
uint64_t imm = ((int32_t)(rA(ctx->opcode) << 11)) >> 27;
tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
#endif
}
-static always_inline void gen_evsplatfi (DisasContext *ctx)
+static inline void gen_evsplatfi(DisasContext *ctx)
{
uint64_t imm = rA(ctx->opcode) << 11;
#endif
}
-static always_inline void gen_evsel (DisasContext *ctx)
+static inline void gen_evsel(DisasContext *ctx)
{
int l1 = gen_new_label();
int l2 = gen_new_label();
GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, PPC_SPE); ////
/* SPE load and stores */
-static always_inline void gen_addr_spe_imm_index (DisasContext *ctx, TCGv EA, int sh)
+static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
{
target_ulong uimm = rB(ctx->opcode);
}
}
-static always_inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
+static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
{
#if defined(TARGET_PPC64)
gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
#endif
}
-static always_inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
+static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
{
#if defined(TARGET_PPC64)
TCGv t0 = tcg_temp_new();
#endif
}
-static always_inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
+static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
{
TCGv t0 = tcg_temp_new();
#if defined(TARGET_PPC64)
tcg_temp_free(t0);
}
-static always_inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
+static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
{
TCGv t0 = tcg_temp_new();
gen_qemu_ld16u(ctx, t0, addr);
tcg_temp_free(t0);
}
-static always_inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
+static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
{
TCGv t0 = tcg_temp_new();
gen_qemu_ld16u(ctx, t0, addr);
tcg_temp_free(t0);
}
-static always_inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
+static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
{
TCGv t0 = tcg_temp_new();
gen_qemu_ld16s(ctx, t0, addr);
tcg_temp_free(t0);
}
-static always_inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
+static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
{
TCGv t0 = tcg_temp_new();
#if defined(TARGET_PPC64)
tcg_temp_free(t0);
}
-static always_inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
+static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
{
#if defined(TARGET_PPC64)
TCGv t0 = tcg_temp_new();
#endif
}
-static always_inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
+static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
{
#if defined(TARGET_PPC64)
TCGv t0 = tcg_temp_new();
#endif
}
-static always_inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
+static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
{
TCGv t0 = tcg_temp_new();
gen_qemu_ld32u(ctx, t0, addr);
tcg_temp_free(t0);
}
-static always_inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
+static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
{
TCGv t0 = tcg_temp_new();
#if defined(TARGET_PPC64)
tcg_temp_free(t0);
}
-static always_inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
+static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
{
#if defined(TARGET_PPC64)
gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
#endif
}
-static always_inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
+static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
{
#if defined(TARGET_PPC64)
TCGv t0 = tcg_temp_new();
gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
}
-static always_inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
+static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
{
TCGv t0 = tcg_temp_new();
#if defined(TARGET_PPC64)
gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
}
-static always_inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
+static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
{
TCGv t0 = tcg_temp_new();
#if defined(TARGET_PPC64)
tcg_temp_free(t0);
}
-static always_inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
+static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
{
#if defined(TARGET_PPC64)
TCGv t0 = tcg_temp_new();
gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
}
-static always_inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
+static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
{
#if defined(TARGET_PPC64)
TCGv t0 = tcg_temp_new();
#endif
}
-static always_inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
+static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
{
gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
}
/*** SPE floating-point extension ***/
#if defined(TARGET_PPC64)
#define GEN_SPEFPUOP_CONV_32_32(name) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
TCGv_i32 t0; \
TCGv t1; \
tcg_temp_free(t1); \
}
#define GEN_SPEFPUOP_CONV_32_64(name) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
TCGv_i32 t0; \
TCGv t1; \
tcg_temp_free(t1); \
}
#define GEN_SPEFPUOP_CONV_64_32(name) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
TCGv_i32 t0 = tcg_temp_new_i32(); \
tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
tcg_temp_free_i32(t0); \
}
#define GEN_SPEFPUOP_CONV_64_64(name) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
}
#define GEN_SPEFPUOP_ARITH2_32_32(name) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
TCGv_i32 t0, t1; \
TCGv_i64 t2; \
tcg_temp_free(t2); \
}
#define GEN_SPEFPUOP_ARITH2_64_64(name) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \
cpu_gpr[rB(ctx->opcode)]); \
}
#define GEN_SPEFPUOP_COMP_32(name) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
TCGv_i32 t0, t1; \
if (unlikely(!ctx->spe_enabled)) { \
tcg_temp_free_i32(t1); \
}
#define GEN_SPEFPUOP_COMP_64(name) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \
}
#else
#define GEN_SPEFPUOP_CONV_32_32(name) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
}
#define GEN_SPEFPUOP_CONV_32_64(name) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
TCGv_i64 t0 = tcg_temp_new_i64(); \
gen_load_gpr64(t0, rB(ctx->opcode)); \
tcg_temp_free_i64(t0); \
}
#define GEN_SPEFPUOP_CONV_64_32(name) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
TCGv_i64 t0 = tcg_temp_new_i64(); \
gen_helper_##name(t0, cpu_gpr[rB(ctx->opcode)]); \
tcg_temp_free_i64(t0); \
}
#define GEN_SPEFPUOP_CONV_64_64(name) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
TCGv_i64 t0 = tcg_temp_new_i64(); \
gen_load_gpr64(t0, rB(ctx->opcode)); \
tcg_temp_free_i64(t0); \
}
#define GEN_SPEFPUOP_ARITH2_32_32(name) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \
cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
}
#define GEN_SPEFPUOP_ARITH2_64_64(name) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
TCGv_i64 t0, t1; \
if (unlikely(!ctx->spe_enabled)) { \
tcg_temp_free_i64(t1); \
}
#define GEN_SPEFPUOP_COMP_32(name) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
if (unlikely(!ctx->spe_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_APU); \
cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
}
#define GEN_SPEFPUOP_COMP_64(name) \
-static always_inline void gen_##name (DisasContext *ctx) \
+static inline void gen_##name(DisasContext *ctx) \
{ \
TCGv_i64 t0, t1; \
if (unlikely(!ctx->spe_enabled)) { \
GEN_SPEFPUOP_ARITH2_64_64(evfssub);
GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
-static always_inline void gen_evfsabs (DisasContext *ctx)
+static inline void gen_evfsabs(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
gen_exception(ctx, POWERPC_EXCP_APU);
tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
#endif
}
-static always_inline void gen_evfsnabs (DisasContext *ctx)
+static inline void gen_evfsnabs(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
gen_exception(ctx, POWERPC_EXCP_APU);
tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
#endif
}
-static always_inline void gen_evfsneg (DisasContext *ctx)
+static inline void gen_evfsneg(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
gen_exception(ctx, POWERPC_EXCP_APU);
GEN_SPEFPUOP_ARITH2_32_32(efssub);
GEN_SPEFPUOP_ARITH2_32_32(efsmul);
GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
-static always_inline void gen_efsabs (DisasContext *ctx)
+static inline void gen_efsabs(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
gen_exception(ctx, POWERPC_EXCP_APU);
}
tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
}
-static always_inline void gen_efsnabs (DisasContext *ctx)
+static inline void gen_efsnabs(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
gen_exception(ctx, POWERPC_EXCP_APU);
}
tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
}
-static always_inline void gen_efsneg (DisasContext *ctx)
+static inline void gen_efsneg(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
gen_exception(ctx, POWERPC_EXCP_APU);
GEN_SPEFPUOP_ARITH2_64_64(efdsub);
GEN_SPEFPUOP_ARITH2_64_64(efdmul);
GEN_SPEFPUOP_ARITH2_64_64(efddiv);
-static always_inline void gen_efdabs (DisasContext *ctx)
+static inline void gen_efdabs(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
gen_exception(ctx, POWERPC_EXCP_APU);
tcg_gen_andi_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
#endif
}
-static always_inline void gen_efdnabs (DisasContext *ctx)
+static inline void gen_efdnabs(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
gen_exception(ctx, POWERPC_EXCP_APU);
tcg_gen_ori_tl(cpu_gprh[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
#endif
}
-static always_inline void gen_efdneg (DisasContext *ctx)
+static inline void gen_efdneg(DisasContext *ctx)
{
if (unlikely(!ctx->spe_enabled)) {
gen_exception(ctx, POWERPC_EXCP_APU);
}
/*****************************************************************************/
-static always_inline void gen_intermediate_code_internal (CPUState *env,
- TranslationBlock *tb,
- int search_pc)
+static inline void gen_intermediate_code_internal(CPUState *env,
+ TranslationBlock *tb,
+ int search_pc)
{
DisasContext ctx, *ctxp = &ctx;
opc_handler_t **table, *handler;