target_phys_addr_t l3_base, DisplayState *ds,
qemu_irq irq, qemu_irq drq,
omap_clk fck1, omap_clk fck2, omap_clk ck54m,
- omap_clk ick1, omap_clk ick2);
+ omap_clk ick1, omap_clk ick2, int region_start);
void omap_rfbi_attach(struct omap_dss_s *s, int cs, struct rfbi_chip_s *chip);
void omap3_lcd_panel_attach(struct omap_dss_s *s, int cs, struct omap3_lcd_panel_s *lcd_panel);
void *omap3_lcd_panel_init(DisplayState *ds);
omap_findclk(s, "dss_clk1"), omap_findclk(s, "dss_clk2"),
omap_findclk(s, "dss_54m_clk"),
omap_findclk(s, "dss_l3_iclk"),
- omap_findclk(s, "dss_l4_iclk"));
+ omap_findclk(s, "dss_l4_iclk"),0);
omap_sti_init(omap_l4ta(s->l4, 18), 0x54000000,
s->irq[0][OMAP_INT_24XX_STI], omap_findclk(s, "emul_ck"),
s->dss = omap_dss_init(omap3_l4ta_get(s->l4, L4A_DSS), 0x68005400, ds,
s->irq[0][OMAP_INT_35XX_DSS_IRQ], s->drq[OMAP24XX_DMA_DSS],
- NULL,NULL,NULL,NULL,NULL);
+ NULL,NULL,NULL,NULL,NULL,1);
//gpio_clks[0] = NULL;
//gpio_clks[1] = NULL;
target_phys_addr_t l3_base, DisplayState *ds,
qemu_irq irq, qemu_irq drq,
omap_clk fck1, omap_clk fck2, omap_clk ck54m,
- omap_clk ick1, omap_clk ick2)
+ omap_clk ick1, omap_clk ick2, int region_base)
{
int iomemtype[6];
struct omap_dss_s *s = (struct omap_dss_s *)
iomemtype[4] = cpu_register_io_memory(0, omap_im3_readfn,
omap_im3_writefn, s);
/* TODO: DSI */
- omap_l4_attach(ta, 1, iomemtype[0]);
- omap_l4_attach(ta, 2, iomemtype[1]);
- omap_l4_attach(ta, 3, iomemtype[2]);
- omap_l4_attach(ta, 4, iomemtype[3]);
+ omap_l4_attach(ta, region_base+0, iomemtype[0]);
+ omap_l4_attach(ta, region_base+1, iomemtype[1]);
+ omap_l4_attach(ta, region_base+2, iomemtype[2]);
+ omap_l4_attach(ta, region_base+3, iomemtype[3]);
cpu_register_physical_memory(l3_base, 0x1000, iomemtype[4]);
return s;