case 0xad: /* POWER_SET */\r
case 0xae: /* POWER_CLR */\r
return s->reg_data[0xac];\r
- case 0xfe: /* PHY_CLK_CTRL */\r
case 0xfd: /* PHY_PWR_CTRL */\r
+ case 0xfe: /* PHY_CLK_CTRL */\r
return s->reg_data[addr];\r
+ case 0xff: /* PHY_CLK_CTRL */\r
+ return s->reg_data[0xfe] & 0x1;\r
default:\r
#ifdef VERBOSE\r
printf("%s: unknown register %02x pc %x \n", __FUNCTION__, addr,cpu_single_env->regs[15] );\r
case 0xae: /* POWER_CLEAR */\r
s->reg_data[0xac] = (s->reg_data[0xac] & ~value) & 0x20;\r
break;\r
- case 0xfe: /* PHY_CLK_CTRL */\r
- s->reg_data[addr] = value & 0x7;\r
- break;\r
case 0xfd: /* PHY_PWR_CTRL */\r
s->reg_data[addr] = value & 0x1;\r
break;\r
+ case 0xfe: /* PHY_CLK_CTRL */\r
+ s->reg_data[addr] = value & 0x7;\r
+ break;\r
default:\r
#ifdef VERBOSE\r
printf("%s: unknown register %02x pc %x \n", __FUNCTION__, addr,cpu_single_env->regs[15] );\r
struct twl4030_i2c_s *s = (struct twl4030_i2c_s *) opaque;\r
\r
switch (addr) {\r
+ case 0x98: /* GPIO_DATAIN1 */\r
+ case 0x99: /* GPIO_DATAIN2 */\r
+ case 0x9a: /* GPIO_DATAIN3 */\r
case 0x9b: /* GPIO_DATADIR1 */\r
+ case 0x9c: /* GPIO_DATADIR2 */\r
+ case 0x9d: /* GPIO_DATADIR3 */\r
case 0xb1: /* GPIO_ISR1A */\r
case 0xb2: /* GPIO_ISR2A */\r
case 0xb3: /* GPIO_ISR3A */\r
+ case 0xc0: /* GPIO_EDR1 */\r
+ case 0xc1: /* GPIO_EDR2 */\r
+ case 0xc2: /* GPIO_EDR3 */\r
+ case 0xc3: /* GPIO_EDR4 */\r
+ case 0xc4: /* GPIO_EDR5 */\r
return s->reg_data[addr];\r
default:\r
#ifdef VERBOSE\r
case 0xb6: /* GPIO_IMR3A */\r
s->reg_data[addr] = value & 0x03;\r
break;\r
+ case 0xc0: /* GPIO_EDR1 */\r
+ case 0xc1: /* GPIO_EDR2 */\r
+ case 0xc2: /* GPIO_EDR3 */\r
+ case 0xc3: /* GPIO_EDR4 */\r
+ case 0xc4: /* GPIO_EDR5 */\r
+ s->reg_data[addr] = value;\r
+ break;\r
case 0xc5: /* GPIO_SIH_CTRL */\r
s->reg_data[addr] = value & 0x07;\r
break;\r
struct twl4030_i2c_s *s = (struct twl4030_i2c_s *) opaque;\r
\r
switch (addr) {\r
+ case 0x1c: /* RTC */\r
+ case 0x1d:\r
+ case 0x1e:\r
+ case 0x1f:\r
+ case 0x20:\r
+ case 0x21:\r
+ case 0x22:\r
+ case 0x23:\r
+ case 0x24:\r
+ case 0x25:\r
+ case 0x26:\r
+ case 0x27:\r
+ case 0x28:\r
+ case 0x29:\r
+ case 0x2a:\r
+ case 0x2b:\r
+ case 0x2c:\r
+ case 0x2d: /*RTC end */\r
case 0x2e: /* PWR_ISR1 */\r
case 0x33: /* PWR_EDR1 */\r
case 0x34: /* PWR_EDR2 */\r
uint8_t seq_addr, seq_sub;\r
\r
switch (addr) {\r
+ case 0x29: /* RTC_CTRL_REG */\r
+ case 0x2a: /* RTC_STATUS_REG */\r
+ case 0x2b: /* RTC_INTERRUPTS_REG */\r
+ case 0x33: /* PWR_EDR1 */\r
+ case 0x34: /* PWR_EDR2 */\r
+ s->reg_data[addr] = value;\r
+ break;\r
case 0x46: /* P1_SW_EVENTS */\r
case 0x47: /* P2_SW_EVENTS */\r
case 0x48: /* P3_SW_EVENTS */\r