X-Git-Url: http://vcs.maemo.org/git/?a=blobdiff_plain;f=target-mips%2Ftranslate.c;h=719af3ae8f1e2de3f097e6f690a53c5d4b97401a;hb=d66846a14e191c75f4aa373623dd9a7aaa843ade;hp=e092439cfbfa8ccd7dec270685b0813f04cf739d;hpb=5e755519ac9d867f7da13f58a9d0c262db82e14c;p=qemu diff --git a/target-mips/translate.c b/target-mips/translate.c index e092439..719af3a 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -1,6 +1,6 @@ /* * MIPS32 emulation for qemu: main translation routines. - * + * * Copyright (c) 2004-2005 Jocelyn Mayer * Copyright (c) 2006 Marius Groeger (FPU operations) * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support) @@ -142,7 +142,7 @@ enum { OPC_SRL = 0x02 | OPC_SPECIAL, /* also ROTR */ OPC_SRA = 0x03 | OPC_SPECIAL, OPC_SLLV = 0x04 | OPC_SPECIAL, - OPC_SRLV = 0x06 | OPC_SPECIAL, + OPC_SRLV = 0x06 | OPC_SPECIAL, /* also ROTRV */ OPC_SRAV = 0x07 | OPC_SPECIAL, OPC_DSLLV = 0x14 | OPC_SPECIAL, OPC_DSRLV = 0x16 | OPC_SPECIAL, /* also DROTRV */ @@ -214,6 +214,26 @@ enum { OPC_SPECIAL3D_RESERVED = 0x3D | OPC_SPECIAL, }; +/* Multiplication variants of the vr54xx. */ +#define MASK_MUL_VR54XX(op) MASK_SPECIAL(op) | (op & (0x1F << 6)) + +enum { + OPC_VR54XX_MULS = (0x03 << 6) | OPC_MULT, + OPC_VR54XX_MULSU = (0x03 << 6) | OPC_MULTU, + OPC_VR54XX_MACC = (0x05 << 6) | OPC_MULT, + OPC_VR54XX_MACCU = (0x05 << 6) | OPC_MULTU, + OPC_VR54XX_MSAC = (0x07 << 6) | OPC_MULT, + OPC_VR54XX_MSACU = (0x07 << 6) | OPC_MULTU, + OPC_VR54XX_MULHI = (0x09 << 6) | OPC_MULT, + OPC_VR54XX_MULHIU = (0x09 << 6) | OPC_MULTU, + OPC_VR54XX_MULSHI = (0x0B << 6) | OPC_MULT, + OPC_VR54XX_MULSHIU = (0x0B << 6) | OPC_MULTU, + OPC_VR54XX_MACCHI = (0x0D << 6) | OPC_MULT, + OPC_VR54XX_MACCHIU = (0x0D << 6) | OPC_MULTU, + OPC_VR54XX_MSACHI = (0x0F << 6) | OPC_MULT, + OPC_VR54XX_MSACHIU = (0x0F << 6) | OPC_MULTU, +}; + /* REGIMM (rt field) opcodes */ #define MASK_REGIMM(op) MASK_OP_MAJOR(op) | (op & (0x1F << 16)) @@ -266,6 +286,8 @@ enum { OPC_DINSM = 0x05 | OPC_SPECIAL3, OPC_DINSU = 0x06 | OPC_SPECIAL3, OPC_DINS = 0x07 | OPC_SPECIAL3, + OPC_FORK = 0x08 | OPC_SPECIAL3, + OPC_YIELD = 0x09 | OPC_SPECIAL3, OPC_BSHFL = 0x20 | OPC_SPECIAL3, OPC_DBSHFL = 0x24 | OPC_SPECIAL3, OPC_RDHWR = 0x3B | OPC_SPECIAL3, @@ -296,8 +318,10 @@ enum { OPC_DMFC0 = (0x01 << 21) | OPC_CP0, OPC_MTC0 = (0x04 << 21) | OPC_CP0, OPC_DMTC0 = (0x05 << 21) | OPC_CP0, + OPC_MFTR = (0x08 << 21) | OPC_CP0, OPC_RDPGPR = (0x0A << 21) | OPC_CP0, OPC_MFMC0 = (0x0B << 21) | OPC_CP0, + OPC_MTTR = (0x0C << 21) | OPC_CP0, OPC_WRPGPR = (0x0E << 21) | OPC_CP0, OPC_C0 = (0x10 << 21) | OPC_CP0, OPC_C0_FIRST = (0x10 << 21) | OPC_CP0, @@ -308,6 +332,10 @@ enum { #define MASK_MFMC0(op) MASK_CP0(op) | (op & 0xFFFF) enum { + OPC_DMT = 0x01 | (0 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0, + OPC_EMT = 0x01 | (1 << 5) | (0x0F << 6) | (0x01 << 11) | OPC_MFMC0, + OPC_DVPE = 0x01 | (0 << 5) | OPC_MFMC0, + OPC_EVPE = 0x01 | (1 << 5) | OPC_MFMC0, OPC_DI = (0 << 5) | (0x0C << 11) | OPC_MFMC0, OPC_EI = (1 << 5) | (0x0C << 11) | OPC_MFMC0, }; @@ -428,7 +456,7 @@ NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \ NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \ NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \ }; \ -static inline void func(int n) \ +static always_inline void func(int n) \ { \ NAME ## _table[n](); \ } @@ -441,6 +469,10 @@ GEN32(gen_op_load_gpr_T2, gen_op_load_gpr_T2_gpr); GEN32(gen_op_store_T0_gpr, gen_op_store_T0_gpr_gpr); GEN32(gen_op_store_T1_gpr, gen_op_store_T1_gpr_gpr); +/* Moves to/from shadow registers */ +GEN32(gen_op_load_srsgpr_T0, gen_op_load_srsgpr_T0_gpr); +GEN32(gen_op_store_T0_srsgpr, gen_op_store_T0_srsgpr_gpr); + static const char *fregnames[] = { "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", @@ -458,7 +490,7 @@ NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \ NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \ NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \ }; \ -static inline void func(int n) \ +static always_inline void func(int n) \ { \ NAME ## _table[n](); \ } @@ -509,7 +541,7 @@ static GenOpFunc1 * gen_op_cmp ## type ## _ ## fmt ## _table[16] = { \ gen_op_cmp ## type ## _ ## fmt ## _le, \ gen_op_cmp ## type ## _ ## fmt ## _ngt, \ }; \ -static inline void gen_cmp ## type ## _ ## fmt(int n, long cc) \ +static always_inline void gen_cmp ## type ## _ ## fmt(int n, long cc) \ { \ gen_op_cmp ## type ## _ ## fmt ## _table[n](cc); \ } @@ -531,6 +563,8 @@ typedef struct DisasContext { uint32_t hflags, saved_hflags; int bstate; target_ulong btarget; + void *last_T0_store; + int last_T0_gpr; } DisasContext; enum { @@ -560,16 +594,46 @@ do { \ ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)); \ } while (0) -#define GEN_LOAD_REG_TN(Tn, Rn) \ +#define GEN_LOAD_REG_T0(Rn) \ +do { \ + if (Rn == 0) { \ + gen_op_reset_T0(); \ + } else { \ + if (ctx->glue(last_T0, _store) != gen_opc_ptr \ + || ctx->glue(last_T0, _gpr) != Rn) { \ + gen_op_load_gpr_T0(Rn); \ + } \ + } \ +} while (0) + +#define GEN_LOAD_REG_T1(Rn) \ +do { \ + if (Rn == 0) { \ + gen_op_reset_T1(); \ + } else { \ + gen_op_load_gpr_T1(Rn); \ + } \ +} while (0) + +#define GEN_LOAD_REG_T2(Rn) \ +do { \ + if (Rn == 0) { \ + gen_op_reset_T2(); \ + } else { \ + gen_op_load_gpr_T2(Rn); \ + } \ +} while (0) + +#define GEN_LOAD_SRSREG_TN(Tn, Rn) \ do { \ if (Rn == 0) { \ glue(gen_op_reset_, Tn)(); \ } else { \ - glue(gen_op_load_gpr_, Tn)(Rn); \ + glue(gen_op_load_srsgpr_, Tn)(Rn); \ } \ } while (0) -#ifdef TARGET_MIPS64 +#if defined(TARGET_MIPS64) #define GEN_LOAD_IMM_TN(Tn, Imm) \ do { \ if (Imm == 0) { \ @@ -591,10 +655,25 @@ do { \ } while (0) #endif -#define GEN_STORE_TN_REG(Rn, Tn) \ +#define GEN_STORE_T0_REG(Rn) \ +do { \ + if (Rn != 0) { \ + glue(gen_op_store_T0,_gpr)(Rn); \ + ctx->glue(last_T0,_store) = gen_opc_ptr; \ + ctx->glue(last_T0,_gpr) = Rn; \ + } \ +} while (0) + +#define GEN_STORE_T1_REG(Rn) \ +do { \ + if (Rn != 0) \ + glue(gen_op_store_T1,_gpr)(Rn); \ +} while (0) + +#define GEN_STORE_TN_SRSREG(Rn, Tn) \ do { \ if (Rn != 0) { \ - glue(glue(gen_op_store_, Tn),_gpr)(Rn); \ + glue(glue(gen_op_store_, Tn),_srsgpr)(Rn); \ } \ } while (0) @@ -608,9 +687,9 @@ do { \ glue(gen_op_store_fpr_, FTn)(Fn); \ } while (0) -static inline void gen_save_pc(target_ulong pc) +static always_inline void gen_save_pc(target_ulong pc) { -#ifdef TARGET_MIPS64 +#if defined(TARGET_MIPS64) if (pc == (int32_t)pc) { gen_op_save_pc(pc); } else { @@ -621,9 +700,9 @@ static inline void gen_save_pc(target_ulong pc) #endif } -static inline void gen_save_btarget(target_ulong btarget) +static always_inline void gen_save_btarget(target_ulong btarget) { -#ifdef TARGET_MIPS64 +#if defined(TARGET_MIPS64) if (btarget == (int32_t)btarget) { gen_op_save_btarget(btarget); } else { @@ -634,7 +713,7 @@ static inline void gen_save_btarget(target_ulong btarget) #endif } -static inline void save_cpu_state (DisasContext *ctx, int do_save_pc) +static always_inline void save_cpu_state (DisasContext *ctx, int do_save_pc) { #if defined MIPS_DEBUG_DISAS if (loglevel & CPU_LOG_TB_IN_ASM) { @@ -666,7 +745,7 @@ static inline void save_cpu_state (DisasContext *ctx, int do_save_pc) } } -static inline void restore_cpu_state (CPUState *env, DisasContext *ctx) +static always_inline void restore_cpu_state (CPUState *env, DisasContext *ctx) { ctx->saved_hflags = ctx->hflags; switch (ctx->hflags & MIPS_HFLAG_BMASK) { @@ -684,7 +763,7 @@ static inline void restore_cpu_state (CPUState *env, DisasContext *ctx) } } -static inline void generate_exception_err (DisasContext *ctx, int excp, int err) +static always_inline void generate_exception_err (DisasContext *ctx, int excp, int err) { #if defined MIPS_DEBUG_DISAS if (loglevel & CPU_LOG_TB_IN_ASM) @@ -698,20 +777,39 @@ static inline void generate_exception_err (DisasContext *ctx, int excp, int err) ctx->bstate = BS_EXCP; } -static inline void generate_exception (DisasContext *ctx, int excp) +static always_inline void generate_exception (DisasContext *ctx, int excp) { generate_exception_err (ctx, excp, 0); } -static inline void check_cp1_enabled(DisasContext *ctx) +static always_inline void check_cp0_enabled(DisasContext *ctx) { - if (!(ctx->hflags & MIPS_HFLAG_FPU)) + if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) generate_exception_err(ctx, EXCP_CpU, 1); } -static inline void check_cp1_64bitmode(DisasContext *ctx) +static always_inline void check_cp1_enabled(DisasContext *ctx) { - if (!(ctx->hflags & MIPS_HFLAG_F64)) + if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU))) + generate_exception_err(ctx, EXCP_CpU, 1); +} + +/* Verify that the processor is running with COP1X instructions enabled. + This is associated with the nabla symbol in the MIPS32 and MIPS64 + opcode tables. */ + +static always_inline void check_cop1x(DisasContext *ctx) +{ + if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X))) + generate_exception(ctx, EXCP_RI); +} + +/* Verify that the processor is running with 64-bit floating-point + operations enabled. */ + +static always_inline void check_cp1_64bitmode(DisasContext *ctx) +{ + if (unlikely(~ctx->hflags & (MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X))) generate_exception(ctx, EXCP_RI); } @@ -728,7 +826,23 @@ static inline void check_cp1_64bitmode(DisasContext *ctx) */ void check_cp1_registers(DisasContext *ctx, int regs) { - if (!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1)) + if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1))) + generate_exception(ctx, EXCP_RI); +} + +/* This code generates a "reserved instruction" exception if the + CPU does not support the instruction set corresponding to flags. */ +static always_inline void check_insn(CPUState *env, DisasContext *ctx, int flags) +{ + if (unlikely(!(env->insn_flags & flags))) + generate_exception(ctx, EXCP_RI); +} + +/* This code generates a "reserved instruction" exception if 64-bit + instructions are not enabled. */ +static always_inline void check_mips_64(DisasContext *ctx) +{ + if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) generate_exception(ctx, EXCP_RI); } @@ -740,17 +854,19 @@ void check_cp1_registers(DisasContext *ctx, int regs) #define op_ldst(name) (*gen_op_##name[ctx->mem_idx])() #define OP_LD_TABLE(width) \ static GenOpFunc *gen_op_l##width[] = { \ - &gen_op_l##width##_user, \ &gen_op_l##width##_kernel, \ + &gen_op_l##width##_super, \ + &gen_op_l##width##_user, \ } #define OP_ST_TABLE(width) \ static GenOpFunc *gen_op_s##width[] = { \ - &gen_op_s##width##_user, \ &gen_op_s##width##_kernel, \ + &gen_op_s##width##_super, \ + &gen_op_s##width##_user, \ } #endif -#ifdef TARGET_MIPS64 +#if defined(TARGET_MIPS64) OP_LD_TABLE(d); OP_LD_TABLE(dl); OP_LD_TABLE(dr); @@ -798,132 +914,131 @@ static void gen_ldst (DisasContext *ctx, uint32_t opc, int rt, gen_op_addr_add(); } /* Don't do NOP if destination is zero: we must perform the actual - * memory access - */ + memory access. */ switch (opc) { -#ifdef TARGET_MIPS64 +#if defined(TARGET_MIPS64) case OPC_LWU: op_ldst(lwu); - GEN_STORE_TN_REG(rt, T0); + GEN_STORE_T0_REG(rt); opn = "lwu"; break; case OPC_LD: op_ldst(ld); - GEN_STORE_TN_REG(rt, T0); + GEN_STORE_T0_REG(rt); opn = "ld"; break; case OPC_LLD: op_ldst(lld); - GEN_STORE_TN_REG(rt, T0); + GEN_STORE_T0_REG(rt); opn = "lld"; break; case OPC_SD: - GEN_LOAD_REG_TN(T1, rt); + GEN_LOAD_REG_T1(rt); op_ldst(sd); opn = "sd"; break; case OPC_SCD: save_cpu_state(ctx, 1); - GEN_LOAD_REG_TN(T1, rt); + GEN_LOAD_REG_T1(rt); op_ldst(scd); - GEN_STORE_TN_REG(rt, T0); + GEN_STORE_T0_REG(rt); opn = "scd"; break; case OPC_LDL: - GEN_LOAD_REG_TN(T1, rt); + GEN_LOAD_REG_T1(rt); op_ldst(ldl); - GEN_STORE_TN_REG(rt, T0); + GEN_STORE_T1_REG(rt); opn = "ldl"; break; case OPC_SDL: - GEN_LOAD_REG_TN(T1, rt); + GEN_LOAD_REG_T1(rt); op_ldst(sdl); opn = "sdl"; break; case OPC_LDR: - GEN_LOAD_REG_TN(T1, rt); + GEN_LOAD_REG_T1(rt); op_ldst(ldr); - GEN_STORE_TN_REG(rt, T0); + GEN_STORE_T1_REG(rt); opn = "ldr"; break; case OPC_SDR: - GEN_LOAD_REG_TN(T1, rt); + GEN_LOAD_REG_T1(rt); op_ldst(sdr); opn = "sdr"; break; #endif case OPC_LW: op_ldst(lw); - GEN_STORE_TN_REG(rt, T0); + GEN_STORE_T0_REG(rt); opn = "lw"; break; case OPC_SW: - GEN_LOAD_REG_TN(T1, rt); + GEN_LOAD_REG_T1(rt); op_ldst(sw); opn = "sw"; break; case OPC_LH: op_ldst(lh); - GEN_STORE_TN_REG(rt, T0); + GEN_STORE_T0_REG(rt); opn = "lh"; break; case OPC_SH: - GEN_LOAD_REG_TN(T1, rt); + GEN_LOAD_REG_T1(rt); op_ldst(sh); opn = "sh"; break; case OPC_LHU: op_ldst(lhu); - GEN_STORE_TN_REG(rt, T0); + GEN_STORE_T0_REG(rt); opn = "lhu"; break; case OPC_LB: op_ldst(lb); - GEN_STORE_TN_REG(rt, T0); + GEN_STORE_T0_REG(rt); opn = "lb"; break; case OPC_SB: - GEN_LOAD_REG_TN(T1, rt); + GEN_LOAD_REG_T1(rt); op_ldst(sb); opn = "sb"; break; case OPC_LBU: op_ldst(lbu); - GEN_STORE_TN_REG(rt, T0); + GEN_STORE_T0_REG(rt); opn = "lbu"; break; case OPC_LWL: - GEN_LOAD_REG_TN(T1, rt); + GEN_LOAD_REG_T1(rt); op_ldst(lwl); - GEN_STORE_TN_REG(rt, T0); + GEN_STORE_T1_REG(rt); opn = "lwl"; break; case OPC_SWL: - GEN_LOAD_REG_TN(T1, rt); + GEN_LOAD_REG_T1(rt); op_ldst(swl); opn = "swr"; break; case OPC_LWR: - GEN_LOAD_REG_TN(T1, rt); + GEN_LOAD_REG_T1(rt); op_ldst(lwr); - GEN_STORE_TN_REG(rt, T0); + GEN_STORE_T1_REG(rt); opn = "lwr"; break; case OPC_SWR: - GEN_LOAD_REG_TN(T1, rt); + GEN_LOAD_REG_T1(rt); op_ldst(swr); opn = "swr"; break; case OPC_LL: op_ldst(ll); - GEN_STORE_TN_REG(rt, T0); + GEN_STORE_T0_REG(rt); opn = "ll"; break; case OPC_SC: save_cpu_state(ctx, 1); - GEN_LOAD_REG_TN(T1, rt); + GEN_LOAD_REG_T1(rt); op_ldst(sc); - GEN_STORE_TN_REG(rt, T0); + GEN_STORE_T0_REG(rt); opn = "sc"; break; default: @@ -950,8 +1065,7 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft, gen_op_addr_add(); } /* Don't do NOP if destination is zero: we must perform the actual - * memory access - */ + memory access. */ switch (opc) { case OPC_LWC1: op_ldst(lwc1); @@ -982,16 +1096,15 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft, } /* Arithmetic with immediate operand */ -static void gen_arith_imm (DisasContext *ctx, uint32_t opc, int rt, - int rs, int16_t imm) +static void gen_arith_imm (CPUState *env, DisasContext *ctx, uint32_t opc, + int rt, int rs, int16_t imm) { target_ulong uimm; const char *opn = "imm arith"; if (rt == 0 && opc != OPC_ADDI && opc != OPC_DADDI) { - /* if no destination, treat it as a NOP - * For addi, we must generate the overflow exception when needed. - */ + /* If no destination, treat it as a NOP. + For addi, we must generate the overflow exception when needed. */ MIPS_DEBUG("NOP"); return; } @@ -999,7 +1112,7 @@ static void gen_arith_imm (DisasContext *ctx, uint32_t opc, int rt, switch (opc) { case OPC_ADDI: case OPC_ADDIU: -#ifdef TARGET_MIPS64 +#if defined(TARGET_MIPS64) case OPC_DADDI: case OPC_DADDIU: #endif @@ -1010,7 +1123,7 @@ static void gen_arith_imm (DisasContext *ctx, uint32_t opc, int rt, case OPC_ANDI: case OPC_ORI: case OPC_XORI: - GEN_LOAD_REG_TN(T0, rs); + GEN_LOAD_REG_T0(rs); GEN_LOAD_IMM_TN(T1, uimm); break; case OPC_LUI: @@ -1019,7 +1132,7 @@ static void gen_arith_imm (DisasContext *ctx, uint32_t opc, int rt, case OPC_SLL: case OPC_SRA: case OPC_SRL: -#ifdef TARGET_MIPS64 +#if defined(TARGET_MIPS64) case OPC_DSLL: case OPC_DSRA: case OPC_DSRL: @@ -1028,7 +1141,7 @@ static void gen_arith_imm (DisasContext *ctx, uint32_t opc, int rt, case OPC_DSRL32: #endif uimm &= 0x1f; - GEN_LOAD_REG_TN(T0, rs); + GEN_LOAD_REG_T0(rs); GEN_LOAD_IMM_TN(T1, uimm); break; } @@ -1042,7 +1155,7 @@ static void gen_arith_imm (DisasContext *ctx, uint32_t opc, int rt, gen_op_add(); opn = "addiu"; break; -#ifdef TARGET_MIPS64 +#if defined(TARGET_MIPS64) case OPC_DADDI: save_cpu_state(ctx, 1); gen_op_daddo(); @@ -1091,8 +1204,14 @@ static void gen_arith_imm (DisasContext *ctx, uint32_t opc, int rt, opn = "srl"; break; case 1: - gen_op_rotr(); - opn = "rotr"; + /* rotr is decoded as srl on non-R2 CPUs */ + if (env->insn_flags & ISA_MIPS32R2) { + gen_op_rotr(); + opn = "rotr"; + } else { + gen_op_srl(); + opn = "srl"; + } break; default: MIPS_INVAL("invalid srl flag"); @@ -1100,7 +1219,7 @@ static void gen_arith_imm (DisasContext *ctx, uint32_t opc, int rt, break; } break; -#ifdef TARGET_MIPS64 +#if defined(TARGET_MIPS64) case OPC_DSLL: gen_op_dsll(); opn = "dsll"; @@ -1116,8 +1235,14 @@ static void gen_arith_imm (DisasContext *ctx, uint32_t opc, int rt, opn = "dsrl"; break; case 1: - gen_op_drotr(); - opn = "drotr"; + /* drotr is decoded as dsrl on non-R2 CPUs */ + if (env->insn_flags & ISA_MIPS32R2) { + gen_op_drotr(); + opn = "drotr"; + } else { + gen_op_dsrl(); + opn = "dsrl"; + } break; default: MIPS_INVAL("invalid dsrl flag"); @@ -1140,8 +1265,14 @@ static void gen_arith_imm (DisasContext *ctx, uint32_t opc, int rt, opn = "dsrl32"; break; case 1: - gen_op_drotr32(); - opn = "drotr32"; + /* drotr32 is decoded as dsrl32 on non-R2 CPUs */ + if (env->insn_flags & ISA_MIPS32R2) { + gen_op_drotr32(); + opn = "drotr32"; + } else { + gen_op_dsrl32(); + opn = "dsrl32"; + } break; default: MIPS_INVAL("invalid dsrl32 flag"); @@ -1155,26 +1286,31 @@ static void gen_arith_imm (DisasContext *ctx, uint32_t opc, int rt, generate_exception(ctx, EXCP_RI); return; } - GEN_STORE_TN_REG(rt, T0); + GEN_STORE_T0_REG(rt); MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt], regnames[rs], uimm); } /* Arithmetic */ -static void gen_arith (DisasContext *ctx, uint32_t opc, +static void gen_arith (CPUState *env, DisasContext *ctx, uint32_t opc, int rd, int rs, int rt) { const char *opn = "arith"; if (rd == 0 && opc != OPC_ADD && opc != OPC_SUB && opc != OPC_DADD && opc != OPC_DSUB) { - /* if no destination, treat it as a NOP - * For add & sub, we must generate the overflow exception when needed. - */ + /* If no destination, treat it as a NOP. + For add & sub, we must generate the overflow exception when needed. */ MIPS_DEBUG("NOP"); return; } - GEN_LOAD_REG_TN(T0, rs); - GEN_LOAD_REG_TN(T1, rt); + GEN_LOAD_REG_T0(rs); + /* Specialcase the conventional move operation. */ + if (rt == 0 && (opc == OPC_ADDU || opc == OPC_DADDU + || opc == OPC_SUBU || opc == OPC_DSUBU)) { + GEN_STORE_T0_REG(rd); + return; + } + GEN_LOAD_REG_T1(rt); switch (opc) { case OPC_ADD: save_cpu_state(ctx, 1); @@ -1194,7 +1330,7 @@ static void gen_arith (DisasContext *ctx, uint32_t opc, gen_op_sub(); opn = "subu"; break; -#ifdef TARGET_MIPS64 +#if defined(TARGET_MIPS64) case OPC_DADD: save_cpu_state(ctx, 1); gen_op_daddo(); @@ -1265,8 +1401,14 @@ static void gen_arith (DisasContext *ctx, uint32_t opc, opn = "srlv"; break; case 1: - gen_op_rotrv(); - opn = "rotrv"; + /* rotrv is decoded as srlv on non-R2 CPUs */ + if (env->insn_flags & ISA_MIPS32R2) { + gen_op_rotrv(); + opn = "rotrv"; + } else { + gen_op_srlv(); + opn = "srlv"; + } break; default: MIPS_INVAL("invalid srlv flag"); @@ -1274,7 +1416,7 @@ static void gen_arith (DisasContext *ctx, uint32_t opc, break; } break; -#ifdef TARGET_MIPS64 +#if defined(TARGET_MIPS64) case OPC_DSLLV: gen_op_dsllv(); opn = "dsllv"; @@ -1290,8 +1432,14 @@ static void gen_arith (DisasContext *ctx, uint32_t opc, opn = "dsrlv"; break; case 1: - gen_op_drotrv(); - opn = "drotrv"; + /* drotrv is decoded as dsrlv on non-R2 CPUs */ + if (env->insn_flags & ISA_MIPS32R2) { + gen_op_drotrv(); + opn = "drotrv"; + } else { + gen_op_dsrlv(); + opn = "dsrlv"; + } break; default: MIPS_INVAL("invalid dsrlv flag"); @@ -1305,7 +1453,7 @@ static void gen_arith (DisasContext *ctx, uint32_t opc, generate_exception(ctx, EXCP_RI); return; } - GEN_STORE_TN_REG(rd, T0); + GEN_STORE_T0_REG(rd); print: MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]); } @@ -1316,29 +1464,29 @@ static void gen_HILO (DisasContext *ctx, uint32_t opc, int reg) const char *opn = "hilo"; if (reg == 0 && (opc == OPC_MFHI || opc == OPC_MFLO)) { - /* Treat as a NOP */ + /* Treat as NOP. */ MIPS_DEBUG("NOP"); return; } switch (opc) { case OPC_MFHI: - gen_op_load_HI(); - GEN_STORE_TN_REG(reg, T0); + gen_op_load_HI(0); + GEN_STORE_T0_REG(reg); opn = "mfhi"; break; case OPC_MFLO: - gen_op_load_LO(); - GEN_STORE_TN_REG(reg, T0); + gen_op_load_LO(0); + GEN_STORE_T0_REG(reg); opn = "mflo"; break; case OPC_MTHI: - GEN_LOAD_REG_TN(T0, reg); - gen_op_store_HI(); + GEN_LOAD_REG_T0(reg); + gen_op_store_HI(0); opn = "mthi"; break; case OPC_MTLO: - GEN_LOAD_REG_TN(T0, reg); - gen_op_store_LO(); + GEN_LOAD_REG_T0(reg); + gen_op_store_LO(0); opn = "mtlo"; break; default: @@ -1354,8 +1502,8 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc, { const char *opn = "mul/div"; - GEN_LOAD_REG_TN(T0, rs); - GEN_LOAD_REG_TN(T1, rt); + GEN_LOAD_REG_T0(rs); + GEN_LOAD_REG_T1(rt); switch (opc) { case OPC_DIV: gen_op_div(); @@ -1373,7 +1521,7 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc, gen_op_multu(); opn = "multu"; break; -#ifdef TARGET_MIPS64 +#if defined(TARGET_MIPS64) case OPC_DDIV: gen_op_ddiv(); opn = "ddiv"; @@ -1415,16 +1563,90 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc, MIPS_DEBUG("%s %s %s", opn, regnames[rs], regnames[rt]); } +static void gen_mul_vr54xx (DisasContext *ctx, uint32_t opc, + int rd, int rs, int rt) +{ + const char *opn = "mul vr54xx"; + + GEN_LOAD_REG_T0(rs); + GEN_LOAD_REG_T1(rt); + + switch (opc) { + case OPC_VR54XX_MULS: + gen_op_muls(); + opn = "muls"; + break; + case OPC_VR54XX_MULSU: + gen_op_mulsu(); + opn = "mulsu"; + break; + case OPC_VR54XX_MACC: + gen_op_macc(); + opn = "macc"; + break; + case OPC_VR54XX_MACCU: + gen_op_maccu(); + opn = "maccu"; + break; + case OPC_VR54XX_MSAC: + gen_op_msac(); + opn = "msac"; + break; + case OPC_VR54XX_MSACU: + gen_op_msacu(); + opn = "msacu"; + break; + case OPC_VR54XX_MULHI: + gen_op_mulhi(); + opn = "mulhi"; + break; + case OPC_VR54XX_MULHIU: + gen_op_mulhiu(); + opn = "mulhiu"; + break; + case OPC_VR54XX_MULSHI: + gen_op_mulshi(); + opn = "mulshi"; + break; + case OPC_VR54XX_MULSHIU: + gen_op_mulshiu(); + opn = "mulshiu"; + break; + case OPC_VR54XX_MACCHI: + gen_op_macchi(); + opn = "macchi"; + break; + case OPC_VR54XX_MACCHIU: + gen_op_macchiu(); + opn = "macchiu"; + break; + case OPC_VR54XX_MSACHI: + gen_op_msachi(); + opn = "msachi"; + break; + case OPC_VR54XX_MSACHIU: + gen_op_msachiu(); + opn = "msachiu"; + break; + default: + MIPS_INVAL("mul vr54xx"); + generate_exception(ctx, EXCP_RI); + return; + } + GEN_STORE_T0_REG(rd); + MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]); +} + static void gen_cl (DisasContext *ctx, uint32_t opc, int rd, int rs) { const char *opn = "CLx"; if (rd == 0) { - /* Treat as a NOP */ + /* Treat as NOP. */ MIPS_DEBUG("NOP"); return; } - GEN_LOAD_REG_TN(T0, rs); + GEN_LOAD_REG_T0(rs); switch (opc) { case OPC_CLO: gen_op_clo(); @@ -1434,7 +1656,7 @@ static void gen_cl (DisasContext *ctx, uint32_t opc, gen_op_clz(); opn = "clz"; break; -#ifdef TARGET_MIPS64 +#if defined(TARGET_MIPS64) case OPC_DCLO: gen_op_dclo(); opn = "dclo"; @@ -1470,8 +1692,8 @@ static void gen_trap (DisasContext *ctx, uint32_t opc, case OPC_TNE: /* Compare two registers */ if (rs != rt) { - GEN_LOAD_REG_TN(T0, rs); - GEN_LOAD_REG_TN(T1, rt); + GEN_LOAD_REG_T0(rs); + GEN_LOAD_REG_T1(rt); cond = 1; } break; @@ -1483,7 +1705,7 @@ static void gen_trap (DisasContext *ctx, uint32_t opc, case OPC_TNEI: /* Compare register to immediate */ if (rs != 0 || imm != 0) { - GEN_LOAD_REG_TN(T0, rs); + GEN_LOAD_REG_T0(rs); GEN_LOAD_IMM_TN(T1, (int32_t)imm); cond = 1; } @@ -1506,7 +1728,7 @@ static void gen_trap (DisasContext *ctx, uint32_t opc, case OPC_TLTIU: /* r0 < 0 unsigned */ case OPC_TNE: /* rs != rs */ case OPC_TNEI: /* r0 != 0 */ - /* Never trap: treat as NOP */ + /* Never trap: treat as NOP. */ return; default: MIPS_INVAL("trap"); @@ -1550,7 +1772,7 @@ static void gen_trap (DisasContext *ctx, uint32_t opc, ctx->bstate = BS_STOP; } -static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) +static always_inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) { TranslationBlock *tb; tb = ctx->tb; @@ -1596,8 +1818,8 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc, case OPC_BNEL: /* Compare two registers */ if (rs != rt) { - GEN_LOAD_REG_TN(T0, rs); - GEN_LOAD_REG_TN(T1, rt); + GEN_LOAD_REG_T0(rs); + GEN_LOAD_REG_T1(rt); bcond = 1; } btarget = ctx->pc + 4 + offset; @@ -1636,7 +1858,7 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc, generate_exception(ctx, EXCP_RI); return; } - GEN_LOAD_REG_TN(T2, rs); + GEN_LOAD_REG_T2(rs); break; default: MIPS_INVAL("branch/jump"); @@ -1666,7 +1888,7 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc, case OPC_BNE: /* rx != rx */ case OPC_BGTZ: /* 0 > 0 */ case OPC_BLTZ: /* 0 < 0 */ - /* Treated as NOP */ + /* Treat as NOP. */ MIPS_DEBUG("bnever (NOP)"); return; case OPC_BLTZAL: /* 0 < 0 */ @@ -1812,64 +2034,73 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc, static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt, int rs, int lsb, int msb) { - GEN_LOAD_REG_TN(T1, rs); + GEN_LOAD_REG_T1(rs); switch (opc) { case OPC_EXT: if (lsb + msb > 31) goto fail; gen_op_ext(lsb, msb + 1); break; +#if defined(TARGET_MIPS64) case OPC_DEXTM: if (lsb + msb > 63) goto fail; - gen_op_ext(lsb, msb + 1 + 32); + gen_op_dext(lsb, msb + 1 + 32); break; case OPC_DEXTU: if (lsb + msb > 63) goto fail; - gen_op_ext(lsb + 32, msb + 1); + gen_op_dext(lsb + 32, msb + 1); break; case OPC_DEXT: - gen_op_ext(lsb, msb + 1); + if (lsb + msb > 63) + goto fail; + gen_op_dext(lsb, msb + 1); break; +#endif case OPC_INS: if (lsb > msb) goto fail; - GEN_LOAD_REG_TN(T0, rt); + GEN_LOAD_REG_T0(rt); gen_op_ins(lsb, msb - lsb + 1); break; +#if defined(TARGET_MIPS64) case OPC_DINSM: if (lsb > msb) goto fail; - GEN_LOAD_REG_TN(T0, rt); - gen_op_ins(lsb, msb - lsb + 1 + 32); + GEN_LOAD_REG_T0(rt); + gen_op_dins(lsb, msb - lsb + 1 + 32); break; case OPC_DINSU: if (lsb > msb) goto fail; - GEN_LOAD_REG_TN(T0, rt); - gen_op_ins(lsb + 32, msb - lsb + 1); + GEN_LOAD_REG_T0(rt); + gen_op_dins(lsb + 32, msb - lsb + 1); break; case OPC_DINS: if (lsb > msb) goto fail; - GEN_LOAD_REG_TN(T0, rt); - gen_op_ins(lsb, msb - lsb + 1); + GEN_LOAD_REG_T0(rt); + gen_op_dins(lsb, msb - lsb + 1); break; +#endif default: fail: MIPS_INVAL("bitops"); generate_exception(ctx, EXCP_RI); return; } - GEN_STORE_TN_REG(rt, T0); + GEN_STORE_T0_REG(rt); } /* CP0 (MMU and control) */ -static void gen_mfc0 (DisasContext *ctx, int reg, int sel) +static void gen_mfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) { const char *rn = "invalid"; + if (sel != 0) + check_insn(env, ctx, ISA_MIPS32); + switch (reg) { case 0: switch (sel) { @@ -1878,17 +2109,20 @@ static void gen_mfc0 (DisasContext *ctx, int reg, int sel) rn = "Index"; break; case 1: -// gen_op_mfc0_mvpcontrol(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mfc0_mvpcontrol(); rn = "MVPControl"; -// break; + break; case 2: -// gen_op_mfc0_mvpconf0(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mfc0_mvpconf0(); rn = "MVPConf0"; -// break; + break; case 3: -// gen_op_mfc0_mvpconf1(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mfc0_mvpconf1(); rn = "MVPConf1"; -// break; + break; default: goto die; } @@ -1900,33 +2134,40 @@ static void gen_mfc0 (DisasContext *ctx, int reg, int sel) rn = "Random"; break; case 1: -// gen_op_mfc0_vpecontrol(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mfc0_vpecontrol(); rn = "VPEControl"; -// break; + break; case 2: -// gen_op_mfc0_vpeconf0(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mfc0_vpeconf0(); rn = "VPEConf0"; -// break; + break; case 3: -// gen_op_mfc0_vpeconf1(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mfc0_vpeconf1(); rn = "VPEConf1"; -// break; + break; case 4: -// gen_op_mfc0_YQMask(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mfc0_yqmask(); rn = "YQMask"; -// break; + break; case 5: -// gen_op_mfc0_vpeschedule(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mfc0_vpeschedule(); rn = "VPESchedule"; -// break; + break; case 6: -// gen_op_mfc0_vpeschefback(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mfc0_vpeschefback(); rn = "VPEScheFBack"; -// break; + break; case 7: -// gen_op_mfc0_vpeopt(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mfc0_vpeopt(); rn = "VPEOpt"; -// break; + break; default: goto die; } @@ -1938,33 +2179,40 @@ static void gen_mfc0 (DisasContext *ctx, int reg, int sel) rn = "EntryLo0"; break; case 1: -// gen_op_mfc0_tcstatus(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mfc0_tcstatus(); rn = "TCStatus"; -// break; + break; case 2: -// gen_op_mfc0_tcbind(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mfc0_tcbind(); rn = "TCBind"; -// break; + break; case 3: -// gen_op_mfc0_tcrestart(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mfc0_tcrestart(); rn = "TCRestart"; -// break; + break; case 4: -// gen_op_mfc0_tchalt(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mfc0_tchalt(); rn = "TCHalt"; -// break; + break; case 5: -// gen_op_mfc0_tccontext(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mfc0_tccontext(); rn = "TCContext"; -// break; + break; case 6: -// gen_op_mfc0_tcschedule(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mfc0_tcschedule(); rn = "TCSchedule"; -// break; + break; case 7: -// gen_op_mfc0_tcschefback(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mfc0_tcschefback(); rn = "TCScheFBack"; -// break; + break; default: goto die; } @@ -2000,6 +2248,7 @@ static void gen_mfc0 (DisasContext *ctx, int reg, int sel) rn = "PageMask"; break; case 1: + check_insn(env, ctx, ISA_MIPS32R2); gen_op_mfc0_pagegrain(); rn = "PageGrain"; break; @@ -2014,25 +2263,30 @@ static void gen_mfc0 (DisasContext *ctx, int reg, int sel) rn = "Wired"; break; case 1: -// gen_op_mfc0_srsconf0(); /* shadow registers */ + check_insn(env, ctx, ISA_MIPS32R2); + gen_op_mfc0_srsconf0(); rn = "SRSConf0"; -// break; + break; case 2: -// gen_op_mfc0_srsconf1(); /* shadow registers */ + check_insn(env, ctx, ISA_MIPS32R2); + gen_op_mfc0_srsconf1(); rn = "SRSConf1"; -// break; + break; case 3: -// gen_op_mfc0_srsconf2(); /* shadow registers */ + check_insn(env, ctx, ISA_MIPS32R2); + gen_op_mfc0_srsconf2(); rn = "SRSConf2"; -// break; + break; case 4: -// gen_op_mfc0_srsconf3(); /* shadow registers */ + check_insn(env, ctx, ISA_MIPS32R2); + gen_op_mfc0_srsconf3(); rn = "SRSConf3"; -// break; + break; case 5: -// gen_op_mfc0_srsconf4(); /* shadow registers */ + check_insn(env, ctx, ISA_MIPS32R2); + gen_op_mfc0_srsconf4(); rn = "SRSConf4"; -// break; + break; default: goto die; } @@ -2040,6 +2294,7 @@ static void gen_mfc0 (DisasContext *ctx, int reg, int sel) case 7: switch (sel) { case 0: + check_insn(env, ctx, ISA_MIPS32R2); gen_op_mfc0_hwrena(); rn = "HWREna"; break; @@ -2096,14 +2351,17 @@ static void gen_mfc0 (DisasContext *ctx, int reg, int sel) rn = "Status"; break; case 1: + check_insn(env, ctx, ISA_MIPS32R2); gen_op_mfc0_intctl(); rn = "IntCtl"; break; case 2: + check_insn(env, ctx, ISA_MIPS32R2); gen_op_mfc0_srsctl(); rn = "SRSCtl"; break; case 3: + check_insn(env, ctx, ISA_MIPS32R2); gen_op_mfc0_srsmap(); rn = "SRSMap"; break; @@ -2138,6 +2396,7 @@ static void gen_mfc0 (DisasContext *ctx, int reg, int sel) rn = "PRid"; break; case 1: + check_insn(env, ctx, ISA_MIPS32R2); gen_op_mfc0_ebase(); rn = "EBase"; break; @@ -2210,7 +2469,8 @@ static void gen_mfc0 (DisasContext *ctx, int reg, int sel) case 20: switch (sel) { case 0: -#ifdef TARGET_MIPS64 +#if defined(TARGET_MIPS64) + check_insn(env, ctx, ISA_MIPS3); gen_op_mfc0_xcontext(); rn = "XContext"; break; @@ -2402,29 +2662,35 @@ die: generate_exception(ctx, EXCP_RI); } -static void gen_mtc0 (DisasContext *ctx, int reg, int sel) +static void gen_mtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) { const char *rn = "invalid"; + if (sel != 0) + check_insn(env, ctx, ISA_MIPS32); + switch (reg) { case 0: switch (sel) { case 0: - gen_op_mtc0_index(); + gen_op_mtc0_index(); rn = "Index"; break; case 1: -// gen_op_mtc0_mvpcontrol(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mtc0_mvpcontrol(); rn = "MVPControl"; -// break; + break; case 2: -// gen_op_mtc0_mvpconf0(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + /* ignored */ rn = "MVPConf0"; -// break; + break; case 3: -// gen_op_mtc0_mvpconf1(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + /* ignored */ rn = "MVPConf1"; -// break; + break; default: goto die; } @@ -2436,33 +2702,40 @@ static void gen_mtc0 (DisasContext *ctx, int reg, int sel) rn = "Random"; break; case 1: -// gen_op_mtc0_vpecontrol(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mtc0_vpecontrol(); rn = "VPEControl"; -// break; + break; case 2: -// gen_op_mtc0_vpeconf0(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mtc0_vpeconf0(); rn = "VPEConf0"; -// break; + break; case 3: -// gen_op_mtc0_vpeconf1(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mtc0_vpeconf1(); rn = "VPEConf1"; -// break; + break; case 4: -// gen_op_mtc0_YQMask(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mtc0_yqmask(); rn = "YQMask"; -// break; + break; case 5: -// gen_op_mtc0_vpeschedule(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mtc0_vpeschedule(); rn = "VPESchedule"; -// break; + break; case 6: -// gen_op_mtc0_vpeschefback(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mtc0_vpeschefback(); rn = "VPEScheFBack"; -// break; + break; case 7: -// gen_op_mtc0_vpeopt(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mtc0_vpeopt(); rn = "VPEOpt"; -// break; + break; default: goto die; } @@ -2474,33 +2747,40 @@ static void gen_mtc0 (DisasContext *ctx, int reg, int sel) rn = "EntryLo0"; break; case 1: -// gen_op_mtc0_tcstatus(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mtc0_tcstatus(); rn = "TCStatus"; -// break; + break; case 2: -// gen_op_mtc0_tcbind(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mtc0_tcbind(); rn = "TCBind"; -// break; + break; case 3: -// gen_op_mtc0_tcrestart(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mtc0_tcrestart(); rn = "TCRestart"; -// break; + break; case 4: -// gen_op_mtc0_tchalt(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mtc0_tchalt(); rn = "TCHalt"; -// break; + break; case 5: -// gen_op_mtc0_tccontext(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mtc0_tccontext(); rn = "TCContext"; -// break; + break; case 6: -// gen_op_mtc0_tcschedule(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mtc0_tcschedule(); rn = "TCSchedule"; -// break; + break; case 7: -// gen_op_mtc0_tcschefback(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mtc0_tcschefback(); rn = "TCScheFBack"; -// break; + break; default: goto die; } @@ -2536,6 +2816,7 @@ static void gen_mtc0 (DisasContext *ctx, int reg, int sel) rn = "PageMask"; break; case 1: + check_insn(env, ctx, ISA_MIPS32R2); gen_op_mtc0_pagegrain(); rn = "PageGrain"; break; @@ -2550,25 +2831,30 @@ static void gen_mtc0 (DisasContext *ctx, int reg, int sel) rn = "Wired"; break; case 1: -// gen_op_mtc0_srsconf0(); /* shadow registers */ + check_insn(env, ctx, ISA_MIPS32R2); + gen_op_mtc0_srsconf0(); rn = "SRSConf0"; -// break; + break; case 2: -// gen_op_mtc0_srsconf1(); /* shadow registers */ + check_insn(env, ctx, ISA_MIPS32R2); + gen_op_mtc0_srsconf1(); rn = "SRSConf1"; -// break; + break; case 3: -// gen_op_mtc0_srsconf2(); /* shadow registers */ + check_insn(env, ctx, ISA_MIPS32R2); + gen_op_mtc0_srsconf2(); rn = "SRSConf2"; -// break; + break; case 4: -// gen_op_mtc0_srsconf3(); /* shadow registers */ + check_insn(env, ctx, ISA_MIPS32R2); + gen_op_mtc0_srsconf3(); rn = "SRSConf3"; -// break; + break; case 5: -// gen_op_mtc0_srsconf4(); /* shadow registers */ + check_insn(env, ctx, ISA_MIPS32R2); + gen_op_mtc0_srsconf4(); rn = "SRSConf4"; -// break; + break; default: goto die; } @@ -2576,6 +2862,7 @@ static void gen_mtc0 (DisasContext *ctx, int reg, int sel) case 7: switch (sel) { case 0: + check_insn(env, ctx, ISA_MIPS32R2); gen_op_mtc0_hwrena(); rn = "HWREna"; break; @@ -2627,25 +2914,35 @@ static void gen_mtc0 (DisasContext *ctx, int reg, int sel) switch (sel) { case 0: gen_op_mtc0_status(); + /* BS_STOP isn't good enough here, hflags may have changed. */ + gen_save_pc(ctx->pc + 4); + ctx->bstate = BS_EXCP; rn = "Status"; break; case 1: + check_insn(env, ctx, ISA_MIPS32R2); gen_op_mtc0_intctl(); + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; rn = "IntCtl"; break; case 2: + check_insn(env, ctx, ISA_MIPS32R2); gen_op_mtc0_srsctl(); + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; rn = "SRSCtl"; break; case 3: + check_insn(env, ctx, ISA_MIPS32R2); gen_op_mtc0_srsmap(); + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; rn = "SRSMap"; break; default: goto die; } - /* Stop translation as we may have switched the execution mode */ - ctx->bstate = BS_STOP; break; case 13: switch (sel) { @@ -2676,6 +2973,7 @@ static void gen_mtc0 (DisasContext *ctx, int reg, int sel) rn = "PRid"; break; case 1: + check_insn(env, ctx, ISA_MIPS32R2); gen_op_mtc0_ebase(); rn = "EBase"; break; @@ -2753,7 +3051,8 @@ static void gen_mtc0 (DisasContext *ctx, int reg, int sel) case 20: switch (sel) { case 0: -#ifdef TARGET_MIPS64 +#if defined(TARGET_MIPS64) + check_insn(env, ctx, ISA_MIPS3); gen_op_mtc0_xcontext(); rn = "XContext"; break; @@ -2781,29 +3080,40 @@ static void gen_mtc0 (DisasContext *ctx, int reg, int sel) switch (sel) { case 0: gen_op_mtc0_debug(); /* EJTAG support */ + /* BS_STOP isn't good enough here, hflags may have changed. */ + gen_save_pc(ctx->pc + 4); + ctx->bstate = BS_EXCP; rn = "Debug"; break; case 1: // gen_op_mtc0_tracecontrol(); /* PDtrace support */ rn = "TraceControl"; + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; // break; case 2: // gen_op_mtc0_tracecontrol2(); /* PDtrace support */ rn = "TraceControl2"; + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; // break; case 3: + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; // gen_op_mtc0_usertracedata(); /* PDtrace support */ rn = "UserTraceData"; + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; // break; case 4: // gen_op_mtc0_debug(); /* PDtrace support */ + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; rn = "TraceBPC"; // break; default: goto die; } - /* Stop translation as we may have switched the execution mode */ - ctx->bstate = BS_STOP; break; case 24: switch (sel) { @@ -2951,11 +3261,14 @@ die: generate_exception(ctx, EXCP_RI); } -#ifdef TARGET_MIPS64 -static void gen_dmfc0 (DisasContext *ctx, int reg, int sel) +#if defined(TARGET_MIPS64) +static void gen_dmfc0 (CPUState *env, DisasContext *ctx, int reg, int sel) { const char *rn = "invalid"; + if (sel != 0) + check_insn(env, ctx, ISA_MIPS64); + switch (reg) { case 0: switch (sel) { @@ -2964,17 +3277,20 @@ static void gen_dmfc0 (DisasContext *ctx, int reg, int sel) rn = "Index"; break; case 1: -// gen_op_dmfc0_mvpcontrol(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mfc0_mvpcontrol(); rn = "MVPControl"; -// break; + break; case 2: -// gen_op_dmfc0_mvpconf0(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mfc0_mvpconf0(); rn = "MVPConf0"; -// break; + break; case 3: -// gen_op_dmfc0_mvpconf1(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mfc0_mvpconf1(); rn = "MVPConf1"; -// break; + break; default: goto die; } @@ -2986,33 +3302,40 @@ static void gen_dmfc0 (DisasContext *ctx, int reg, int sel) rn = "Random"; break; case 1: -// gen_op_dmfc0_vpecontrol(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mfc0_vpecontrol(); rn = "VPEControl"; -// break; + break; case 2: -// gen_op_dmfc0_vpeconf0(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mfc0_vpeconf0(); rn = "VPEConf0"; -// break; + break; case 3: -// gen_op_dmfc0_vpeconf1(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mfc0_vpeconf1(); rn = "VPEConf1"; -// break; + break; case 4: -// gen_op_dmfc0_YQMask(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_dmfc0_yqmask(); rn = "YQMask"; -// break; + break; case 5: -// gen_op_dmfc0_vpeschedule(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_dmfc0_vpeschedule(); rn = "VPESchedule"; -// break; + break; case 6: -// gen_op_dmfc0_vpeschefback(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_dmfc0_vpeschefback(); rn = "VPEScheFBack"; -// break; + break; case 7: -// gen_op_dmfc0_vpeopt(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mfc0_vpeopt(); rn = "VPEOpt"; -// break; + break; default: goto die; } @@ -3024,33 +3347,40 @@ static void gen_dmfc0 (DisasContext *ctx, int reg, int sel) rn = "EntryLo0"; break; case 1: -// gen_op_dmfc0_tcstatus(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mfc0_tcstatus(); rn = "TCStatus"; -// break; + break; case 2: -// gen_op_dmfc0_tcbind(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mfc0_tcbind(); rn = "TCBind"; -// break; + break; case 3: -// gen_op_dmfc0_tcrestart(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_dmfc0_tcrestart(); rn = "TCRestart"; -// break; + break; case 4: -// gen_op_dmfc0_tchalt(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_dmfc0_tchalt(); rn = "TCHalt"; -// break; + break; case 5: -// gen_op_dmfc0_tccontext(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_dmfc0_tccontext(); rn = "TCContext"; -// break; + break; case 6: -// gen_op_dmfc0_tcschedule(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_dmfc0_tcschedule(); rn = "TCSchedule"; -// break; + break; case 7: -// gen_op_dmfc0_tcschefback(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_dmfc0_tcschefback(); rn = "TCScheFBack"; -// break; + break; default: goto die; } @@ -3086,6 +3416,7 @@ static void gen_dmfc0 (DisasContext *ctx, int reg, int sel) rn = "PageMask"; break; case 1: + check_insn(env, ctx, ISA_MIPS32R2); gen_op_mfc0_pagegrain(); rn = "PageGrain"; break; @@ -3100,25 +3431,30 @@ static void gen_dmfc0 (DisasContext *ctx, int reg, int sel) rn = "Wired"; break; case 1: -// gen_op_dmfc0_srsconf0(); /* shadow registers */ + check_insn(env, ctx, ISA_MIPS32R2); + gen_op_mfc0_srsconf0(); rn = "SRSConf0"; -// break; + break; case 2: -// gen_op_dmfc0_srsconf1(); /* shadow registers */ + check_insn(env, ctx, ISA_MIPS32R2); + gen_op_mfc0_srsconf1(); rn = "SRSConf1"; -// break; + break; case 3: -// gen_op_dmfc0_srsconf2(); /* shadow registers */ + check_insn(env, ctx, ISA_MIPS32R2); + gen_op_mfc0_srsconf2(); rn = "SRSConf2"; -// break; + break; case 4: -// gen_op_dmfc0_srsconf3(); /* shadow registers */ + check_insn(env, ctx, ISA_MIPS32R2); + gen_op_mfc0_srsconf3(); rn = "SRSConf3"; -// break; + break; case 5: -// gen_op_dmfc0_srsconf4(); /* shadow registers */ + check_insn(env, ctx, ISA_MIPS32R2); + gen_op_mfc0_srsconf4(); rn = "SRSConf4"; -// break; + break; default: goto die; } @@ -3126,6 +3462,7 @@ static void gen_dmfc0 (DisasContext *ctx, int reg, int sel) case 7: switch (sel) { case 0: + check_insn(env, ctx, ISA_MIPS32R2); gen_op_mfc0_hwrena(); rn = "HWREna"; break; @@ -3182,15 +3519,18 @@ static void gen_dmfc0 (DisasContext *ctx, int reg, int sel) rn = "Status"; break; case 1: + check_insn(env, ctx, ISA_MIPS32R2); gen_op_mfc0_intctl(); rn = "IntCtl"; break; case 2: + check_insn(env, ctx, ISA_MIPS32R2); gen_op_mfc0_srsctl(); rn = "SRSCtl"; break; case 3: - gen_op_mfc0_srsmap(); /* shadow registers */ + check_insn(env, ctx, ISA_MIPS32R2); + gen_op_mfc0_srsmap(); rn = "SRSMap"; break; default: @@ -3224,6 +3564,7 @@ static void gen_dmfc0 (DisasContext *ctx, int reg, int sel) rn = "PRid"; break; case 1: + check_insn(env, ctx, ISA_MIPS32R2); gen_op_mfc0_ebase(); rn = "EBase"; break; @@ -3287,11 +3628,10 @@ static void gen_dmfc0 (DisasContext *ctx, int reg, int sel) case 20: switch (sel) { case 0: -#ifdef TARGET_MIPS64 + check_insn(env, ctx, ISA_MIPS3); gen_op_dmfc0_xcontext(); rn = "XContext"; break; -#endif default: goto die; } @@ -3479,10 +3819,13 @@ die: generate_exception(ctx, EXCP_RI); } -static void gen_dmtc0 (DisasContext *ctx, int reg, int sel) +static void gen_dmtc0 (CPUState *env, DisasContext *ctx, int reg, int sel) { const char *rn = "invalid"; + if (sel != 0) + check_insn(env, ctx, ISA_MIPS64); + switch (reg) { case 0: switch (sel) { @@ -3491,17 +3834,20 @@ static void gen_dmtc0 (DisasContext *ctx, int reg, int sel) rn = "Index"; break; case 1: -// gen_op_mtc0_mvpcontrol(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mtc0_mvpcontrol(); rn = "MVPControl"; -// break; + break; case 2: -// gen_op_mtc0_mvpconf0(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + /* ignored */ rn = "MVPConf0"; -// break; + break; case 3: -// gen_op_mtc0_mvpconf1(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + /* ignored */ rn = "MVPConf1"; -// break; + break; default: goto die; } @@ -3513,33 +3859,40 @@ static void gen_dmtc0 (DisasContext *ctx, int reg, int sel) rn = "Random"; break; case 1: -// gen_op_mtc0_vpecontrol(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mtc0_vpecontrol(); rn = "VPEControl"; -// break; + break; case 2: -// gen_op_mtc0_vpeconf0(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mtc0_vpeconf0(); rn = "VPEConf0"; -// break; + break; case 3: -// gen_op_mtc0_vpeconf1(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mtc0_vpeconf1(); rn = "VPEConf1"; -// break; + break; case 4: -// gen_op_mtc0_YQMask(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mtc0_yqmask(); rn = "YQMask"; -// break; + break; case 5: -// gen_op_mtc0_vpeschedule(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mtc0_vpeschedule(); rn = "VPESchedule"; -// break; + break; case 6: -// gen_op_mtc0_vpeschefback(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mtc0_vpeschefback(); rn = "VPEScheFBack"; -// break; + break; case 7: -// gen_op_mtc0_vpeopt(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mtc0_vpeopt(); rn = "VPEOpt"; -// break; + break; default: goto die; } @@ -3551,33 +3904,40 @@ static void gen_dmtc0 (DisasContext *ctx, int reg, int sel) rn = "EntryLo0"; break; case 1: -// gen_op_mtc0_tcstatus(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mtc0_tcstatus(); rn = "TCStatus"; -// break; + break; case 2: -// gen_op_mtc0_tcbind(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mtc0_tcbind(); rn = "TCBind"; -// break; + break; case 3: -// gen_op_mtc0_tcrestart(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mtc0_tcrestart(); rn = "TCRestart"; -// break; + break; case 4: -// gen_op_mtc0_tchalt(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mtc0_tchalt(); rn = "TCHalt"; -// break; + break; case 5: -// gen_op_mtc0_tccontext(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mtc0_tccontext(); rn = "TCContext"; -// break; + break; case 6: -// gen_op_mtc0_tcschedule(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mtc0_tcschedule(); rn = "TCSchedule"; -// break; + break; case 7: -// gen_op_mtc0_tcschefback(); /* MT ASE */ + check_insn(env, ctx, ASE_MT); + gen_op_mtc0_tcschefback(); rn = "TCScheFBack"; -// break; + break; default: goto die; } @@ -3613,6 +3973,7 @@ static void gen_dmtc0 (DisasContext *ctx, int reg, int sel) rn = "PageMask"; break; case 1: + check_insn(env, ctx, ISA_MIPS32R2); gen_op_mtc0_pagegrain(); rn = "PageGrain"; break; @@ -3627,25 +3988,30 @@ static void gen_dmtc0 (DisasContext *ctx, int reg, int sel) rn = "Wired"; break; case 1: -// gen_op_mtc0_srsconf0(); /* shadow registers */ + check_insn(env, ctx, ISA_MIPS32R2); + gen_op_mtc0_srsconf0(); rn = "SRSConf0"; -// break; + break; case 2: -// gen_op_mtc0_srsconf1(); /* shadow registers */ + check_insn(env, ctx, ISA_MIPS32R2); + gen_op_mtc0_srsconf1(); rn = "SRSConf1"; -// break; + break; case 3: -// gen_op_mtc0_srsconf2(); /* shadow registers */ + check_insn(env, ctx, ISA_MIPS32R2); + gen_op_mtc0_srsconf2(); rn = "SRSConf2"; -// break; + break; case 4: -// gen_op_mtc0_srsconf3(); /* shadow registers */ + check_insn(env, ctx, ISA_MIPS32R2); + gen_op_mtc0_srsconf3(); rn = "SRSConf3"; -// break; + break; case 5: -// gen_op_mtc0_srsconf4(); /* shadow registers */ + check_insn(env, ctx, ISA_MIPS32R2); + gen_op_mtc0_srsconf4(); rn = "SRSConf4"; -// break; + break; default: goto die; } @@ -3653,6 +4019,7 @@ static void gen_dmtc0 (DisasContext *ctx, int reg, int sel) case 7: switch (sel) { case 0: + check_insn(env, ctx, ISA_MIPS32R2); gen_op_mtc0_hwrena(); rn = "HWREna"; break; @@ -3704,25 +4071,35 @@ static void gen_dmtc0 (DisasContext *ctx, int reg, int sel) switch (sel) { case 0: gen_op_mtc0_status(); + /* BS_STOP isn't good enough here, hflags may have changed. */ + gen_save_pc(ctx->pc + 4); + ctx->bstate = BS_EXCP; rn = "Status"; break; case 1: + check_insn(env, ctx, ISA_MIPS32R2); gen_op_mtc0_intctl(); + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; rn = "IntCtl"; break; case 2: + check_insn(env, ctx, ISA_MIPS32R2); gen_op_mtc0_srsctl(); + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; rn = "SRSCtl"; break; case 3: + check_insn(env, ctx, ISA_MIPS32R2); gen_op_mtc0_srsmap(); + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; rn = "SRSMap"; break; default: goto die; } - /* Stop translation as we may have switched the execution mode */ - ctx->bstate = BS_STOP; break; case 13: switch (sel) { @@ -3753,6 +4130,7 @@ static void gen_dmtc0 (DisasContext *ctx, int reg, int sel) rn = "PRid"; break; case 1: + check_insn(env, ctx, ISA_MIPS32R2); gen_op_mtc0_ebase(); rn = "EBase"; break; @@ -3821,11 +4199,10 @@ static void gen_dmtc0 (DisasContext *ctx, int reg, int sel) case 20: switch (sel) { case 0: -#ifdef TARGET_MIPS64 + check_insn(env, ctx, ISA_MIPS3); gen_op_mtc0_xcontext(); rn = "XContext"; break; -#endif default: goto die; } @@ -3849,29 +4226,38 @@ static void gen_dmtc0 (DisasContext *ctx, int reg, int sel) switch (sel) { case 0: gen_op_mtc0_debug(); /* EJTAG support */ + /* BS_STOP isn't good enough here, hflags may have changed. */ + gen_save_pc(ctx->pc + 4); + ctx->bstate = BS_EXCP; rn = "Debug"; break; case 1: // gen_op_mtc0_tracecontrol(); /* PDtrace support */ + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; rn = "TraceControl"; // break; case 2: // gen_op_mtc0_tracecontrol2(); /* PDtrace support */ + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; rn = "TraceControl2"; // break; case 3: // gen_op_mtc0_usertracedata(); /* PDtrace support */ + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; rn = "UserTraceData"; // break; case 4: // gen_op_mtc0_debug(); /* PDtrace support */ + /* Stop translation as we may have switched the execution mode */ + ctx->bstate = BS_STOP; rn = "TraceBPC"; // break; default: goto die; } - /* Stop translation as we may have switched the execution mode */ - ctx->bstate = BS_STOP; break; case 24: switch (sel) { @@ -4020,6 +4406,334 @@ die: } #endif /* TARGET_MIPS64 */ +static void gen_mftr(CPUState *env, DisasContext *ctx, int rt, + int u, int sel, int h) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 && + ((env->CP0_TCBind[other_tc] & (0xf << CP0TCBd_CurVPE)) != + (env->CP0_TCBind[env->current_tc] & (0xf << CP0TCBd_CurVPE)))) + gen_op_set_T0(-1); + else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) > + (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC))) + gen_op_set_T0(-1); + else if (u == 0) { + switch (rt) { + case 2: + switch (sel) { + case 1: + gen_op_mftc0_tcstatus(); + break; + case 2: + gen_op_mftc0_tcbind(); + break; + case 3: + gen_op_mftc0_tcrestart(); + break; + case 4: + gen_op_mftc0_tchalt(); + break; + case 5: + gen_op_mftc0_tccontext(); + break; + case 6: + gen_op_mftc0_tcschedule(); + break; + case 7: + gen_op_mftc0_tcschefback(); + break; + default: + gen_mfc0(env, ctx, rt, sel); + break; + } + break; + case 10: + switch (sel) { + case 0: + gen_op_mftc0_entryhi(); + break; + default: + gen_mfc0(env, ctx, rt, sel); + break; + } + case 12: + switch (sel) { + case 0: + gen_op_mftc0_status(); + break; + default: + gen_mfc0(env, ctx, rt, sel); + break; + } + case 23: + switch (sel) { + case 0: + gen_op_mftc0_debug(); + break; + default: + gen_mfc0(env, ctx, rt, sel); + break; + } + break; + default: + gen_mfc0(env, ctx, rt, sel); + } + } else switch (sel) { + /* GPR registers. */ + case 0: + gen_op_mftgpr(rt); + break; + /* Auxiliary CPU registers */ + case 1: + switch (rt) { + case 0: + gen_op_mftlo(0); + break; + case 1: + gen_op_mfthi(0); + break; + case 2: + gen_op_mftacx(0); + break; + case 4: + gen_op_mftlo(1); + break; + case 5: + gen_op_mfthi(1); + break; + case 6: + gen_op_mftacx(1); + break; + case 8: + gen_op_mftlo(2); + break; + case 9: + gen_op_mfthi(2); + break; + case 10: + gen_op_mftacx(2); + break; + case 12: + gen_op_mftlo(3); + break; + case 13: + gen_op_mfthi(3); + break; + case 14: + gen_op_mftacx(3); + break; + case 16: + gen_op_mftdsp(); + break; + default: + goto die; + } + break; + /* Floating point (COP1). */ + case 2: + /* XXX: For now we support only a single FPU context. */ + if (h == 0) { + GEN_LOAD_FREG_FTN(WT0, rt); + gen_op_mfc1(); + } else { + GEN_LOAD_FREG_FTN(WTH0, rt); + gen_op_mfhc1(); + } + break; + case 3: + /* XXX: For now we support only a single FPU context. */ + gen_op_cfc1(rt); + break; + /* COP2: Not implemented. */ + case 4: + case 5: + /* fall through */ + default: + goto die; + } +#if defined MIPS_DEBUG_DISAS + if (loglevel & CPU_LOG_TB_IN_ASM) { + fprintf(logfile, "mftr (reg %d u %d sel %d h %d)\n", + rt, u, sel, h); + } +#endif + return; + +die: +#if defined MIPS_DEBUG_DISAS + if (loglevel & CPU_LOG_TB_IN_ASM) { + fprintf(logfile, "mftr (reg %d u %d sel %d h %d)\n", + rt, u, sel, h); + } +#endif + generate_exception(ctx, EXCP_RI); +} + +static void gen_mttr(CPUState *env, DisasContext *ctx, int rd, + int u, int sel, int h) +{ + int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + + if ((env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) == 0 && + ((env->CP0_TCBind[other_tc] & (0xf << CP0TCBd_CurVPE)) != + (env->CP0_TCBind[env->current_tc] & (0xf << CP0TCBd_CurVPE)))) + /* NOP */ ; + else if ((env->CP0_VPEControl & (0xff << CP0VPECo_TargTC)) > + (env->mvp->CP0_MVPConf0 & (0xff << CP0MVPC0_PTC))) + /* NOP */ ; + else if (u == 0) { + switch (rd) { + case 2: + switch (sel) { + case 1: + gen_op_mttc0_tcstatus(); + break; + case 2: + gen_op_mttc0_tcbind(); + break; + case 3: + gen_op_mttc0_tcrestart(); + break; + case 4: + gen_op_mttc0_tchalt(); + break; + case 5: + gen_op_mttc0_tccontext(); + break; + case 6: + gen_op_mttc0_tcschedule(); + break; + case 7: + gen_op_mttc0_tcschefback(); + break; + default: + gen_mtc0(env, ctx, rd, sel); + break; + } + break; + case 10: + switch (sel) { + case 0: + gen_op_mttc0_entryhi(); + break; + default: + gen_mtc0(env, ctx, rd, sel); + break; + } + case 12: + switch (sel) { + case 0: + gen_op_mttc0_status(); + break; + default: + gen_mtc0(env, ctx, rd, sel); + break; + } + case 23: + switch (sel) { + case 0: + gen_op_mttc0_debug(); + break; + default: + gen_mtc0(env, ctx, rd, sel); + break; + } + break; + default: + gen_mtc0(env, ctx, rd, sel); + } + } else switch (sel) { + /* GPR registers. */ + case 0: + gen_op_mttgpr(rd); + break; + /* Auxiliary CPU registers */ + case 1: + switch (rd) { + case 0: + gen_op_mttlo(0); + break; + case 1: + gen_op_mtthi(0); + break; + case 2: + gen_op_mttacx(0); + break; + case 4: + gen_op_mttlo(1); + break; + case 5: + gen_op_mtthi(1); + break; + case 6: + gen_op_mttacx(1); + break; + case 8: + gen_op_mttlo(2); + break; + case 9: + gen_op_mtthi(2); + break; + case 10: + gen_op_mttacx(2); + break; + case 12: + gen_op_mttlo(3); + break; + case 13: + gen_op_mtthi(3); + break; + case 14: + gen_op_mttacx(3); + break; + case 16: + gen_op_mttdsp(); + break; + default: + goto die; + } + break; + /* Floating point (COP1). */ + case 2: + /* XXX: For now we support only a single FPU context. */ + if (h == 0) { + gen_op_mtc1(); + GEN_STORE_FTN_FREG(rd, WT0); + } else { + gen_op_mthc1(); + GEN_STORE_FTN_FREG(rd, WTH0); + } + break; + case 3: + /* XXX: For now we support only a single FPU context. */ + gen_op_ctc1(rd); + break; + /* COP2: Not implemented. */ + case 4: + case 5: + /* fall through */ + default: + goto die; + } +#if defined MIPS_DEBUG_DISAS + if (loglevel & CPU_LOG_TB_IN_ASM) { + fprintf(logfile, "mttr (reg %d u %d sel %d h %d)\n", + rd, u, sel, h); + } +#endif + return; + +die: +#if defined MIPS_DEBUG_DISAS + if (loglevel & CPU_LOG_TB_IN_ASM) { + fprintf(logfile, "mttr (reg %d u %d sel %d h %d)\n", + rd, u, sel, h); + } +#endif + generate_exception(ctx, EXCP_RI); +} + static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int rd) { const char *opn = "ldst"; @@ -4027,75 +4741,102 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int switch (opc) { case OPC_MFC0: if (rt == 0) { - /* Treat as NOP */ + /* Treat as NOP. */ return; } - gen_mfc0(ctx, rd, ctx->opcode & 0x7); + gen_mfc0(env, ctx, rd, ctx->opcode & 0x7); gen_op_store_T0_gpr(rt); opn = "mfc0"; break; case OPC_MTC0: - GEN_LOAD_REG_TN(T0, rt); - gen_mtc0(ctx, rd, ctx->opcode & 0x7); + GEN_LOAD_REG_T0(rt); + save_cpu_state(ctx, 1); + gen_mtc0(env, ctx, rd, ctx->opcode & 0x7); opn = "mtc0"; break; -#ifdef TARGET_MIPS64 +#if defined(TARGET_MIPS64) case OPC_DMFC0: + check_insn(env, ctx, ISA_MIPS3); if (rt == 0) { - /* Treat as NOP */ + /* Treat as NOP. */ return; } - gen_dmfc0(ctx, rd, ctx->opcode & 0x7); + gen_dmfc0(env, ctx, rd, ctx->opcode & 0x7); gen_op_store_T0_gpr(rt); opn = "dmfc0"; break; case OPC_DMTC0: - GEN_LOAD_REG_TN(T0, rt); - gen_dmtc0(ctx, rd, ctx->opcode & 0x7); + check_insn(env, ctx, ISA_MIPS3); + GEN_LOAD_REG_T0(rt); + save_cpu_state(ctx, 1); + gen_dmtc0(env, ctx, rd, ctx->opcode & 0x7); opn = "dmtc0"; break; #endif + case OPC_MFTR: + check_insn(env, ctx, ASE_MT); + if (rd == 0) { + /* Treat as NOP. */ + return; + } + gen_mftr(env, ctx, rt, (ctx->opcode >> 5) & 1, + ctx->opcode & 0x7, (ctx->opcode >> 4) & 1); + gen_op_store_T0_gpr(rd); + opn = "mftr"; + break; + case OPC_MTTR: + check_insn(env, ctx, ASE_MT); + GEN_LOAD_REG_T0(rt); + gen_mttr(env, ctx, rd, (ctx->opcode >> 5) & 1, + ctx->opcode & 0x7, (ctx->opcode >> 4) & 1); + opn = "mttr"; + break; case OPC_TLBWI: opn = "tlbwi"; - if (!env->do_tlbwi) + if (!env->tlb->do_tlbwi) goto die; gen_op_tlbwi(); break; case OPC_TLBWR: opn = "tlbwr"; - if (!env->do_tlbwr) + if (!env->tlb->do_tlbwr) goto die; gen_op_tlbwr(); break; case OPC_TLBP: opn = "tlbp"; - if (!env->do_tlbp) + if (!env->tlb->do_tlbp) goto die; gen_op_tlbp(); break; case OPC_TLBR: opn = "tlbr"; - if (!env->do_tlbr) + if (!env->tlb->do_tlbr) goto die; gen_op_tlbr(); break; case OPC_ERET: opn = "eret"; + check_insn(env, ctx, ISA_MIPS2); + save_cpu_state(ctx, 1); gen_op_eret(); ctx->bstate = BS_EXCP; break; case OPC_DERET: opn = "deret"; + check_insn(env, ctx, ISA_MIPS32); if (!(ctx->hflags & MIPS_HFLAG_DM)) { MIPS_INVAL(opn); generate_exception(ctx, EXCP_RI); } else { + save_cpu_state(ctx, 1); gen_op_deret(); ctx->bstate = BS_EXCP; } break; case OPC_WAIT: opn = "wait"; + check_insn(env, ctx, ISA_MIPS3 | ISA_MIPS32); /* If we get an exception, we want to restart at next instruction */ ctx->pc += 4; save_cpu_state(ctx, 1); @@ -4113,12 +4854,15 @@ static void gen_cp0 (CPUState *env, DisasContext *ctx, uint32_t opc, int rt, int } /* CP1 Branches (before delay slot) */ -static void gen_compute_branch1 (DisasContext *ctx, uint32_t op, +static void gen_compute_branch1 (CPUState *env, DisasContext *ctx, uint32_t op, int32_t cc, int32_t offset) { target_ulong btarget; const char *opn = "cp1 cond branch"; + if (cc != 0) + check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32); + btarget = ctx->pc + 4 + offset; switch (op) { @@ -4183,35 +4927,33 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs) case OPC_MFC1: GEN_LOAD_FREG_FTN(WT0, fs); gen_op_mfc1(); - GEN_STORE_TN_REG(rt, T0); + GEN_STORE_T0_REG(rt); opn = "mfc1"; break; case OPC_MTC1: - GEN_LOAD_REG_TN(T0, rt); + GEN_LOAD_REG_T0(rt); gen_op_mtc1(); GEN_STORE_FTN_FREG(fs, WT0); opn = "mtc1"; break; case OPC_CFC1: - GEN_LOAD_IMM_TN(T1, fs); - gen_op_cfc1(); - GEN_STORE_TN_REG(rt, T0); + gen_op_cfc1(fs); + GEN_STORE_T0_REG(rt); opn = "cfc1"; break; case OPC_CTC1: - GEN_LOAD_IMM_TN(T1, fs); - GEN_LOAD_REG_TN(T0, rt); - gen_op_ctc1(); + GEN_LOAD_REG_T0(rt); + gen_op_ctc1(fs); opn = "ctc1"; break; case OPC_DMFC1: GEN_LOAD_FREG_FTN(DT0, fs); gen_op_dmfc1(); - GEN_STORE_TN_REG(rt, T0); + GEN_STORE_T0_REG(rt); opn = "dmfc1"; break; case OPC_DMTC1: - GEN_LOAD_REG_TN(T0, rt); + GEN_LOAD_REG_T0(rt); gen_op_dmtc1(); GEN_STORE_FTN_FREG(fs, DT0); opn = "dmtc1"; @@ -4219,11 +4961,11 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs) case OPC_MFHC1: GEN_LOAD_FREG_FTN(WTH0, fs); gen_op_mfhc1(); - GEN_STORE_TN_REG(rt, T0); + GEN_STORE_T0_REG(rt); opn = "mfhc1"; break; case OPC_MTHC1: - GEN_LOAD_REG_TN(T0, rt); + GEN_LOAD_REG_T0(rt); gen_op_mthc1(); GEN_STORE_FTN_FREG(fs, WTH0); opn = "mthc1"; @@ -4240,8 +4982,8 @@ static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf) { uint32_t ccbit; - GEN_LOAD_REG_TN(T0, rd); - GEN_LOAD_REG_TN(T1, rs); + GEN_LOAD_REG_T0(rd); + GEN_LOAD_REG_T1(rs); if (cc) { ccbit = 1 << (24 + cc); } else @@ -4250,7 +4992,7 @@ static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf) gen_op_movf(ccbit); else gen_op_movt(ccbit); - GEN_STORE_TN_REG(rd, T0); + GEN_STORE_T0_REG(rd); } #define GEN_MOVCF(fmt) \ @@ -4425,7 +5167,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, opn = "floor.w.s"; break; case FOP(17, 16): - GEN_LOAD_REG_TN(T0, ft); + GEN_LOAD_REG_T0(ft); GEN_LOAD_FREG_FTN(WT0, fs); GEN_LOAD_FREG_FTN(WT2, fd); gen_movcf_s(ctx, (ft >> 2) & 0x7, ft & 0x1); @@ -4433,7 +5175,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, opn = "movcf.s"; break; case FOP(18, 16): - GEN_LOAD_REG_TN(T0, ft); + GEN_LOAD_REG_T0(ft); GEN_LOAD_FREG_FTN(WT0, fs); GEN_LOAD_FREG_FTN(WT2, fd); gen_op_float_movz_s(); @@ -4441,7 +5183,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, opn = "movz.s"; break; case FOP(19, 16): - GEN_LOAD_REG_TN(T0, ft); + GEN_LOAD_REG_T0(ft); GEN_LOAD_FREG_FTN(WT0, fs); GEN_LOAD_FREG_FTN(WT2, fd); gen_op_float_movn_s(); @@ -4449,12 +5191,14 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, opn = "movn.s"; break; case FOP(21, 16): + check_cop1x(ctx); GEN_LOAD_FREG_FTN(WT0, fs); gen_op_float_recip_s(); GEN_STORE_FTN_FREG(fd, WT2); opn = "recip.s"; break; case FOP(22, 16): + check_cop1x(ctx); GEN_LOAD_FREG_FTN(WT0, fs); gen_op_float_rsqrt_s(); GEN_STORE_FTN_FREG(fd, WT2); @@ -4485,7 +5229,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, case FOP(31, 16): check_cp1_64bitmode(ctx); GEN_LOAD_FREG_FTN(WT0, fs); - GEN_LOAD_FREG_FTN(WT2, fd); + GEN_LOAD_FREG_FTN(WT2, ft); gen_op_float_rsqrt2_s(); GEN_STORE_FTN_FREG(fd, WT2); opn = "rsqrt2.s"; @@ -4537,7 +5281,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, GEN_LOAD_FREG_FTN(WT0, fs); GEN_LOAD_FREG_FTN(WT1, ft); if (ctx->opcode & (1 << 6)) { - check_cp1_64bitmode(ctx); + check_cop1x(ctx); gen_cmpabs_s(func-48, cc); opn = condnames_abs[func-48]; } else { @@ -4666,7 +5410,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, opn = "floor.w.d"; break; case FOP(17, 17): - GEN_LOAD_REG_TN(T0, ft); + GEN_LOAD_REG_T0(ft); GEN_LOAD_FREG_FTN(DT0, fs); GEN_LOAD_FREG_FTN(DT2, fd); gen_movcf_d(ctx, (ft >> 2) & 0x7, ft & 0x1); @@ -4674,7 +5418,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, opn = "movcf.d"; break; case FOP(18, 17): - GEN_LOAD_REG_TN(T0, ft); + GEN_LOAD_REG_T0(ft); GEN_LOAD_FREG_FTN(DT0, fs); GEN_LOAD_FREG_FTN(DT2, fd); gen_op_float_movz_d(); @@ -4682,7 +5426,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, opn = "movz.d"; break; case FOP(19, 17): - GEN_LOAD_REG_TN(T0, ft); + GEN_LOAD_REG_T0(ft); GEN_LOAD_FREG_FTN(DT0, fs); GEN_LOAD_FREG_FTN(DT2, fd); gen_op_float_movn_d(); @@ -4690,14 +5434,14 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, opn = "movn.d"; break; case FOP(21, 17): - check_cp1_registers(ctx, fs | fd); + check_cp1_64bitmode(ctx); GEN_LOAD_FREG_FTN(DT0, fs); gen_op_float_recip_d(); GEN_STORE_FTN_FREG(fd, DT2); opn = "recip.d"; break; case FOP(22, 17): - check_cp1_registers(ctx, fs | fd); + check_cp1_64bitmode(ctx); GEN_LOAD_FREG_FTN(DT0, fs); gen_op_float_rsqrt_d(); GEN_STORE_FTN_FREG(fd, DT2); @@ -4752,7 +5496,8 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, GEN_LOAD_FREG_FTN(DT0, fs); GEN_LOAD_FREG_FTN(DT1, ft); if (ctx->opcode & (1 << 6)) { - check_cp1_64bitmode(ctx); + check_cop1x(ctx); + check_cp1_registers(ctx, fs | ft); gen_cmpabs_d(func-48, cc); opn = condnames_abs[func-48]; } else { @@ -4810,7 +5555,6 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, opn = "cvt.d.l"; break; case FOP(38, 20): - case FOP(38, 21): check_cp1_64bitmode(ctx); GEN_LOAD_FREG_FTN(WT0, fs); GEN_LOAD_FREG_FTN(WTH0, fs); @@ -4881,7 +5625,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, break; case FOP(17, 22): check_cp1_64bitmode(ctx); - GEN_LOAD_REG_TN(T0, ft); + GEN_LOAD_REG_T0(ft); GEN_LOAD_FREG_FTN(WT0, fs); GEN_LOAD_FREG_FTN(WTH0, fs); GEN_LOAD_FREG_FTN(WT2, fd); @@ -4893,7 +5637,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, break; case FOP(18, 22): check_cp1_64bitmode(ctx); - GEN_LOAD_REG_TN(T0, ft); + GEN_LOAD_REG_T0(ft); GEN_LOAD_FREG_FTN(WT0, fs); GEN_LOAD_FREG_FTN(WTH0, fs); GEN_LOAD_FREG_FTN(WT2, fd); @@ -4905,7 +5649,7 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, break; case FOP(19, 22): check_cp1_64bitmode(ctx); - GEN_LOAD_REG_TN(T0, ft); + GEN_LOAD_REG_T0(ft); GEN_LOAD_FREG_FTN(WT0, fs); GEN_LOAD_FREG_FTN(WTH0, fs); GEN_LOAD_FREG_FTN(WT2, fd); @@ -4970,8 +5714,8 @@ static void gen_farith (DisasContext *ctx, uint32_t op1, check_cp1_64bitmode(ctx); GEN_LOAD_FREG_FTN(WT0, fs); GEN_LOAD_FREG_FTN(WTH0, fs); - GEN_LOAD_FREG_FTN(WT2, fd); - GEN_LOAD_FREG_FTN(WTH2, fd); + GEN_LOAD_FREG_FTN(WT2, ft); + GEN_LOAD_FREG_FTN(WTH2, ft); gen_op_float_rsqrt2_ps(); GEN_STORE_FTN_FREG(fd, WT2); GEN_STORE_FTN_FREG(fd, WTH2); @@ -5086,52 +5830,57 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc, const char *opn = "extended float load/store"; int store = 0; - /* All of those work only on 64bit FPUs. */ - check_cp1_64bitmode(ctx); if (base == 0) { if (index == 0) gen_op_reset_T0(); else - GEN_LOAD_REG_TN(T0, index); + GEN_LOAD_REG_T0(index); } else if (index == 0) { - GEN_LOAD_REG_TN(T0, base); + GEN_LOAD_REG_T0(base); } else { - GEN_LOAD_REG_TN(T0, base); - GEN_LOAD_REG_TN(T1, index); + GEN_LOAD_REG_T0(base); + GEN_LOAD_REG_T1(index); gen_op_addr_add(); } /* Don't do NOP if destination is zero: we must perform the actual - * memory access - */ + memory access. */ switch (opc) { case OPC_LWXC1: + check_cop1x(ctx); op_ldst(lwc1); GEN_STORE_FTN_FREG(fd, WT0); opn = "lwxc1"; break; case OPC_LDXC1: + check_cop1x(ctx); + check_cp1_registers(ctx, fd); op_ldst(ldc1); GEN_STORE_FTN_FREG(fd, DT0); opn = "ldxc1"; break; case OPC_LUXC1: + check_cp1_64bitmode(ctx); op_ldst(luxc1); GEN_STORE_FTN_FREG(fd, DT0); opn = "luxc1"; break; case OPC_SWXC1: + check_cop1x(ctx); GEN_LOAD_FREG_FTN(WT0, fs); op_ldst(swc1); opn = "swxc1"; store = 1; break; case OPC_SDXC1: + check_cop1x(ctx); + check_cp1_registers(ctx, fs); GEN_LOAD_FREG_FTN(DT0, fs); op_ldst(sdc1); opn = "sdxc1"; store = 1; break; case OPC_SUXC1: + check_cp1_64bitmode(ctx); GEN_LOAD_FREG_FTN(DT0, fs); op_ldst(suxc1); opn = "suxc1"; @@ -5151,11 +5900,10 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, { const char *opn = "flt3_arith"; - /* All of those work only on 64bit FPUs. */ - check_cp1_64bitmode(ctx); switch (opc) { case OPC_ALNV_PS: - GEN_LOAD_REG_TN(T0, fr); + check_cp1_64bitmode(ctx); + GEN_LOAD_REG_T0(fr); GEN_LOAD_FREG_FTN(DT0, fs); GEN_LOAD_FREG_FTN(DT1, ft); gen_op_float_alnv_ps(); @@ -5163,6 +5911,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, opn = "alnv.ps"; break; case OPC_MADD_S: + check_cop1x(ctx); GEN_LOAD_FREG_FTN(WT0, fs); GEN_LOAD_FREG_FTN(WT1, ft); GEN_LOAD_FREG_FTN(WT2, fr); @@ -5171,6 +5920,8 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, opn = "madd.s"; break; case OPC_MADD_D: + check_cop1x(ctx); + check_cp1_registers(ctx, fd | fs | ft | fr); GEN_LOAD_FREG_FTN(DT0, fs); GEN_LOAD_FREG_FTN(DT1, ft); GEN_LOAD_FREG_FTN(DT2, fr); @@ -5179,6 +5930,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, opn = "madd.d"; break; case OPC_MADD_PS: + check_cp1_64bitmode(ctx); GEN_LOAD_FREG_FTN(WT0, fs); GEN_LOAD_FREG_FTN(WTH0, fs); GEN_LOAD_FREG_FTN(WT1, ft); @@ -5191,6 +5943,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, opn = "madd.ps"; break; case OPC_MSUB_S: + check_cop1x(ctx); GEN_LOAD_FREG_FTN(WT0, fs); GEN_LOAD_FREG_FTN(WT1, ft); GEN_LOAD_FREG_FTN(WT2, fr); @@ -5199,6 +5952,8 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, opn = "msub.s"; break; case OPC_MSUB_D: + check_cop1x(ctx); + check_cp1_registers(ctx, fd | fs | ft | fr); GEN_LOAD_FREG_FTN(DT0, fs); GEN_LOAD_FREG_FTN(DT1, ft); GEN_LOAD_FREG_FTN(DT2, fr); @@ -5207,6 +5962,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, opn = "msub.d"; break; case OPC_MSUB_PS: + check_cp1_64bitmode(ctx); GEN_LOAD_FREG_FTN(WT0, fs); GEN_LOAD_FREG_FTN(WTH0, fs); GEN_LOAD_FREG_FTN(WT1, ft); @@ -5219,6 +5975,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, opn = "msub.ps"; break; case OPC_NMADD_S: + check_cop1x(ctx); GEN_LOAD_FREG_FTN(WT0, fs); GEN_LOAD_FREG_FTN(WT1, ft); GEN_LOAD_FREG_FTN(WT2, fr); @@ -5227,6 +5984,8 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, opn = "nmadd.s"; break; case OPC_NMADD_D: + check_cop1x(ctx); + check_cp1_registers(ctx, fd | fs | ft | fr); GEN_LOAD_FREG_FTN(DT0, fs); GEN_LOAD_FREG_FTN(DT1, ft); GEN_LOAD_FREG_FTN(DT2, fr); @@ -5235,6 +5994,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, opn = "nmadd.d"; break; case OPC_NMADD_PS: + check_cp1_64bitmode(ctx); GEN_LOAD_FREG_FTN(WT0, fs); GEN_LOAD_FREG_FTN(WTH0, fs); GEN_LOAD_FREG_FTN(WT1, ft); @@ -5247,6 +6007,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, opn = "nmadd.ps"; break; case OPC_NMSUB_S: + check_cop1x(ctx); GEN_LOAD_FREG_FTN(WT0, fs); GEN_LOAD_FREG_FTN(WT1, ft); GEN_LOAD_FREG_FTN(WT2, fr); @@ -5255,6 +6016,8 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, opn = "nmsub.s"; break; case OPC_NMSUB_D: + check_cop1x(ctx); + check_cp1_registers(ctx, fd | fs | ft | fr); GEN_LOAD_FREG_FTN(DT0, fs); GEN_LOAD_FREG_FTN(DT1, ft); GEN_LOAD_FREG_FTN(DT2, fr); @@ -5263,6 +6026,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, opn = "nmsub.d"; break; case OPC_NMSUB_PS: + check_cp1_64bitmode(ctx); GEN_LOAD_FREG_FTN(WT0, fs); GEN_LOAD_FREG_FTN(WTH0, fs); GEN_LOAD_FREG_FTN(WT1, ft); @@ -5287,10 +6051,9 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, /* MIPS16 extension to MIPS32 */ /* SmartMIPS extension to MIPS32 */ -#ifdef TARGET_MIPS64 +#if defined(TARGET_MIPS64) /* MDMX extension to MIPS64 */ -/* MIPS-3D extension to MIPS64 */ #endif @@ -5330,17 +6093,23 @@ static void decode_opc (CPUState *env, DisasContext *ctx) switch (op1) { case OPC_SLL: /* Arithmetic with immediate */ case OPC_SRL ... OPC_SRA: - gen_arith_imm(ctx, op1, rd, rt, sa); + gen_arith_imm(env, ctx, op1, rd, rt, sa); break; + case OPC_MOVZ ... OPC_MOVN: + check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32); case OPC_SLLV: /* Arithmetic */ case OPC_SRLV ... OPC_SRAV: - case OPC_MOVZ ... OPC_MOVN: case OPC_ADD ... OPC_NOR: case OPC_SLT ... OPC_SLTU: - gen_arith(ctx, op1, rd, rs, rt); + gen_arith(env, ctx, op1, rd, rs, rt); break; case OPC_MULT ... OPC_DIVU: - gen_muldiv(ctx, op1, rs, rt); + if (sa) { + check_insn(env, ctx, INSN_VR54XX); + op1 = MASK_MUL_VR54XX(ctx->opcode); + gen_mul_vr54xx(ctx, op1, rd, rs, rt); + } else + gen_muldiv(ctx, op1, rs, rt); break; case OPC_JR ... OPC_JALR: gen_compute_branch(ctx, op1, rs, rd, sa); @@ -5369,10 +6138,6 @@ static void decode_opc (CPUState *env, DisasContext *ctx) generate_exception(ctx, EXCP_SYSCALL); break; case OPC_BREAK: - /* XXX: Hack to work around wrong handling of self-modifying code. */ - ctx->pc += 4; - save_cpu_state(ctx, 1); - ctx->pc -= 4; generate_exception(ctx, EXCP_BREAK); break; case OPC_SPIM: @@ -5386,10 +6151,11 @@ static void decode_opc (CPUState *env, DisasContext *ctx) #endif break; case OPC_SYNC: - /* Treat as a noop. */ + /* Treat as NOP. */ break; case OPC_MOVCI: + check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32); if (env->CP0_Config1 & (1 << CP0C1_FP)) { save_cpu_state(ctx, 1); check_cp1_enabled(ctx); @@ -5400,26 +6166,26 @@ static void decode_opc (CPUState *env, DisasContext *ctx) } break; -#ifdef TARGET_MIPS64 +#if defined(TARGET_MIPS64) /* MIPS64 specific opcodes */ case OPC_DSLL: case OPC_DSRL ... OPC_DSRA: case OPC_DSLL32: case OPC_DSRL32 ... OPC_DSRA32: - if (!(ctx->hflags & MIPS_HFLAG_64)) - generate_exception(ctx, EXCP_RI); - gen_arith_imm(ctx, op1, rd, rt, sa); + check_insn(env, ctx, ISA_MIPS3); + check_mips_64(ctx); + gen_arith_imm(env, ctx, op1, rd, rt, sa); break; case OPC_DSLLV: case OPC_DSRLV ... OPC_DSRAV: case OPC_DADD ... OPC_DSUBU: - if (!(ctx->hflags & MIPS_HFLAG_64)) - generate_exception(ctx, EXCP_RI); - gen_arith(ctx, op1, rd, rs, rt); + check_insn(env, ctx, ISA_MIPS3); + check_mips_64(ctx); + gen_arith(env, ctx, op1, rd, rs, rt); break; case OPC_DMULT ... OPC_DDIVU: - if (!(ctx->hflags & MIPS_HFLAG_64)) - generate_exception(ctx, EXCP_RI); + check_insn(env, ctx, ISA_MIPS3); + check_mips_64(ctx); gen_muldiv(ctx, op1, rs, rt); break; #endif @@ -5434,29 +6200,32 @@ static void decode_opc (CPUState *env, DisasContext *ctx) switch (op1) { case OPC_MADD ... OPC_MADDU: /* Multiply and add/sub */ case OPC_MSUB ... OPC_MSUBU: + check_insn(env, ctx, ISA_MIPS32); gen_muldiv(ctx, op1, rs, rt); break; case OPC_MUL: - gen_arith(ctx, op1, rd, rs, rt); + gen_arith(env, ctx, op1, rd, rs, rt); break; case OPC_CLZ ... OPC_CLO: + check_insn(env, ctx, ISA_MIPS32); gen_cl(ctx, op1, rd, rs); break; case OPC_SDBBP: /* XXX: not clear which exception should be raised * when in debug mode... */ + check_insn(env, ctx, ISA_MIPS32); if (!(ctx->hflags & MIPS_HFLAG_DM)) { generate_exception(ctx, EXCP_DBp); } else { generate_exception(ctx, EXCP_DBp); } - /* Treat as a noop */ + /* Treat as NOP. */ break; -#ifdef TARGET_MIPS64 +#if defined(TARGET_MIPS64) case OPC_DCLZ ... OPC_DCLO: - if (!(ctx->hflags & MIPS_HFLAG_64)) - generate_exception(ctx, EXCP_RI); + check_insn(env, ctx, ISA_MIPS64); + check_mips_64(ctx); gen_cl(ctx, op1, rd, rs); break; #endif @@ -5471,21 +6240,23 @@ static void decode_opc (CPUState *env, DisasContext *ctx) switch (op1) { case OPC_EXT: case OPC_INS: + check_insn(env, ctx, ISA_MIPS32R2); gen_bitops(ctx, op1, rt, rs, sa, rd); break; case OPC_BSHFL: + check_insn(env, ctx, ISA_MIPS32R2); op2 = MASK_BSHFL(ctx->opcode); switch (op2) { case OPC_WSBH: - GEN_LOAD_REG_TN(T1, rt); + GEN_LOAD_REG_T1(rt); gen_op_wsbh(); break; case OPC_SEB: - GEN_LOAD_REG_TN(T1, rt); + GEN_LOAD_REG_T1(rt); gen_op_seb(); break; case OPC_SEH: - GEN_LOAD_REG_TN(T1, rt); + GEN_LOAD_REG_T1(rt); gen_op_seh(); break; default: /* Invalid */ @@ -5493,9 +6264,10 @@ static void decode_opc (CPUState *env, DisasContext *ctx) generate_exception(ctx, EXCP_RI); break; } - GEN_STORE_TN_REG(rd, T0); + GEN_STORE_T0_REG(rd); break; case OPC_RDHWR: + check_insn(env, ctx, ISA_MIPS32R2); switch (rd) { case 0: save_cpu_state(ctx, 1); @@ -5515,7 +6287,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx) break; case 29: #if defined (CONFIG_USER_ONLY) - gen_op_tls_value (); + gen_op_tls_value(); break; #endif default: /* Invalid */ @@ -5523,26 +6295,38 @@ static void decode_opc (CPUState *env, DisasContext *ctx) generate_exception(ctx, EXCP_RI); break; } - GEN_STORE_TN_REG(rt, T0); + GEN_STORE_T0_REG(rt); + break; + case OPC_FORK: + check_insn(env, ctx, ASE_MT); + GEN_LOAD_REG_T0(rt); + GEN_LOAD_REG_T1(rs); + gen_op_fork(); break; -#ifdef TARGET_MIPS64 + case OPC_YIELD: + check_insn(env, ctx, ASE_MT); + GEN_LOAD_REG_T0(rs); + gen_op_yield(); + GEN_STORE_T0_REG(rd); + break; +#if defined(TARGET_MIPS64) case OPC_DEXTM ... OPC_DEXT: case OPC_DINSM ... OPC_DINS: - if (!(ctx->hflags & MIPS_HFLAG_64)) - generate_exception(ctx, EXCP_RI); + check_insn(env, ctx, ISA_MIPS64R2); + check_mips_64(ctx); gen_bitops(ctx, op1, rt, rs, sa, rd); break; case OPC_DBSHFL: - if (!(ctx->hflags & MIPS_HFLAG_64)) - generate_exception(ctx, EXCP_RI); + check_insn(env, ctx, ISA_MIPS64R2); + check_mips_64(ctx); op2 = MASK_DBSHFL(ctx->opcode); switch (op2) { case OPC_DSBH: - GEN_LOAD_REG_TN(T1, rt); + GEN_LOAD_REG_T1(rt); gen_op_dsbh(); break; case OPC_DSHD: - GEN_LOAD_REG_TN(T1, rt); + GEN_LOAD_REG_T1(rt); gen_op_dshd(); break; default: /* Invalid */ @@ -5550,7 +6334,8 @@ static void decode_opc (CPUState *env, DisasContext *ctx) generate_exception(ctx, EXCP_RI); break; } - GEN_STORE_TN_REG(rd, T0); + GEN_STORE_T0_REG(rd); + break; #endif default: /* Invalid */ MIPS_INVAL("special3"); @@ -5570,7 +6355,8 @@ static void decode_opc (CPUState *env, DisasContext *ctx) gen_trap(ctx, op1, rs, -1, imm); break; case OPC_SYNCI: - /* treat as noop */ + check_insn(env, ctx, ISA_MIPS32R2); + /* Treat as NOP. */ break; default: /* Invalid */ MIPS_INVAL("regimm"); @@ -5579,13 +6365,14 @@ static void decode_opc (CPUState *env, DisasContext *ctx) } break; case OPC_CP0: - save_cpu_state(ctx, 1); - gen_op_cp0_enabled(); + check_cp0_enabled(ctx); op1 = MASK_CP0(ctx->opcode); switch (op1) { case OPC_MFC0: case OPC_MTC0: -#ifdef TARGET_MIPS64 + case OPC_MFTR: + case OPC_MTTR: +#if defined(TARGET_MIPS64) case OPC_DMFC0: case OPC_DMTC0: #endif @@ -5597,12 +6384,32 @@ static void decode_opc (CPUState *env, DisasContext *ctx) case OPC_MFMC0: op2 = MASK_MFMC0(ctx->opcode); switch (op2) { + case OPC_DMT: + check_insn(env, ctx, ASE_MT); + gen_op_dmt(); + break; + case OPC_EMT: + check_insn(env, ctx, ASE_MT); + gen_op_emt(); + break; + case OPC_DVPE: + check_insn(env, ctx, ASE_MT); + gen_op_dvpe(); + break; + case OPC_EVPE: + check_insn(env, ctx, ASE_MT); + gen_op_evpe(); + break; case OPC_DI: + check_insn(env, ctx, ISA_MIPS32R2); + save_cpu_state(ctx, 1); gen_op_di(); /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; break; case OPC_EI: + check_insn(env, ctx, ISA_MIPS32R2); + save_cpu_state(ctx, 1); gen_op_ei(); /* Stop translation as we may have switched the execution mode */ ctx->bstate = BS_STOP; @@ -5612,18 +6419,17 @@ static void decode_opc (CPUState *env, DisasContext *ctx) generate_exception(ctx, EXCP_RI); break; } - GEN_STORE_TN_REG(rt, T0); + GEN_STORE_T0_REG(rt); break; case OPC_RDPGPR: + check_insn(env, ctx, ISA_MIPS32R2); + GEN_LOAD_SRSREG_TN(T0, rt); + GEN_STORE_T0_REG(rd); + break; case OPC_WRPGPR: - if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR)) { - /* Shadow registers not implemented. */ - GEN_LOAD_REG_TN(T0, rt); - GEN_STORE_TN_REG(rd, T0); - } else { - MIPS_INVAL("shadow register move"); - generate_exception(ctx, EXCP_RI); - } + check_insn(env, ctx, ISA_MIPS32R2); + GEN_LOAD_REG_T0(rt); + GEN_STORE_TN_SRSREG(rd, T0); break; default: MIPS_INVAL("cp0"); @@ -5632,7 +6438,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx) } break; case OPC_ADDI ... OPC_LUI: /* Arithmetic with immediate opcode */ - gen_arith_imm(ctx, op, rt, rs, imm); + gen_arith_imm(env, ctx, op, rt, rs, imm); break; case OPC_J ... OPC_JAL: /* Jump */ offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2; @@ -5650,10 +6456,12 @@ static void decode_opc (CPUState *env, DisasContext *ctx) gen_ldst(ctx, op, rt, rs, imm); break; case OPC_CACHE: - /* Treat as a noop */ + check_insn(env, ctx, ISA_MIPS3 | ISA_MIPS32); + /* Treat as NOP. */ break; case OPC_PREF: - /* Treat as a noop */ + check_insn(env, ctx, ISA_MIPS4 | ISA_MIPS32); + /* Treat as NOP. */ break; /* Floating point (COP1). */ @@ -5676,22 +6484,29 @@ static void decode_opc (CPUState *env, DisasContext *ctx) check_cp1_enabled(ctx); op1 = MASK_CP1(ctx->opcode); switch (op1) { + case OPC_MFHC1: + case OPC_MTHC1: + check_insn(env, ctx, ISA_MIPS32R2); case OPC_MFC1: case OPC_CFC1: case OPC_MTC1: case OPC_CTC1: -#ifdef TARGET_MIPS64 + gen_cp1(ctx, op1, rt, rd); + break; +#if defined(TARGET_MIPS64) case OPC_DMFC1: case OPC_DMTC1: -#endif - case OPC_MFHC1: - case OPC_MTHC1: + check_insn(env, ctx, ISA_MIPS3); gen_cp1(ctx, op1, rt, rd); break; - case OPC_BC1: +#endif case OPC_BC1ANY2: case OPC_BC1ANY4: - gen_compute_branch1(ctx, MASK_BC1(ctx->opcode), + check_cop1x(ctx); + check_insn(env, ctx, ASE_MIPS3D); + /* fall through */ + case OPC_BC1: + gen_compute_branch1(env, ctx, MASK_BC1(ctx->opcode), (rt >> 2) & 0x7, imm << 2); return; case OPC_S_FMT: @@ -5737,7 +6552,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx) gen_flt3_ldst(ctx, op1, sa, rd, rs, rt); break; case OPC_PREFX: - /* treat as noop */ + /* Treat as NOP. */ break; case OPC_ALNV_PS: case OPC_MADD_S: @@ -5764,7 +6579,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx) } break; -#ifdef TARGET_MIPS64 +#if defined(TARGET_MIPS64) /* MIPS64 opcodes */ case OPC_LWU: case OPC_LDL ... OPC_LDR: @@ -5773,24 +6588,22 @@ static void decode_opc (CPUState *env, DisasContext *ctx) case OPC_LD: case OPC_SCD: case OPC_SD: - if (!(ctx->hflags & MIPS_HFLAG_64)) - generate_exception(ctx, EXCP_RI); + check_insn(env, ctx, ISA_MIPS3); + check_mips_64(ctx); gen_ldst(ctx, op, rt, rs, imm); break; case OPC_DADDI ... OPC_DADDIU: - if (!(ctx->hflags & MIPS_HFLAG_64)) - generate_exception(ctx, EXCP_RI); - gen_arith_imm(ctx, op, rt, rs, imm); + check_insn(env, ctx, ISA_MIPS3); + check_mips_64(ctx); + gen_arith_imm(env, ctx, op, rt, rs, imm); break; #endif -#ifdef MIPS_HAS_MIPS16 case OPC_JALX: + check_insn(env, ctx, ASE_MIPS16); /* MIPS16: Not implemented. */ -#endif -#ifdef MIPS_HAS_MDMX case OPC_MDMX: + check_insn(env, ctx, ASE_MDMX); /* MDMX: Not implemented. */ -#endif default: /* Invalid */ MIPS_INVAL("major opcode"); generate_exception(ctx, EXCP_RI); @@ -5839,11 +6652,11 @@ static void decode_opc (CPUState *env, DisasContext *ctx) } } -static inline int +static always_inline int gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb, int search_pc) { - DisasContext ctx, *ctxp = &ctx; + DisasContext ctx; target_ulong pc_start; uint16_t *gen_opc_end; int j, lj = -1; @@ -5861,12 +6674,12 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb, ctx.tb = tb; ctx.bstate = BS_NONE; /* Restore delay slot state from the tb context. */ - ctx.hflags = tb->flags; + ctx.hflags = (uint32_t)tb->flags; /* FIXME: maybe use 64 bits here? */ restore_cpu_state(env, &ctx); #if defined(CONFIG_USER_ONLY) - ctx.mem_idx = 0; + ctx.mem_idx = MIPS_HFLAG_UM; #else - ctx.mem_idx = !((ctx.hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM); + ctx.mem_idx = ctx.hflags & MIPS_HFLAG_KSU; #endif #ifdef DEBUG_DISAS if (loglevel & CPU_LOG_TB_CPU) { @@ -5877,16 +6690,19 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb, #endif #ifdef MIPS_DEBUG_DISAS if (loglevel & CPU_LOG_TB_IN_ASM) - fprintf(logfile, "\ntb %p super %d cond %04x\n", + fprintf(logfile, "\ntb %p idx %d hflags %04x\n", tb, ctx.mem_idx, ctx.hflags); #endif while (ctx.bstate == BS_NONE && gen_opc_ptr < gen_opc_end) { if (env->nb_breakpoints > 0) { for(j = 0; j < env->nb_breakpoints; j++) { if (env->breakpoints[j] == ctx.pc) { - save_cpu_state(ctxp, 1); + save_cpu_state(&ctx, 1); ctx.bstate = BS_BRANCH; gen_op_debug(); + /* Include the breakpoint location or the tb won't + * be flushed when it must be. */ + ctx.pc += 4; goto done_generating; } } @@ -5918,7 +6734,7 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb, #endif } if (env->singlestep_enabled) { - save_cpu_state(ctxp, ctx.bstate == BS_NONE); + save_cpu_state(&ctx, ctx.bstate == BS_NONE); gen_op_debug(); } else { switch (ctx.bstate) { @@ -5927,7 +6743,7 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb, gen_goto_tb(&ctx, 0, ctx.pc); break; case BS_NONE: - save_cpu_state(ctxp, 0); + save_cpu_state(&ctx, 0); gen_goto_tb(&ctx, 0, ctx.pc); break; case BS_EXCP: @@ -5941,13 +6757,13 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb, } } done_generating: + ctx.last_T0_store = NULL; *gen_opc_ptr = INDEX_op_end; if (search_pc) { j = gen_opc_ptr - gen_opc_buf; lj++; while (lj <= j) gen_opc_instr_start[lj++] = 0; - tb->size = 0; } else { tb->size = ctx.pc - pc_start; } @@ -5970,7 +6786,7 @@ done_generating: fprintf(logfile, "---------------- %d %08x\n", ctx.bstate, ctx.hflags); } #endif - + return 0; } @@ -5984,7 +6800,7 @@ int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb) return gen_intermediate_code_internal(env, tb, 1); } -void fpu_dump_state(CPUState *env, FILE *f, +void fpu_dump_state(CPUState *env, FILE *f, int (*fpu_fprintf)(FILE *f, const char *fmt, ...), int flags) { @@ -6009,13 +6825,14 @@ void fpu_dump_state(CPUState *env, FILE *f, fpu_fprintf(f, "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%08x(0x%02x)\n", - env->fcr0, env->fcr31, is_fpu64, env->fp_status, get_float_exception_flags(&env->fp_status)); - fpu_fprintf(f, "FT0: "); printfpr(&env->ft0); - fpu_fprintf(f, "FT1: "); printfpr(&env->ft1); - fpu_fprintf(f, "FT2: "); printfpr(&env->ft2); + env->fpu->fcr0, env->fpu->fcr31, is_fpu64, env->fpu->fp_status, + get_float_exception_flags(&env->fpu->fp_status)); + fpu_fprintf(f, "FT0: "); printfpr(&env->fpu->ft0); + fpu_fprintf(f, "FT1: "); printfpr(&env->fpu->ft1); + fpu_fprintf(f, "FT2: "); printfpr(&env->fpu->ft2); for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) { fpu_fprintf(f, "%3s: ", fregnames[i]); - printfpr(&env->fpr[i]); + printfpr(&env->fpu->fpr[i]); } #undef printfpr @@ -6023,9 +6840,9 @@ void fpu_dump_state(CPUState *env, FILE *f, void dump_fpu (CPUState *env) { - if (loglevel) { + if (loglevel) { fprintf(logfile, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx " LO=0x" TARGET_FMT_lx " ds %04x " TARGET_FMT_lx " %d\n", - env->PC, env->HI, env->LO, env->hflags, env->btarget, env->bcond); + env->PC[env->current_tc], env->HI[0][env->current_tc], env->LO[0][env->current_tc], env->hflags, env->btarget, env->bcond); fpu_dump_state(env, logfile, fprintf, 0); } } @@ -6042,18 +6859,18 @@ void cpu_mips_check_sign_extensions (CPUState *env, FILE *f, { int i; - if (!SIGN_EXT_P(env->PC)) - cpu_fprintf(f, "BROKEN: pc=0x" TARGET_FMT_lx "\n", env->PC); - if (!SIGN_EXT_P(env->HI)) - cpu_fprintf(f, "BROKEN: HI=0x" TARGET_FMT_lx "\n", env->HI); - if (!SIGN_EXT_P(env->LO)) - cpu_fprintf(f, "BROKEN: LO=0x" TARGET_FMT_lx "\n", env->LO); + if (!SIGN_EXT_P(env->PC[env->current_tc])) + cpu_fprintf(f, "BROKEN: pc=0x" TARGET_FMT_lx "\n", env->PC[env->current_tc]); + if (!SIGN_EXT_P(env->HI[0][env->current_tc])) + cpu_fprintf(f, "BROKEN: HI=0x" TARGET_FMT_lx "\n", env->HI[0][env->current_tc]); + if (!SIGN_EXT_P(env->LO[0][env->current_tc])) + cpu_fprintf(f, "BROKEN: LO=0x" TARGET_FMT_lx "\n", env->LO[0][env->current_tc]); if (!SIGN_EXT_P(env->btarget)) cpu_fprintf(f, "BROKEN: btarget=0x" TARGET_FMT_lx "\n", env->btarget); for (i = 0; i < 32; i++) { - if (!SIGN_EXT_P(env->gpr[i])) - cpu_fprintf(f, "BROKEN: %s=0x" TARGET_FMT_lx "\n", regnames[i], env->gpr[i]); + if (!SIGN_EXT_P(env->gpr[i][env->current_tc])) + cpu_fprintf(f, "BROKEN: %s=0x" TARGET_FMT_lx "\n", regnames[i], env->gpr[i][env->current_tc]); } if (!SIGN_EXT_P(env->CP0_EPC)) @@ -6063,18 +6880,18 @@ void cpu_mips_check_sign_extensions (CPUState *env, FILE *f, } #endif -void cpu_dump_state (CPUState *env, FILE *f, +void cpu_dump_state (CPUState *env, FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...), int flags) { int i; - + cpu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx " LO=0x" TARGET_FMT_lx " ds %04x " TARGET_FMT_lx " %d\n", - env->PC, env->HI, env->LO, env->hflags, env->btarget, env->bcond); + env->PC[env->current_tc], env->HI[env->current_tc], env->LO[env->current_tc], env->hflags, env->btarget, env->bcond); for (i = 0; i < 32; i++) { if ((i & 3) == 0) cpu_fprintf(f, "GPR%02d:", i); - cpu_fprintf(f, " %s " TARGET_FMT_lx, regnames[i], env->gpr[i]); + cpu_fprintf(f, " %s " TARGET_FMT_lx, regnames[i], env->gpr[i][env->current_tc]); if ((i & 3) == 3) cpu_fprintf(f, "\n"); } @@ -6090,14 +6907,23 @@ void cpu_dump_state (CPUState *env, FILE *f, #endif } -CPUMIPSState *cpu_mips_init (void) +#include "translate_init.c" + +CPUMIPSState *cpu_mips_init (const char *cpu_model) { CPUMIPSState *env; + const mips_def_t *def; + def = cpu_mips_find_by_name(cpu_model); + if (!def) + return NULL; env = qemu_mallocz(sizeof(CPUMIPSState)); if (!env) return NULL; + env->cpu_model = def; + cpu_exec_init(env); + env->cpu_model_str = cpu_model; cpu_reset(env); return env; } @@ -6113,16 +6939,11 @@ void cpu_reset (CPUMIPSState *env) if (env->hflags & MIPS_HFLAG_BMASK) { /* If the exception was raised from a delay slot, * come back to the jump. */ - env->CP0_ErrorEPC = env->PC - 4; + env->CP0_ErrorEPC = env->PC[env->current_tc] - 4; } else { - env->CP0_ErrorEPC = env->PC; + env->CP0_ErrorEPC = env->PC[env->current_tc]; } -#ifdef TARGET_MIPS64 - env->hflags = MIPS_HFLAG_64; -#else - env->hflags = 0; -#endif - env->PC = (int32_t)0xBFC00000; + env->PC[env->current_tc] = (int32_t)0xBFC00000; env->CP0_Wired = 0; /* SMP not implemented */ env->CP0_EBase = 0x80000000; @@ -6145,9 +6966,10 @@ void cpu_reset (CPUMIPSState *env) #endif env->exception_index = EXCP_NONE; #if defined(CONFIG_USER_ONLY) - env->hflags |= MIPS_HFLAG_UM; + env->hflags = MIPS_HFLAG_UM; env->user_mode_only = 1; +#else + env->hflags = MIPS_HFLAG_CP0; #endif + cpu_mips_register(env, env->cpu_model); } - -#include "translate_init.c"