X-Git-Url: http://vcs.maemo.org/git/?a=blobdiff_plain;f=target-alpha%2Ftranslate.c;h=5c88a12a999776b520b08311b98e11ac289b4cdb;hb=1304ca878a4e091c193bd4ae273e0b5cb6142237;hp=6b2c7b206ece5211143c43df45fabf704e1d7163;hpb=a1cf28f469883f89e83d6026986254806e88c235;p=qemu diff --git a/target-alpha/translate.c b/target-alpha/translate.c index 6b2c7b2..5c88a12 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -31,7 +31,6 @@ #include "qemu-common.h" #define DO_SINGLE_STEP -#define GENERATE_NOP #define ALPHA_DEBUG_DISAS #define DO_TB_FLUSH @@ -48,13 +47,12 @@ struct DisasContext { /* global register indexes */ static TCGv cpu_env; static TCGv cpu_ir[31]; +static TCGv cpu_fir[31]; static TCGv cpu_pc; - -/* dyngen register indexes */ -static TCGv cpu_T[3]; +static TCGv cpu_lock; /* register names */ -static char cpu_reg_names[10*4+21*5]; +static char cpu_reg_names[10*4+21*5 + 10*5+21*6]; #include "gen-icount.h" @@ -69,30 +67,25 @@ static void alpha_translate_init(void) cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env"); -#if TARGET_LONG_BITS > HOST_LONG_BITS - cpu_T[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, - offsetof(CPUState, t0), "T0"); - cpu_T[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, - offsetof(CPUState, t1), "T1"); - cpu_T[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, - offsetof(CPUState, t2), "T2"); -#else - cpu_T[0] = tcg_global_reg_new(TCG_TYPE_I64, TCG_AREG1, "T0"); - cpu_T[1] = tcg_global_reg_new(TCG_TYPE_I64, TCG_AREG2, "T1"); - cpu_T[2] = tcg_global_reg_new(TCG_TYPE_I64, TCG_AREG3, "T2"); -#endif - p = cpu_reg_names; for (i = 0; i < 31; i++) { sprintf(p, "ir%d", i); cpu_ir[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, offsetof(CPUState, ir[i]), p); p += (i < 10) ? 4 : 5; + + sprintf(p, "fir%d", i); + cpu_fir[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, + offsetof(CPUState, fir[i]), p); + p += (i < 10) ? 5 : 6; } cpu_pc = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, offsetof(CPUState, pc), "pc"); + cpu_lock = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0, + offsetof(CPUState, lock), "lock"); + /* register helpers */ #undef DEF_HELPER #define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name); @@ -101,231 +94,169 @@ static void alpha_translate_init(void) done_init = 1; } -static always_inline void gen_op_nop (void) +static always_inline void gen_excp (DisasContext *ctx, + int exception, int error_code) { -#if defined(GENERATE_NOP) - gen_op_no_op(); -#endif -} + TCGv tmp1, tmp2; -#define GEN32(func, NAME) \ -static GenOpFunc *NAME ## _table [32] = { \ -NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \ -NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \ -NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \ -NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \ -NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \ -NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \ -NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \ -NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \ -}; \ -static always_inline void func (int n) \ -{ \ - NAME ## _table[n](); \ + tcg_gen_movi_i64(cpu_pc, ctx->pc); + tmp1 = tcg_const_i32(exception); + tmp2 = tcg_const_i32(error_code); + tcg_gen_helper_0_2(helper_excp, tmp1, tmp2); + tcg_temp_free(tmp2); + tcg_temp_free(tmp1); } -/* FIR moves */ -/* Special hacks for fir31 */ -#define gen_op_load_FT0_fir31 gen_op_reset_FT0 -#define gen_op_load_FT1_fir31 gen_op_reset_FT1 -#define gen_op_load_FT2_fir31 gen_op_reset_FT2 -#define gen_op_store_FT0_fir31 gen_op_nop -#define gen_op_store_FT1_fir31 gen_op_nop -#define gen_op_store_FT2_fir31 gen_op_nop -#define gen_op_cmov_fir31 gen_op_nop -GEN32(gen_op_load_FT0_fir, gen_op_load_FT0_fir); -GEN32(gen_op_load_FT1_fir, gen_op_load_FT1_fir); -GEN32(gen_op_load_FT2_fir, gen_op_load_FT2_fir); -GEN32(gen_op_store_FT0_fir, gen_op_store_FT0_fir); -GEN32(gen_op_store_FT1_fir, gen_op_store_FT1_fir); -GEN32(gen_op_store_FT2_fir, gen_op_store_FT2_fir); -GEN32(gen_op_cmov_fir, gen_op_cmov_fir); - -static always_inline void gen_load_fir (DisasContext *ctx, int firn, int Tn) +static always_inline void gen_invalid (DisasContext *ctx) { - switch (Tn) { - case 0: - gen_op_load_FT0_fir(firn); - break; - case 1: - gen_op_load_FT1_fir(firn); - break; - case 2: - gen_op_load_FT2_fir(firn); - break; - } + gen_excp(ctx, EXCP_OPCDEC, 0); } -static always_inline void gen_store_fir (DisasContext *ctx, int firn, int Tn) +static always_inline void gen_qemu_ldf (TCGv t0, TCGv t1, int flags) { - switch (Tn) { - case 0: - gen_op_store_FT0_fir(firn); - break; - case 1: - gen_op_store_FT1_fir(firn); - break; - case 2: - gen_op_store_FT2_fir(firn); - break; - } + TCGv tmp = tcg_temp_new(TCG_TYPE_I32); + tcg_gen_qemu_ld32u(tmp, t1, flags); + tcg_gen_helper_1_1(helper_memory_to_f, t0, tmp); + tcg_temp_free(tmp); } -/* Memory moves */ -#if defined(CONFIG_USER_ONLY) -#define OP_LD_TABLE(width) \ -static GenOpFunc *gen_op_ld##width[] = { \ - &gen_op_ld##width##_raw, \ -} -#define OP_ST_TABLE(width) \ -static GenOpFunc *gen_op_st##width[] = { \ - &gen_op_st##width##_raw, \ -} -#else -#define OP_LD_TABLE(width) \ -static GenOpFunc *gen_op_ld##width[] = { \ - &gen_op_ld##width##_kernel, \ - &gen_op_ld##width##_executive, \ - &gen_op_ld##width##_supervisor, \ - &gen_op_ld##width##_user, \ -} -#define OP_ST_TABLE(width) \ -static GenOpFunc *gen_op_st##width[] = { \ - &gen_op_st##width##_kernel, \ - &gen_op_st##width##_executive, \ - &gen_op_st##width##_supervisor, \ - &gen_op_st##width##_user, \ -} -#endif - -#define GEN_LD(width) \ -OP_LD_TABLE(width); \ -static always_inline void gen_ld##width (DisasContext *ctx) \ -{ \ - (*gen_op_ld##width[ctx->mem_idx])(); \ -} - -#define GEN_ST(width) \ -OP_ST_TABLE(width); \ -static always_inline void gen_st##width (DisasContext *ctx) \ -{ \ - (*gen_op_st##width[ctx->mem_idx])(); \ +static always_inline void gen_qemu_ldg (TCGv t0, TCGv t1, int flags) +{ + TCGv tmp = tcg_temp_new(TCG_TYPE_I64); + tcg_gen_qemu_ld64(tmp, t1, flags); + tcg_gen_helper_1_1(helper_memory_to_g, t0, tmp); + tcg_temp_free(tmp); } -GEN_LD(bu); -GEN_ST(b); -GEN_LD(wu); -GEN_ST(w); -GEN_LD(l); -GEN_ST(l); -GEN_LD(q); -GEN_ST(q); -GEN_LD(q_u); -GEN_ST(q_u); -GEN_LD(l_l); -GEN_ST(l_c); -GEN_LD(q_l); -GEN_ST(q_c); - -#if 0 /* currently unused */ -GEN_LD(f); -GEN_ST(f); -GEN_LD(g); -GEN_ST(g); -#endif /* 0 */ -GEN_LD(s); -GEN_ST(s); -GEN_LD(t); -GEN_ST(t); - -static always_inline void _gen_op_bcond (DisasContext *ctx) +static always_inline void gen_qemu_lds (TCGv t0, TCGv t1, int flags) { -#if 0 // Qemu does not know how to do this... - gen_op_bcond(ctx->pc); -#else - gen_op_bcond(ctx->pc >> 32, ctx->pc); -#endif + TCGv tmp = tcg_temp_new(TCG_TYPE_I32); + tcg_gen_qemu_ld32u(tmp, t1, flags); + tcg_gen_helper_1_1(helper_memory_to_s, t0, tmp); + tcg_temp_free(tmp); } -static always_inline void gen_excp (DisasContext *ctx, - int exception, int error_code) +static always_inline void gen_qemu_ldl_l (TCGv t0, TCGv t1, int flags) { - TCGv tmp1, tmp2; - - tcg_gen_movi_i64(cpu_pc, ctx->pc); - tmp1 = tcg_const_i32(exception); - tmp2 = tcg_const_i32(error_code); - tcg_gen_helper_0_2(helper_excp, tmp1, tmp2); - tcg_temp_free(tmp2); - tcg_temp_free(tmp1); + tcg_gen_mov_i64(cpu_lock, t1); + tcg_gen_qemu_ld32s(t0, t1, flags); } -static always_inline void gen_invalid (DisasContext *ctx) +static always_inline void gen_qemu_ldq_l (TCGv t0, TCGv t1, int flags) { - gen_excp(ctx, EXCP_OPCDEC, 0); + tcg_gen_mov_i64(cpu_lock, t1); + tcg_gen_qemu_ld64(t0, t1, flags); } static always_inline void gen_load_mem (DisasContext *ctx, - void (*gen_load_op)(DisasContext *ctx), + void (*tcg_gen_qemu_load)(TCGv t0, TCGv t1, int flags), int ra, int rb, int32_t disp16, - int clear) + int fp, int clear) { - if (ra == 31 && disp16 == 0) { - /* UNOP */ - gen_op_nop(); + TCGv addr; + + if (unlikely(ra == 31)) + return; + + addr = tcg_temp_new(TCG_TYPE_I64); + if (rb != 31) { + tcg_gen_addi_i64(addr, cpu_ir[rb], disp16); + if (clear) + tcg_gen_andi_i64(addr, addr, ~0x7); } else { - if (rb != 31) - tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp16); - else - tcg_gen_movi_i64(cpu_T[0], disp16); if (clear) - tcg_gen_andi_i64(cpu_T[0], cpu_T[0], ~0x7); - (*gen_load_op)(ctx); - if (ra != 31) - tcg_gen_mov_i64(cpu_ir[ra], cpu_T[1]); + disp16 &= ~0x7; + tcg_gen_movi_i64(addr, disp16); } + if (fp) + tcg_gen_qemu_load(cpu_fir[ra], addr, ctx->mem_idx); + else + tcg_gen_qemu_load(cpu_ir[ra], addr, ctx->mem_idx); + tcg_temp_free(addr); } -static always_inline void gen_store_mem (DisasContext *ctx, - void (*gen_store_op)(DisasContext *ctx), - int ra, int rb, int32_t disp16, - int clear) +static always_inline void gen_qemu_stf (TCGv t0, TCGv t1, int flags) { - if (rb != 31) - tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp16); - else - tcg_gen_movi_i64(cpu_T[0], disp16); - if (clear) - tcg_gen_andi_i64(cpu_T[0], cpu_T[0], ~0x7); - if (ra != 31) - tcg_gen_mov_i64(cpu_T[1], cpu_ir[ra]); - else - tcg_gen_movi_i64(cpu_T[1], 0); - (*gen_store_op)(ctx); + TCGv tmp = tcg_temp_new(TCG_TYPE_I32); + tcg_gen_helper_1_1(helper_f_to_memory, tmp, t0); + tcg_gen_qemu_st32(tmp, t1, flags); + tcg_temp_free(tmp); } -static always_inline void gen_load_fmem (DisasContext *ctx, - void (*gen_load_fop)(DisasContext *ctx), - int ra, int rb, int32_t disp16) +static always_inline void gen_qemu_stg (TCGv t0, TCGv t1, int flags) { - if (rb != 31) - tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp16); - else - tcg_gen_movi_i64(cpu_T[0], disp16); - (*gen_load_fop)(ctx); - gen_store_fir(ctx, ra, 1); + TCGv tmp = tcg_temp_new(TCG_TYPE_I64); + tcg_gen_helper_1_1(helper_g_to_memory, tmp, t0); + tcg_gen_qemu_st64(tmp, t1, flags); + tcg_temp_free(tmp); } -static always_inline void gen_store_fmem (DisasContext *ctx, - void (*gen_store_fop)(DisasContext *ctx), - int ra, int rb, int32_t disp16) +static always_inline void gen_qemu_sts (TCGv t0, TCGv t1, int flags) { - if (rb != 31) - tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp16); - else - tcg_gen_movi_i64(cpu_T[0], disp16); - gen_load_fir(ctx, ra, 1); - (*gen_store_fop)(ctx); + TCGv tmp = tcg_temp_new(TCG_TYPE_I32); + tcg_gen_helper_1_1(helper_s_to_memory, tmp, t0); + tcg_gen_qemu_st32(tmp, t1, flags); + tcg_temp_free(tmp); +} + +static always_inline void gen_qemu_stl_c (TCGv t0, TCGv t1, int flags) +{ + int l1, l2; + + l1 = gen_new_label(); + l2 = gen_new_label(); + tcg_gen_brcond_i64(TCG_COND_NE, cpu_lock, t1, l1); + tcg_gen_qemu_st32(t0, t1, flags); + tcg_gen_movi_i64(t0, 0); + tcg_gen_br(l2); + gen_set_label(l1); + tcg_gen_movi_i64(t0, 1); + gen_set_label(l2); + tcg_gen_movi_i64(cpu_lock, -1); +} + +static always_inline void gen_qemu_stq_c (TCGv t0, TCGv t1, int flags) +{ + int l1, l2; + + l1 = gen_new_label(); + l2 = gen_new_label(); + tcg_gen_brcond_i64(TCG_COND_NE, cpu_lock, t1, l1); + tcg_gen_qemu_st64(t0, t1, flags); + tcg_gen_movi_i64(t0, 0); + tcg_gen_br(l2); + gen_set_label(l1); + tcg_gen_movi_i64(t0, 1); + gen_set_label(l2); + tcg_gen_movi_i64(cpu_lock, -1); +} + +static always_inline void gen_store_mem (DisasContext *ctx, + void (*tcg_gen_qemu_store)(TCGv t0, TCGv t1, int flags), + int ra, int rb, int32_t disp16, + int fp, int clear) +{ + TCGv addr = tcg_temp_new(TCG_TYPE_I64); + if (rb != 31) { + tcg_gen_addi_i64(addr, cpu_ir[rb], disp16); + if (clear) + tcg_gen_andi_i64(addr, addr, ~0x7); + } else { + if (clear) + disp16 &= ~0x7; + tcg_gen_movi_i64(addr, disp16); + } + if (ra != 31) { + if (fp) + tcg_gen_qemu_store(cpu_fir[ra], addr, ctx->mem_idx); + else + tcg_gen_qemu_store(cpu_ir[ra], addr, ctx->mem_idx); + } else { + TCGv zero = tcg_const_i64(0); + tcg_gen_qemu_store(zero, addr, ctx->mem_idx); + tcg_temp_free(zero); + } + tcg_temp_free(addr); } static always_inline void gen_bcond (DisasContext *ctx, @@ -358,35 +289,30 @@ static always_inline void gen_bcond (DisasContext *ctx, } static always_inline void gen_fbcond (DisasContext *ctx, - void (*gen_test_op)(void), + void* func, int ra, int32_t disp16) { - tcg_gen_movi_i64(cpu_T[1], ctx->pc + (int64_t)(disp16 << 2)); - gen_load_fir(ctx, ra, 0); - (*gen_test_op)(); - _gen_op_bcond(ctx); -} + int l1, l2; + TCGv tmp; -static always_inline void gen_arith3 (DisasContext *ctx, - void (*gen_arith_op)(void), - int ra, int rb, int rc, - int islit, uint8_t lit) -{ - if (ra != 31) - tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]); - else - tcg_gen_movi_i64(cpu_T[0], 0); - if (islit) - tcg_gen_movi_i64(cpu_T[1], lit); - else - tcg_gen_mov_i64(cpu_T[1], cpu_ir[rb]); - (*gen_arith_op)(); - if (rc != 31) - tcg_gen_mov_i64(cpu_ir[rc], cpu_T[0]); + l1 = gen_new_label(); + l2 = gen_new_label(); + if (ra != 31) { + tmp = tcg_temp_new(TCG_TYPE_I64); + tcg_gen_helper_1_1(func, tmp, cpu_fir[ra]); + } else { + tmp = tcg_const_i64(0); + tcg_gen_helper_1_1(func, tmp, tmp); + } + tcg_gen_brcondi_i64(TCG_COND_NE, tmp, 0, l1); + tcg_gen_movi_i64(cpu_pc, ctx->pc); + tcg_gen_br(l2); + gen_set_label(l1); + tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp16 << 2)); + gen_set_label(l2); } -static always_inline void gen_cmov (DisasContext *ctx, - TCGCond inv_cond, +static always_inline void gen_cmov (TCGCond inv_cond, int ra, int rb, int rc, int islit, uint8_t lit, int mask) { @@ -419,55 +345,69 @@ static always_inline void gen_cmov (DisasContext *ctx, gen_set_label(l1); } -static always_inline void gen_farith2 (DisasContext *ctx, - void (*gen_arith_fop)(void), +static always_inline void gen_farith2 (void *helper, int rb, int rc) { - gen_load_fir(ctx, rb, 0); - (*gen_arith_fop)(); - gen_store_fir(ctx, rc, 0); + if (unlikely(rc == 31)) + return; + + if (rb != 31) + tcg_gen_helper_1_1(helper, cpu_fir[rc], cpu_fir[rb]); + else { + TCGv tmp = tcg_const_i64(0); + tcg_gen_helper_1_1(helper, cpu_fir[rc], tmp); + tcg_temp_free(tmp); + } } -static always_inline void gen_farith3 (DisasContext *ctx, - void (*gen_arith_fop)(void), +static always_inline void gen_farith3 (void *helper, int ra, int rb, int rc) { - gen_load_fir(ctx, ra, 0); - gen_load_fir(ctx, rb, 1); - (*gen_arith_fop)(); - gen_store_fir(ctx, rc, 0); + if (unlikely(rc == 31)) + return; + + if (ra != 31) { + if (rb != 31) + tcg_gen_helper_1_2(helper, cpu_fir[rc], cpu_fir[ra], cpu_fir[rb]); + else { + TCGv tmp = tcg_const_i64(0); + tcg_gen_helper_1_2(helper, cpu_fir[rc], cpu_fir[ra], tmp); + tcg_temp_free(tmp); + } + } else { + TCGv tmp = tcg_const_i64(0); + if (rb != 31) + tcg_gen_helper_1_2(helper, cpu_fir[rc], tmp, cpu_fir[rb]); + else + tcg_gen_helper_1_2(helper, cpu_fir[rc], tmp, tmp); + tcg_temp_free(tmp); + } } -static always_inline void gen_fcmov (DisasContext *ctx, - void (*gen_test_fop)(void), +static always_inline void gen_fcmov (void *func, int ra, int rb, int rc) { - gen_load_fir(ctx, ra, 0); - gen_load_fir(ctx, rb, 1); - (*gen_test_fop)(); - gen_op_cmov_fir(rc); -} + int l1; + TCGv tmp; -static always_inline void gen_fti (DisasContext *ctx, - void (*gen_move_fop)(void), - int ra, int rc) -{ - gen_load_fir(ctx, rc, 0); - (*gen_move_fop)(); - if (ra != 31) - tcg_gen_mov_i64(cpu_ir[ra], cpu_T[0]); -} + if (unlikely(rc == 31)) + return; -static always_inline void gen_itf (DisasContext *ctx, - void (*gen_move_fop)(void), - int ra, int rc) -{ - if (ra != 31) - tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]); + l1 = gen_new_label(); + tmp = tcg_temp_new(TCG_TYPE_I64); + if (ra != 31) { + tmp = tcg_temp_new(TCG_TYPE_I64); + tcg_gen_helper_1_1(func, tmp, cpu_fir[ra]); + } else { + tmp = tcg_const_i64(0); + tcg_gen_helper_1_1(func, tmp, tmp); + } + tcg_gen_brcondi_i64(TCG_COND_EQ, tmp, 0, l1); + if (rb != 31) + tcg_gen_mov_i64(cpu_fir[rc], cpu_fir[ra]); else - tcg_gen_movi_i64(cpu_T[0], 0); - (*gen_move_fop)(); - gen_store_fir(ctx, rc, 0); + tcg_gen_movi_i64(cpu_fir[rc], 0); + gen_set_label(l1); } /* EXTWH, EXTWH, EXTLH, EXTQH */ @@ -484,7 +424,7 @@ static always_inline void gen_ext_h(void (*tcg_gen_ext_i64)(TCGv t0, TCGv t1), tcg_gen_shli_i64(cpu_ir[rc], cpu_ir[ra], 64 - ((lit & 7) * 8)); else tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[ra]); - } else { + } else { TCGv tmp1, tmp2; tmp1 = tcg_temp_new(TCG_TYPE_I64); tcg_gen_andi_i64(tmp1, cpu_ir[rb], 7); @@ -518,23 +458,17 @@ static always_inline void gen_ext_l(void (*tcg_gen_ext_i64)(TCGv t0, TCGv t1), tcg_gen_shli_i64(tmp, tmp, 3); tcg_gen_shr_i64(cpu_ir[rc], cpu_ir[ra], tmp); tcg_temp_free(tmp); - } + } if (tcg_gen_ext_i64) tcg_gen_ext_i64(cpu_ir[rc], cpu_ir[rc]); } else tcg_gen_movi_i64(cpu_ir[rc], 0); } -/* Code to call byte manipulation helpers, used by: - INSWH, INSLH, INSQH, INSBL, INSWL, INSLL, INSQL, - MSKWH, MSKLH, MSKQH, MSKBL, MSKWL, MSKLL, MSKQL, - ZAP, ZAPNOT - - WARNING: it assumes that when ra31 is used, the result is 0. -*/ -static always_inline void gen_byte_manipulation(void *helper, - int ra, int rb, int rc, - int islit, uint8_t lit) +/* Code to call arith3 helpers */ +static always_inline void gen_arith3 (void *helper, + int ra, int rb, int rc, + int islit, uint8_t lit) { if (unlikely(rc == 31)) return; @@ -546,8 +480,16 @@ static always_inline void gen_byte_manipulation(void *helper, tcg_temp_free(tmp); } else tcg_gen_helper_1_2(helper, cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); - } else - tcg_gen_movi_i64(cpu_ir[rc], 0); + } else { + TCGv tmp1 = tcg_const_i64(0); + if (islit) { + TCGv tmp2 = tcg_const_i64(lit); + tcg_gen_helper_1_2(helper, cpu_ir[rc], tmp1, tmp2); + tcg_temp_free(tmp2); + } else + tcg_gen_helper_1_2(helper, cpu_ir[rc], tmp1, cpu_ir[rb]); + tcg_temp_free(tmp1); + } } static always_inline void gen_cmp(TCGCond cond, @@ -680,33 +622,29 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) /* LDBU */ if (!(ctx->amask & AMASK_BWX)) goto invalid_opc; - gen_load_mem(ctx, &gen_ldbu, ra, rb, disp16, 0); + gen_load_mem(ctx, &tcg_gen_qemu_ld8u, ra, rb, disp16, 0, 0); break; case 0x0B: /* LDQ_U */ - gen_load_mem(ctx, &gen_ldq_u, ra, rb, disp16, 1); + gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 0, 1); break; case 0x0C: /* LDWU */ if (!(ctx->amask & AMASK_BWX)) goto invalid_opc; - gen_load_mem(ctx, &gen_ldwu, ra, rb, disp16, 0); + gen_load_mem(ctx, &tcg_gen_qemu_ld16u, ra, rb, disp16, 0, 1); break; case 0x0D: /* STW */ - if (!(ctx->amask & AMASK_BWX)) - goto invalid_opc; - gen_store_mem(ctx, &gen_stw, ra, rb, disp16, 0); + gen_store_mem(ctx, &tcg_gen_qemu_st16, ra, rb, disp16, 0, 0); break; case 0x0E: /* STB */ - if (!(ctx->amask & AMASK_BWX)) - goto invalid_opc; - gen_store_mem(ctx, &gen_stb, ra, rb, disp16, 0); + gen_store_mem(ctx, &tcg_gen_qemu_st8, ra, rb, disp16, 0, 0); break; case 0x0F: /* STQ_U */ - gen_store_mem(ctx, &gen_stq_u, ra, rb, disp16, 1); + gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 0, 1); break; case 0x10: switch (fn7) { @@ -791,7 +729,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) break; case 0x0F: /* CMPBGE */ - gen_arith3(ctx, &gen_op_cmpbge, ra, rb, rc, islit, lit); + gen_arith3(helper_cmpbge, ra, rb, rc, islit, lit); break; case 0x12: /* S8ADDL */ @@ -957,11 +895,11 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) break; case 0x40: /* ADDL/V */ - gen_arith3(ctx, &gen_op_addlv, ra, rb, rc, islit, lit); + gen_arith3(helper_addlv, ra, rb, rc, islit, lit); break; case 0x49: /* SUBL/V */ - gen_arith3(ctx, &gen_op_sublv, ra, rb, rc, islit, lit); + gen_arith3(helper_sublv, ra, rb, rc, islit, lit); break; case 0x4D: /* CMPLT */ @@ -969,11 +907,11 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) break; case 0x60: /* ADDQ/V */ - gen_arith3(ctx, &gen_op_addqv, ra, rb, rc, islit, lit); + gen_arith3(helper_addqv, ra, rb, rc, islit, lit); break; case 0x69: /* SUBQ/V */ - gen_arith3(ctx, &gen_op_subqv, ra, rb, rc, islit, lit); + gen_arith3(helper_subqv, ra, rb, rc, islit, lit); break; case 0x6D: /* CMPLE */ @@ -1002,23 +940,19 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) if (ra != 31) { if (islit) tcg_gen_andi_i64(cpu_ir[rc], cpu_ir[ra], ~lit); - else { - TCGv tmp = tcg_temp_new(TCG_TYPE_I64); - tcg_gen_not_i64(tmp, cpu_ir[rb]); - tcg_gen_and_i64(cpu_ir[rc], cpu_ir[ra], tmp); - tcg_temp_free(tmp); - } + else + tcg_gen_andc_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); } else tcg_gen_movi_i64(cpu_ir[rc], 0); } break; case 0x14: /* CMOVLBS */ - gen_cmov(ctx, TCG_COND_EQ, ra, rb, rc, islit, lit, 1); + gen_cmov(TCG_COND_EQ, ra, rb, rc, islit, lit, 1); break; case 0x16: /* CMOVLBC */ - gen_cmov(ctx, TCG_COND_NE, ra, rb, rc, islit, lit, 1); + gen_cmov(TCG_COND_NE, ra, rb, rc, islit, lit, 1); break; case 0x20: /* BIS */ @@ -1026,7 +960,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) if (ra != 31) { if (islit) tcg_gen_ori_i64(cpu_ir[rc], cpu_ir[ra], lit); - else + else tcg_gen_or_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); } else { if (islit) @@ -1038,11 +972,11 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) break; case 0x24: /* CMOVEQ */ - gen_cmov(ctx, TCG_COND_NE, ra, rb, rc, islit, lit, 0); + gen_cmov(TCG_COND_NE, ra, rb, rc, islit, lit, 0); break; case 0x26: /* CMOVNE */ - gen_cmov(ctx, TCG_COND_EQ, ra, rb, rc, islit, lit, 0); + gen_cmov(TCG_COND_EQ, ra, rb, rc, islit, lit, 0); break; case 0x28: /* ORNOT */ @@ -1050,12 +984,8 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) if (ra != 31) { if (islit) tcg_gen_ori_i64(cpu_ir[rc], cpu_ir[ra], ~lit); - else { - TCGv tmp = tcg_temp_new(TCG_TYPE_I64); - tcg_gen_not_i64(tmp, cpu_ir[rb]); - tcg_gen_or_i64(cpu_ir[rc], cpu_ir[ra], tmp); - tcg_temp_free(tmp); - } + else + tcg_gen_orc_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); } else { if (islit) tcg_gen_movi_i64(cpu_ir[rc], ~lit); @@ -1082,11 +1012,11 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) break; case 0x44: /* CMOVLT */ - gen_cmov(ctx, TCG_COND_GE, ra, rb, rc, islit, lit, 0); + gen_cmov(TCG_COND_GE, ra, rb, rc, islit, lit, 0); break; case 0x46: /* CMOVGE */ - gen_cmov(ctx, TCG_COND_LT, ra, rb, rc, islit, lit, 0); + gen_cmov(TCG_COND_LT, ra, rb, rc, islit, lit, 0); break; case 0x48: /* EQV */ @@ -1094,12 +1024,8 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) if (ra != 31) { if (islit) tcg_gen_xori_i64(cpu_ir[rc], cpu_ir[ra], ~lit); - else { - TCGv tmp = tcg_temp_new(TCG_TYPE_I64); - tcg_gen_not_i64(tmp, cpu_ir[rb]); - tcg_gen_xor_i64(cpu_ir[rc], cpu_ir[ra], tmp); - tcg_temp_free(tmp); - } + else + tcg_gen_eqv_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]); } else { if (islit) tcg_gen_movi_i64(cpu_ir[rc], ~lit); @@ -1119,11 +1045,11 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) break; case 0x64: /* CMOVLE */ - gen_cmov(ctx, TCG_COND_GT, ra, rb, rc, islit, lit, 0); + gen_cmov(TCG_COND_GT, ra, rb, rc, islit, lit, 0); break; case 0x66: /* CMOVGT */ - gen_cmov(ctx, TCG_COND_LE, ra, rb, rc, islit, lit, 0); + gen_cmov(TCG_COND_LE, ra, rb, rc, islit, lit, 0); break; case 0x6C: /* IMPLVER */ @@ -1138,7 +1064,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) switch (fn7) { case 0x02: /* MSKBL */ - gen_byte_manipulation(helper_mskbl, ra, rb, rc, islit, lit); + gen_arith3(helper_mskbl, ra, rb, rc, islit, lit); break; case 0x06: /* EXTBL */ @@ -1146,11 +1072,11 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) break; case 0x0B: /* INSBL */ - gen_byte_manipulation(helper_insbl, ra, rb, rc, islit, lit); + gen_arith3(helper_insbl, ra, rb, rc, islit, lit); break; case 0x12: /* MSKWL */ - gen_byte_manipulation(helper_mskwl, ra, rb, rc, islit, lit); + gen_arith3(helper_mskwl, ra, rb, rc, islit, lit); break; case 0x16: /* EXTWL */ @@ -1158,11 +1084,11 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) break; case 0x1B: /* INSWL */ - gen_byte_manipulation(helper_inswl, ra, rb, rc, islit, lit); + gen_arith3(helper_inswl, ra, rb, rc, islit, lit); break; case 0x22: /* MSKLL */ - gen_byte_manipulation(helper_mskll, ra, rb, rc, islit, lit); + gen_arith3(helper_mskll, ra, rb, rc, islit, lit); break; case 0x26: /* EXTLL */ @@ -1170,19 +1096,19 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) break; case 0x2B: /* INSLL */ - gen_byte_manipulation(helper_insll, ra, rb, rc, islit, lit); + gen_arith3(helper_insll, ra, rb, rc, islit, lit); break; case 0x30: /* ZAP */ - gen_byte_manipulation(helper_zap, ra, rb, rc, islit, lit); + gen_arith3(helper_zap, ra, rb, rc, islit, lit); break; case 0x31: /* ZAPNOT */ - gen_byte_manipulation(helper_zapnot, ra, rb, rc, islit, lit); + gen_arith3(helper_zapnot, ra, rb, rc, islit, lit); break; case 0x32: /* MSKQL */ - gen_byte_manipulation(helper_mskql, ra, rb, rc, islit, lit); + gen_arith3(helper_mskql, ra, rb, rc, islit, lit); break; case 0x34: /* SRL */ @@ -1222,7 +1148,7 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) break; case 0x3B: /* INSQL */ - gen_byte_manipulation(helper_insql, ra, rb, rc, islit, lit); + gen_arith3(helper_insql, ra, rb, rc, islit, lit); break; case 0x3C: /* SRA */ @@ -1242,11 +1168,11 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) break; case 0x52: /* MSKWH */ - gen_byte_manipulation(helper_mskwh, ra, rb, rc, islit, lit); + gen_arith3(helper_mskwh, ra, rb, rc, islit, lit); break; case 0x57: /* INSWH */ - gen_byte_manipulation(helper_inswh, ra, rb, rc, islit, lit); + gen_arith3(helper_inswh, ra, rb, rc, islit, lit); break; case 0x5A: /* EXTWH */ @@ -1254,11 +1180,11 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) break; case 0x62: /* MSKLH */ - gen_byte_manipulation(helper_msklh, ra, rb, rc, islit, lit); + gen_arith3(helper_msklh, ra, rb, rc, islit, lit); break; case 0x67: /* INSLH */ - gen_byte_manipulation(helper_inslh, ra, rb, rc, islit, lit); + gen_arith3(helper_inslh, ra, rb, rc, islit, lit); break; case 0x6A: /* EXTLH */ @@ -1266,11 +1192,11 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) break; case 0x72: /* MSKQH */ - gen_byte_manipulation(helper_mskqh, ra, rb, rc, islit, lit); + gen_arith3(helper_mskqh, ra, rb, rc, islit, lit); break; case 0x77: /* INSQH */ - gen_byte_manipulation(helper_insqh, ra, rb, rc, islit, lit); + gen_arith3(helper_insqh, ra, rb, rc, islit, lit); break; case 0x7A: /* EXTQH */ @@ -1309,15 +1235,15 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) break; case 0x30: /* UMULH */ - gen_arith3(ctx, &gen_op_umulh, ra, rb, rc, islit, lit); + gen_arith3(helper_umulh, ra, rb, rc, islit, lit); break; case 0x40: /* MULL/V */ - gen_arith3(ctx, &gen_op_mullv, ra, rb, rc, islit, lit); + gen_arith3(helper_mullv, ra, rb, rc, islit, lit); break; case 0x60: /* MULQ/V */ - gen_arith3(ctx, &gen_op_mulqv, ra, rb, rc, islit, lit); + gen_arith3(helper_mulqv, ra, rb, rc, islit, lit); break; default: goto invalid_opc; @@ -1329,47 +1255,64 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) /* ITOFS */ if (!(ctx->amask & AMASK_FIX)) goto invalid_opc; - gen_itf(ctx, &gen_op_itofs, ra, rc); + if (likely(rc != 31)) { + if (ra != 31) { + TCGv tmp = tcg_temp_new(TCG_TYPE_I32); + tcg_gen_trunc_i64_i32(tmp, cpu_ir[ra]); + tcg_gen_helper_1_1(helper_memory_to_s, cpu_fir[rc], tmp); + tcg_temp_free(tmp); + } else + tcg_gen_movi_i64(cpu_fir[rc], 0); + } break; case 0x0A: /* SQRTF */ if (!(ctx->amask & AMASK_FIX)) goto invalid_opc; - gen_farith2(ctx, &gen_op_sqrtf, rb, rc); + gen_farith2(&helper_sqrtf, rb, rc); break; case 0x0B: /* SQRTS */ if (!(ctx->amask & AMASK_FIX)) goto invalid_opc; - gen_farith2(ctx, &gen_op_sqrts, rb, rc); + gen_farith2(&helper_sqrts, rb, rc); break; case 0x14: /* ITOFF */ if (!(ctx->amask & AMASK_FIX)) goto invalid_opc; -#if 0 // TODO - gen_itf(ctx, &gen_op_itoff, ra, rc); -#else - goto invalid_opc; -#endif + if (likely(rc != 31)) { + if (ra != 31) { + TCGv tmp = tcg_temp_new(TCG_TYPE_I32); + tcg_gen_trunc_i64_i32(tmp, cpu_ir[ra]); + tcg_gen_helper_1_1(helper_memory_to_f, cpu_fir[rc], tmp); + tcg_temp_free(tmp); + } else + tcg_gen_movi_i64(cpu_fir[rc], 0); + } break; case 0x24: /* ITOFT */ if (!(ctx->amask & AMASK_FIX)) goto invalid_opc; - gen_itf(ctx, &gen_op_itoft, ra, rc); + if (likely(rc != 31)) { + if (ra != 31) + tcg_gen_mov_i64(cpu_fir[rc], cpu_ir[ra]); + else + tcg_gen_movi_i64(cpu_fir[rc], 0); + } break; case 0x2A: /* SQRTG */ if (!(ctx->amask & AMASK_FIX)) goto invalid_opc; - gen_farith2(ctx, &gen_op_sqrtg, rb, rc); + gen_farith2(&helper_sqrtg, rb, rc); break; case 0x02B: /* SQRTT */ if (!(ctx->amask & AMASK_FIX)) goto invalid_opc; - gen_farith2(ctx, &gen_op_sqrtt, rb, rc); + gen_farith2(&helper_sqrtt, rb, rc); break; default: goto invalid_opc; @@ -1381,79 +1324,79 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) switch (fpfn) { /* f11 & 0x3F */ case 0x00: /* ADDF */ - gen_farith3(ctx, &gen_op_addf, ra, rb, rc); + gen_farith3(&helper_addf, ra, rb, rc); break; case 0x01: /* SUBF */ - gen_farith3(ctx, &gen_op_subf, ra, rb, rc); + gen_farith3(&helper_subf, ra, rb, rc); break; case 0x02: /* MULF */ - gen_farith3(ctx, &gen_op_mulf, ra, rb, rc); + gen_farith3(&helper_mulf, ra, rb, rc); break; case 0x03: /* DIVF */ - gen_farith3(ctx, &gen_op_divf, ra, rb, rc); + gen_farith3(&helper_divf, ra, rb, rc); break; case 0x1E: /* CVTDG */ #if 0 // TODO - gen_farith2(ctx, &gen_op_cvtdg, rb, rc); + gen_farith2(&helper_cvtdg, rb, rc); #else goto invalid_opc; #endif break; case 0x20: /* ADDG */ - gen_farith3(ctx, &gen_op_addg, ra, rb, rc); + gen_farith3(&helper_addg, ra, rb, rc); break; case 0x21: /* SUBG */ - gen_farith3(ctx, &gen_op_subg, ra, rb, rc); + gen_farith3(&helper_subg, ra, rb, rc); break; case 0x22: /* MULG */ - gen_farith3(ctx, &gen_op_mulg, ra, rb, rc); + gen_farith3(&helper_mulg, ra, rb, rc); break; case 0x23: /* DIVG */ - gen_farith3(ctx, &gen_op_divg, ra, rb, rc); + gen_farith3(&helper_divg, ra, rb, rc); break; case 0x25: /* CMPGEQ */ - gen_farith3(ctx, &gen_op_cmpgeq, ra, rb, rc); + gen_farith3(&helper_cmpgeq, ra, rb, rc); break; case 0x26: /* CMPGLT */ - gen_farith3(ctx, &gen_op_cmpglt, ra, rb, rc); + gen_farith3(&helper_cmpglt, ra, rb, rc); break; case 0x27: /* CMPGLE */ - gen_farith3(ctx, &gen_op_cmpgle, ra, rb, rc); + gen_farith3(&helper_cmpgle, ra, rb, rc); break; case 0x2C: /* CVTGF */ - gen_farith2(ctx, &gen_op_cvtgf, rb, rc); + gen_farith2(&helper_cvtgf, rb, rc); break; case 0x2D: /* CVTGD */ #if 0 // TODO - gen_farith2(ctx, &gen_op_cvtgd, rb, rc); + gen_farith2(ctx, &helper_cvtgd, rb, rc); #else goto invalid_opc; #endif break; case 0x2F: /* CVTGQ */ - gen_farith2(ctx, &gen_op_cvtgq, rb, rc); + gen_farith2(&helper_cvtgq, rb, rc); break; case 0x3C: /* CVTQF */ - gen_farith2(ctx, &gen_op_cvtqf, rb, rc); + gen_farith2(&helper_cvtqf, rb, rc); break; case 0x3E: /* CVTQG */ - gen_farith2(ctx, &gen_op_cvtqg, rb, rc); + gen_farith2(&helper_cvtqg, rb, rc); break; default: goto invalid_opc; @@ -1465,73 +1408,73 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) switch (fpfn) { /* f11 & 0x3F */ case 0x00: /* ADDS */ - gen_farith3(ctx, &gen_op_adds, ra, rb, rc); + gen_farith3(&helper_adds, ra, rb, rc); break; case 0x01: /* SUBS */ - gen_farith3(ctx, &gen_op_subs, ra, rb, rc); + gen_farith3(&helper_subs, ra, rb, rc); break; case 0x02: /* MULS */ - gen_farith3(ctx, &gen_op_muls, ra, rb, rc); + gen_farith3(&helper_muls, ra, rb, rc); break; case 0x03: /* DIVS */ - gen_farith3(ctx, &gen_op_divs, ra, rb, rc); + gen_farith3(&helper_divs, ra, rb, rc); break; case 0x20: /* ADDT */ - gen_farith3(ctx, &gen_op_addt, ra, rb, rc); + gen_farith3(&helper_addt, ra, rb, rc); break; case 0x21: /* SUBT */ - gen_farith3(ctx, &gen_op_subt, ra, rb, rc); + gen_farith3(&helper_subt, ra, rb, rc); break; case 0x22: /* MULT */ - gen_farith3(ctx, &gen_op_mult, ra, rb, rc); + gen_farith3(&helper_mult, ra, rb, rc); break; case 0x23: /* DIVT */ - gen_farith3(ctx, &gen_op_divt, ra, rb, rc); + gen_farith3(&helper_divt, ra, rb, rc); break; case 0x24: /* CMPTUN */ - gen_farith3(ctx, &gen_op_cmptun, ra, rb, rc); + gen_farith3(&helper_cmptun, ra, rb, rc); break; case 0x25: /* CMPTEQ */ - gen_farith3(ctx, &gen_op_cmpteq, ra, rb, rc); + gen_farith3(&helper_cmpteq, ra, rb, rc); break; case 0x26: /* CMPTLT */ - gen_farith3(ctx, &gen_op_cmptlt, ra, rb, rc); + gen_farith3(&helper_cmptlt, ra, rb, rc); break; case 0x27: /* CMPTLE */ - gen_farith3(ctx, &gen_op_cmptle, ra, rb, rc); + gen_farith3(&helper_cmptle, ra, rb, rc); break; case 0x2C: /* XXX: incorrect */ if (fn11 == 0x2AC) { /* CVTST */ - gen_farith2(ctx, &gen_op_cvtst, rb, rc); + gen_farith2(&helper_cvtst, rb, rc); } else { /* CVTTS */ - gen_farith2(ctx, &gen_op_cvtts, rb, rc); + gen_farith2(&helper_cvtts, rb, rc); } break; case 0x2F: /* CVTTQ */ - gen_farith2(ctx, &gen_op_cvttq, rb, rc); + gen_farith2(&helper_cvttq, rb, rc); break; case 0x3C: /* CVTQS */ - gen_farith2(ctx, &gen_op_cvtqs, rb, rc); + gen_farith2(&helper_cvtqs, rb, rc); break; case 0x3E: /* CVTQT */ - gen_farith2(ctx, &gen_op_cvtqt, rb, rc); + gen_farith2(&helper_cvtqt, rb, rc); break; default: goto invalid_opc; @@ -1541,76 +1484,76 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) switch (fn11) { case 0x010: /* CVTLQ */ - gen_farith2(ctx, &gen_op_cvtlq, rb, rc); + gen_farith2(&helper_cvtlq, rb, rc); break; case 0x020: - /* CPYS */ - if (ra == rb) { - if (ra == 31 && rc == 31) { - /* FNOP */ - gen_op_nop(); - } else { + if (likely(rc != 31)) { + if (ra == rb) /* FMOV */ - gen_load_fir(ctx, rb, 0); - gen_store_fir(ctx, rc, 0); - } - } else { - gen_farith3(ctx, &gen_op_cpys, ra, rb, rc); + tcg_gen_mov_i64(cpu_fir[rc], cpu_fir[ra]); + else + /* CPYS */ + gen_farith3(&helper_cpys, ra, rb, rc); } break; case 0x021: /* CPYSN */ - gen_farith2(ctx, &gen_op_cpysn, rb, rc); + gen_farith3(&helper_cpysn, ra, rb, rc); break; case 0x022: /* CPYSE */ - gen_farith2(ctx, &gen_op_cpyse, rb, rc); + gen_farith3(&helper_cpyse, ra, rb, rc); break; case 0x024: /* MT_FPCR */ - gen_load_fir(ctx, ra, 0); - gen_op_store_fpcr(); + if (likely(ra != 31)) + tcg_gen_helper_0_1(helper_store_fpcr, cpu_fir[ra]); + else { + TCGv tmp = tcg_const_i64(0); + tcg_gen_helper_0_1(helper_store_fpcr, tmp); + tcg_temp_free(tmp); + } break; case 0x025: /* MF_FPCR */ - gen_op_load_fpcr(); - gen_store_fir(ctx, ra, 0); + if (likely(ra != 31)) + tcg_gen_helper_1_0(helper_load_fpcr, cpu_fir[ra]); break; case 0x02A: /* FCMOVEQ */ - gen_fcmov(ctx, &gen_op_cmpfeq, ra, rb, rc); + gen_fcmov(&helper_cmpfeq, ra, rb, rc); break; case 0x02B: /* FCMOVNE */ - gen_fcmov(ctx, &gen_op_cmpfne, ra, rb, rc); + gen_fcmov(&helper_cmpfne, ra, rb, rc); break; case 0x02C: /* FCMOVLT */ - gen_fcmov(ctx, &gen_op_cmpflt, ra, rb, rc); + gen_fcmov(&helper_cmpflt, ra, rb, rc); break; case 0x02D: /* FCMOVGE */ - gen_fcmov(ctx, &gen_op_cmpfge, ra, rb, rc); + gen_fcmov(&helper_cmpfge, ra, rb, rc); break; case 0x02E: /* FCMOVLE */ - gen_fcmov(ctx, &gen_op_cmpfle, ra, rb, rc); + gen_fcmov(&helper_cmpfle, ra, rb, rc); break; case 0x02F: /* FCMOVGT */ - gen_fcmov(ctx, &gen_op_cmpfgt, ra, rb, rc); + gen_fcmov(&helper_cmpfgt, ra, rb, rc); break; case 0x030: /* CVTQL */ - gen_farith2(ctx, &gen_op_cvtql, rb, rc); + gen_farith2(&helper_cvtql, rb, rc); break; case 0x130: /* CVTQL/V */ - gen_farith2(ctx, &gen_op_cvtqlv, rb, rc); + gen_farith2(&helper_cvtqlv, rb, rc); break; case 0x530: /* CVTQL/SV */ - gen_farith2(ctx, &gen_op_cvtqlsv, rb, rc); + gen_farith2(&helper_cvtqlsv, rb, rc); break; default: goto invalid_opc; @@ -1683,18 +1626,20 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) #else if (!ctx->pal_mode) goto invalid_opc; - gen_op_mfpr(insn & 0xFF); - if (ra != 31) - tcg_gen_mov_i64(cpu_ir[ra], cpu_T[0]); + if (ra != 31) { + TCGv tmp = tcg_const_i32(insn & 0xFF); + tcg_gen_helper_1_2(helper_mfpr, cpu_ir[ra], tmp, cpu_ir[ra]); + tcg_temp_free(tmp); + } break; #endif case 0x1A: - if (ra != 31) - tcg_gen_movi_i64(cpu_ir[ra], ctx->pc); if (rb != 31) tcg_gen_andi_i64(cpu_pc, cpu_ir[rb], ~3); else tcg_gen_movi_i64(cpu_pc, 0); + if (ra != 31) + tcg_gen_movi_i64(cpu_ir[ra], ctx->pc); /* Those four jumps only differ by the branch prediction hint */ switch (fn2) { case 0x0: @@ -1719,94 +1664,94 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) #else if (!ctx->pal_mode) goto invalid_opc; - if (rb != 31) - tcg_gen_mov_i64(cpu_T[0], cpu_ir[rb]); - else - tcg_gen_movi_i64(cpu_T[0], 0); - tcg_gen_movi_i64(cpu_T[1], disp12); - tcg_gen_add_i64(cpu_T[0], cpu_T[0], cpu_T[1]); - switch ((insn >> 12) & 0xF) { - case 0x0: - /* Longword physical access */ - gen_op_ldl_raw(); - break; - case 0x1: - /* Quadword physical access */ - gen_op_ldq_raw(); - break; - case 0x2: - /* Longword physical access with lock */ - gen_op_ldl_l_raw(); - break; - case 0x3: - /* Quadword physical access with lock */ - gen_op_ldq_l_raw(); - break; - case 0x4: - /* Longword virtual PTE fetch */ - gen_op_ldl_kernel(); - break; - case 0x5: - /* Quadword virtual PTE fetch */ - gen_op_ldq_kernel(); - break; - case 0x6: - /* Invalid */ - goto invalid_opc; - case 0x7: - /* Invalid */ - goto invalid_opc; - case 0x8: - /* Longword virtual access */ - gen_op_ld_phys_to_virt(); - gen_op_ldl_raw(); - break; - case 0x9: - /* Quadword virtual access */ - gen_op_ld_phys_to_virt(); - gen_op_ldq_raw(); - break; - case 0xA: - /* Longword virtual access with protection check */ - gen_ldl(ctx); - break; - case 0xB: - /* Quadword virtual access with protection check */ - gen_ldq(ctx); - break; - case 0xC: - /* Longword virtual access with altenate access mode */ - gen_op_set_alt_mode(); - gen_op_ld_phys_to_virt(); - gen_op_ldl_raw(); - gen_op_restore_mode(); - break; - case 0xD: - /* Quadword virtual access with altenate access mode */ - gen_op_set_alt_mode(); - gen_op_ld_phys_to_virt(); - gen_op_ldq_raw(); - gen_op_restore_mode(); - break; - case 0xE: - /* Longword virtual access with alternate access mode and - * protection checks - */ - gen_op_set_alt_mode(); - gen_op_ldl_data(); - gen_op_restore_mode(); - break; - case 0xF: - /* Quadword virtual access with alternate access mode and - * protection checks - */ - gen_op_set_alt_mode(); - gen_op_ldq_data(); - gen_op_restore_mode(); - break; + if (ra != 31) { + TCGv addr = tcg_temp_new(TCG_TYPE_I64); + if (rb != 31) + tcg_gen_addi_i64(addr, cpu_ir[rb], disp12); + else + tcg_gen_movi_i64(addr, disp12); + switch ((insn >> 12) & 0xF) { + case 0x0: + /* Longword physical access */ + tcg_gen_helper_0_2(helper_ldl_raw, cpu_ir[ra], addr); + break; + case 0x1: + /* Quadword physical access */ + tcg_gen_helper_0_2(helper_ldq_raw, cpu_ir[ra], addr); + break; + case 0x2: + /* Longword physical access with lock */ + tcg_gen_helper_0_2(helper_ldl_l_raw, cpu_ir[ra], addr); + break; + case 0x3: + /* Quadword physical access with lock */ + tcg_gen_helper_0_2(helper_ldq_l_raw, cpu_ir[ra], addr); + break; + case 0x4: + /* Longword virtual PTE fetch */ + tcg_gen_helper_0_2(helper_ldl_kernel, cpu_ir[ra], addr); + break; + case 0x5: + /* Quadword virtual PTE fetch */ + tcg_gen_helper_0_2(helper_ldq_kernel, cpu_ir[ra], addr); + break; + case 0x6: + /* Incpu_ir[ra]id */ + goto incpu_ir[ra]id_opc; + case 0x7: + /* Incpu_ir[ra]id */ + goto incpu_ir[ra]id_opc; + case 0x8: + /* Longword virtual access */ + tcg_gen_helper_1_1(helper_st_virt_to_phys, addr, addr); + tcg_gen_helper_0_2(helper_ldl_raw, cpu_ir[ra], addr); + break; + case 0x9: + /* Quadword virtual access */ + tcg_gen_helper_1_1(helper_st_virt_to_phys, addr, addr); + tcg_gen_helper_0_2(helper_ldq_raw, cpu_ir[ra], addr); + break; + case 0xA: + /* Longword virtual access with protection check */ + tcg_gen_qemu_ld32s(cpu_ir[ra], addr, ctx->flags); + break; + case 0xB: + /* Quadword virtual access with protection check */ + tcg_gen_qemu_ld64(cpu_ir[ra], addr, ctx->flags); + break; + case 0xC: + /* Longword virtual access with altenate access mode */ + tcg_gen_helper_0_0(helper_set_alt_mode); + tcg_gen_helper_1_1(helper_st_virt_to_phys, addr, addr); + tcg_gen_helper_0_2(helper_ldl_raw, cpu_ir[ra], addr); + tcg_gen_helper_0_0(helper_restore_mode); + break; + case 0xD: + /* Quadword virtual access with altenate access mode */ + tcg_gen_helper_0_0(helper_set_alt_mode); + tcg_gen_helper_1_1(helper_st_virt_to_phys, addr, addr); + tcg_gen_helper_0_2(helper_ldq_raw, cpu_ir[ra], addr); + tcg_gen_helper_0_0(helper_restore_mode); + break; + case 0xE: + /* Longword virtual access with alternate access mode and + * protection checks + */ + tcg_gen_helper_0_0(helper_set_alt_mode); + tcg_gen_helper_0_2(helper_ldl_data, cpu_ir[ra], addr); + tcg_gen_helper_0_0(helper_restore_mode); + break; + case 0xF: + /* Quadword virtual access with alternate access mode and + * protection checks + */ + tcg_gen_helper_0_0(helper_set_alt_mode); + tcg_gen_helper_0_2(helper_ldq_data, cpu_ir[ra], addr); + tcg_gen_helper_0_0(helper_restore_mode); + break; + } + tcg_temp_free(addr); } - if (ra != 31) - tcg_gen_mov_i64(cpu_ir[ra], cpu_T[1]); break; #endif case 0x1C: @@ -1961,13 +1906,29 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) /* FTOIT */ if (!(ctx->amask & AMASK_FIX)) goto invalid_opc; - gen_fti(ctx, &gen_op_ftoit, ra, rb); + if (likely(rc != 31)) { + if (ra != 31) + tcg_gen_mov_i64(cpu_ir[rc], cpu_fir[ra]); + else + tcg_gen_movi_i64(cpu_ir[rc], 0); + } break; case 0x78: /* FTOIS */ if (!(ctx->amask & AMASK_FIX)) goto invalid_opc; - gen_fti(ctx, &gen_op_ftois, ra, rb); + if (rc != 31) { + TCGv tmp1 = tcg_temp_new(TCG_TYPE_I32); + if (ra != 31) + tcg_gen_helper_1_1(helper_s_to_memory, tmp1, cpu_fir[ra]); + else { + TCGv tmp2 = tcg_const_i64(0); + tcg_gen_helper_1_1(helper_s_to_memory, tmp1, tmp2); + tcg_temp_free(tmp2); + } + tcg_gen_ext_i32_i64(cpu_ir[rc], tmp1); + tcg_temp_free(tmp1); + } break; default: goto invalid_opc; @@ -1980,12 +1941,18 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) #else if (!ctx->pal_mode) goto invalid_opc; - if (ra != 31) - tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]); - else - tcg_gen_movi_i64(cpu_T[0], 0); - gen_op_mtpr(insn & 0xFF); - ret = 2; + else { + TCGv tmp1 = tcg_const_i32(insn & 0xFF); + if (ra != 31) + tcg_gen_helper(helper_mtpr, tmp1, cpu_ir[ra]); + else { + TCGv tmp2 = tcg_const_i64(0); + tcg_gen_helper(helper_mtpr, tmp1, tmp2); + tcg_temp_free(tmp2); + } + tcg_temp_free(tmp1); + ret = 2; + } break; #endif case 0x1E: @@ -1997,15 +1964,17 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) goto invalid_opc; if (rb == 31) { /* "Old" alpha */ - gen_op_hw_rei(); + tcg_gen_helper_0_0(helper_hw_rei); } else { - if (ra != 31) - tcg_gen_mov_i64(cpu_T[0], cpu_ir[rb]); - else - tcg_gen_movi_i64(cpu_T[0], 0); - tcg_gen_movi_i64(cpu_T[1], (((int64_t)insn << 51) >> 51)); - tcg_gen_add_i64(cpu_T[0], cpu_T[0], cpu_T[1]); - gen_op_hw_ret(); + TCGv tmp; + + if (ra != 31) { + tmp = tcg_temp_new(TCG_TYPE_I64); + tcg_gen_addi_i64(tmp, cpu_ir[rb], (((int64_t)insn << 51) >> 51)); + } else + tmp = tcg_const_i64(((int64_t)insn << 51) >> 51); + tcg_gen_helper_0_1(helper_hw_ret, tmp); + tcg_temp_free(tmp); } ret = 2; break; @@ -2017,162 +1986,155 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) #else if (!ctx->pal_mode) goto invalid_opc; - if (ra != 31) - tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp12); - else - tcg_gen_movi_i64(cpu_T[0], disp12); - if (ra != 31) - tcg_gen_mov_i64(cpu_T[1], cpu_ir[ra]); - else - tcg_gen_movi_i64(cpu_T[1], 0); - switch ((insn >> 12) & 0xF) { - case 0x0: - /* Longword physical access */ - gen_op_stl_raw(); - break; - case 0x1: - /* Quadword physical access */ - gen_op_stq_raw(); - break; - case 0x2: - /* Longword physical access with lock */ - gen_op_stl_c_raw(); - break; - case 0x3: - /* Quadword physical access with lock */ - gen_op_stq_c_raw(); - break; - case 0x4: - /* Longword virtual access */ - gen_op_st_phys_to_virt(); - gen_op_stl_raw(); - break; - case 0x5: - /* Quadword virtual access */ - gen_op_st_phys_to_virt(); - gen_op_stq_raw(); - break; - case 0x6: - /* Invalid */ - goto invalid_opc; - case 0x7: - /* Invalid */ - goto invalid_opc; - case 0x8: - /* Invalid */ - goto invalid_opc; - case 0x9: - /* Invalid */ - goto invalid_opc; - case 0xA: - /* Invalid */ - goto invalid_opc; - case 0xB: - /* Invalid */ - goto invalid_opc; - case 0xC: - /* Longword virtual access with alternate access mode */ - gen_op_set_alt_mode(); - gen_op_st_phys_to_virt(); - gen_op_ldl_raw(); - gen_op_restore_mode(); - break; - case 0xD: - /* Quadword virtual access with alternate access mode */ - gen_op_set_alt_mode(); - gen_op_st_phys_to_virt(); - gen_op_ldq_raw(); - gen_op_restore_mode(); - break; - case 0xE: - /* Invalid */ - goto invalid_opc; - case 0xF: - /* Invalid */ - goto invalid_opc; + else { + TCGv addr, val; + addr = tcg_temp_new(TCG_TYPE_I64); + if (rb != 31) + tcg_gen_addi_i64(addr, cpu_ir[rb], disp12); + else + tcg_gen_movi_i64(addr, disp12); + if (ra != 31) + val = cpu_ir[ra]; + else { + val = tcg_temp_new(TCG_TYPE_I64); + tcg_gen_movi_i64(val, 0); + } + switch ((insn >> 12) & 0xF) { + case 0x0: + /* Longword physical access */ + tcg_gen_helper_0_2(helper_stl_raw, val, addr); + break; + case 0x1: + /* Quadword physical access */ + tcg_gen_helper_0_2(helper_stq_raw, val, addr); + break; + case 0x2: + /* Longword physical access with lock */ + tcg_gen_helper_1_2(helper_stl_c_raw, val, val, addr); + break; + case 0x3: + /* Quadword physical access with lock */ + tcg_gen_helper_1_2(helper_stq_c_raw, val, val, addr); + break; + case 0x4: + /* Longword virtual access */ + tcg_gen_helper_1_1(helper_st_virt_to_phys, addr, addr); + tcg_gen_helper_0_2(helper_stl_raw, val, addr); + break; + case 0x5: + /* Quadword virtual access */ + tcg_gen_helper_1_1(helper_st_virt_to_phys, addr, addr); + tcg_gen_helper_0_2(helper_stq_raw, val, addr); + break; + case 0x6: + /* Invalid */ + goto invalid_opc; + case 0x7: + /* Invalid */ + goto invalid_opc; + case 0x8: + /* Invalid */ + goto invalid_opc; + case 0x9: + /* Invalid */ + goto invalid_opc; + case 0xA: + /* Invalid */ + goto invalid_opc; + case 0xB: + /* Invalid */ + goto invalid_opc; + case 0xC: + /* Longword virtual access with alternate access mode */ + tcg_gen_helper_0_0(helper_set_alt_mode); + tcg_gen_helper_1_1(helper_st_virt_to_phys, addr, addr); + tcg_gen_helper_0_2(helper_stl_raw, val, addr); + tcg_gen_helper_0_0(helper_restore_mode); + break; + case 0xD: + /* Quadword virtual access with alternate access mode */ + tcg_gen_helper_0_0(helper_set_alt_mode); + tcg_gen_helper_1_1(helper_st_virt_to_phys, addr, addr); + tcg_gen_helper_0_2(helper_stl_raw, val, addr); + tcg_gen_helper_0_0(helper_restore_mode); + break; + case 0xE: + /* Invalid */ + goto invalid_opc; + case 0xF: + /* Invalid */ + goto invalid_opc; + } + if (ra != 31) + tcg_temp_free(val); + tcg_temp_free(addr); } ret = 2; break; #endif case 0x20: /* LDF */ -#if 0 // TODO - gen_load_fmem(ctx, &gen_ldf, ra, rb, disp16); -#else - goto invalid_opc; -#endif + gen_load_mem(ctx, &gen_qemu_ldf, ra, rb, disp16, 1, 0); break; case 0x21: /* LDG */ -#if 0 // TODO - gen_load_fmem(ctx, &gen_ldg, ra, rb, disp16); -#else - goto invalid_opc; -#endif + gen_load_mem(ctx, &gen_qemu_ldg, ra, rb, disp16, 1, 0); break; case 0x22: /* LDS */ - gen_load_fmem(ctx, &gen_lds, ra, rb, disp16); + gen_load_mem(ctx, &gen_qemu_lds, ra, rb, disp16, 1, 0); break; case 0x23: /* LDT */ - gen_load_fmem(ctx, &gen_ldt, ra, rb, disp16); + gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 1, 0); break; case 0x24: /* STF */ -#if 0 // TODO - gen_store_fmem(ctx, &gen_stf, ra, rb, disp16); -#else - goto invalid_opc; -#endif + gen_store_mem(ctx, &gen_qemu_stf, ra, rb, disp16, 1, 0); break; case 0x25: /* STG */ -#if 0 // TODO - gen_store_fmem(ctx, &gen_stg, ra, rb, disp16); -#else - goto invalid_opc; -#endif + gen_store_mem(ctx, &gen_qemu_stg, ra, rb, disp16, 1, 0); break; case 0x26: /* STS */ - gen_store_fmem(ctx, &gen_sts, ra, rb, disp16); + gen_store_mem(ctx, &gen_qemu_sts, ra, rb, disp16, 1, 0); break; case 0x27: /* STT */ - gen_store_fmem(ctx, &gen_stt, ra, rb, disp16); + gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 1, 0); break; case 0x28: /* LDL */ - gen_load_mem(ctx, &gen_ldl, ra, rb, disp16, 0); + gen_load_mem(ctx, &tcg_gen_qemu_ld32s, ra, rb, disp16, 0, 0); break; case 0x29: /* LDQ */ - gen_load_mem(ctx, &gen_ldq, ra, rb, disp16, 0); + gen_load_mem(ctx, &tcg_gen_qemu_ld64, ra, rb, disp16, 0, 0); break; case 0x2A: /* LDL_L */ - gen_load_mem(ctx, &gen_ldl_l, ra, rb, disp16, 0); + gen_load_mem(ctx, &gen_qemu_ldl_l, ra, rb, disp16, 0, 0); break; case 0x2B: /* LDQ_L */ - gen_load_mem(ctx, &gen_ldq_l, ra, rb, disp16, 0); + gen_load_mem(ctx, &gen_qemu_ldq_l, ra, rb, disp16, 0, 0); break; case 0x2C: /* STL */ - gen_store_mem(ctx, &gen_stl, ra, rb, disp16, 0); + gen_store_mem(ctx, &tcg_gen_qemu_st32, ra, rb, disp16, 0, 0); break; case 0x2D: /* STQ */ - gen_store_mem(ctx, &gen_stq, ra, rb, disp16, 0); + gen_store_mem(ctx, &tcg_gen_qemu_st64, ra, rb, disp16, 0, 0); break; case 0x2E: /* STL_C */ - gen_store_mem(ctx, &gen_stl_c, ra, rb, disp16, 0); + gen_store_mem(ctx, &gen_qemu_stl_c, ra, rb, disp16, 0, 0); break; case 0x2F: /* STQ_C */ - gen_store_mem(ctx, &gen_stq_c, ra, rb, disp16, 0); + gen_store_mem(ctx, &gen_qemu_stq_c, ra, rb, disp16, 0, 0); break; case 0x30: /* BR */ @@ -2183,17 +2145,17 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) break; case 0x31: /* FBEQ */ - gen_fbcond(ctx, &gen_op_cmpfeq, ra, disp16); + gen_fbcond(ctx, &helper_cmpfeq, ra, disp16); ret = 1; break; case 0x32: /* FBLT */ - gen_fbcond(ctx, &gen_op_cmpflt, ra, disp16); + gen_fbcond(ctx, &helper_cmpflt, ra, disp16); ret = 1; break; case 0x33: /* FBLE */ - gen_fbcond(ctx, &gen_op_cmpfle, ra, disp16); + gen_fbcond(ctx, &helper_cmpfle, ra, disp16); ret = 1; break; case 0x34: @@ -2205,17 +2167,17 @@ static always_inline int translate_one (DisasContext *ctx, uint32_t insn) break; case 0x35: /* FBNE */ - gen_fbcond(ctx, &gen_op_cmpfne, ra, disp16); + gen_fbcond(ctx, &helper_cmpfne, ra, disp16); ret = 1; break; case 0x36: /* FBGE */ - gen_fbcond(ctx, &gen_op_cmpfge, ra, disp16); + gen_fbcond(ctx, &helper_cmpfge, ra, disp16); ret = 1; break; case 0x37: /* FBGT */ - gen_fbcond(ctx, &gen_op_cmpfgt, ra, disp16); + gen_fbcond(ctx, &helper_cmpfgt, ra, disp16); ret = 1; break; case 0x38: @@ -2379,7 +2341,7 @@ static always_inline void gen_intermediate_code_internal (CPUState *env, } if (loglevel & CPU_LOG_TB_IN_ASM) { fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start)); - target_disas(logfile, pc_start, ctx.pc - pc_start, 1); + target_disas(logfile, pc_start, ctx.pc - pc_start, 1); fprintf(logfile, "\n"); } #endif