X-Git-Url: http://vcs.maemo.org/git/?a=blobdiff_plain;f=exec-all.h;h=bc91f71ca180fb8db38882d02608a5cf78b373fb;hb=f5d2a381d1fb5f7def1c86c95d0c093e54e3aa67;hp=9994acb7a721025e814184c976fb4e9cc94e0a45;hpb=6e59c1db892ce768178e705a5b68ab349eb5282f;p=qemu diff --git a/exec-all.h b/exec-all.h index 9994acb..bc91f71 100644 --- a/exec-all.h +++ b/exec-all.h @@ -28,7 +28,7 @@ #define tostring(s) #s #endif -#if GCC_MAJOR < 3 +#if __GNUC__ < 3 #define __builtin_expect(x, n) (x) #endif @@ -55,10 +55,20 @@ struct TranslationBlock; extern uint16_t gen_opc_buf[OPC_BUF_SIZE]; extern uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE]; -extern uint32_t gen_opc_pc[OPC_BUF_SIZE]; +extern long gen_labels[OPC_BUF_SIZE]; +extern int nb_gen_labels; +extern target_ulong gen_opc_pc[OPC_BUF_SIZE]; +extern target_ulong gen_opc_npc[OPC_BUF_SIZE]; extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE]; extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE]; - +extern target_ulong gen_opc_jump_pc[2]; +extern uint32_t gen_opc_hflags[OPC_BUF_SIZE]; + +typedef void (GenOpFunc)(void); +typedef void (GenOpFunc1)(long); +typedef void (GenOpFunc2)(long, long); +typedef void (GenOpFunc3)(long, long, long); + #if defined(TARGET_I386) void optimize_flags_init(void); @@ -74,37 +84,102 @@ void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf); int cpu_gen_code(CPUState *env, struct TranslationBlock *tb, int max_code_size, int *gen_code_size_ptr); int cpu_restore_state(struct TranslationBlock *tb, - CPUState *env, unsigned long searched_pc); -void cpu_exec_init(void); -int page_unprotect(unsigned long address); -void page_unmap(void); -void tlb_flush_page(CPUState *env, uint32_t addr); -void tlb_flush_page_write(CPUState *env, uint32_t addr); -void tlb_flush(CPUState *env); + CPUState *env, unsigned long searched_pc, + void *puc); +int cpu_gen_code_copy(CPUState *env, struct TranslationBlock *tb, + int max_code_size, int *gen_code_size_ptr); +int cpu_restore_state_copy(struct TranslationBlock *tb, + CPUState *env, unsigned long searched_pc, + void *puc); +void cpu_resume_from_signal(CPUState *env1, void *puc); +void cpu_exec_init(CPUState *env); +int page_unprotect(target_ulong address, unsigned long pc, void *puc); +void tb_invalidate_phys_page_range(target_ulong start, target_ulong end, + int is_cpu_write_access); +void tb_invalidate_page_range(target_ulong start, target_ulong end); +void tlb_flush_page(CPUState *env, target_ulong addr); +void tlb_flush(CPUState *env, int flush_global); +int tlb_set_page_exec(CPUState *env, target_ulong vaddr, + target_phys_addr_t paddr, int prot, + int is_user, int is_softmmu); +static inline int tlb_set_page(CPUState *env, target_ulong vaddr, + target_phys_addr_t paddr, int prot, + int is_user, int is_softmmu) +{ + if (prot & PAGE_READ) + prot |= PAGE_EXEC; + return tlb_set_page_exec(env, vaddr, paddr, prot, is_user, is_softmmu); +} #define CODE_GEN_MAX_SIZE 65536 #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ -#define CODE_GEN_HASH_BITS 15 -#define CODE_GEN_HASH_SIZE (1 << CODE_GEN_HASH_BITS) +#define CODE_GEN_PHYS_HASH_BITS 15 +#define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS) /* maximum total translate dcode allocated */ -#define CODE_GEN_BUFFER_SIZE (2048 * 1024) + +/* NOTE: the translated code area cannot be too big because on some + archs the range of "fast" function calls is limited. Here is a + summary of the ranges: + + i386 : signed 32 bits + arm : signed 26 bits + ppc : signed 24 bits + sparc : signed 32 bits + alpha : signed 23 bits +*/ + +#if defined(__alpha__) +#define CODE_GEN_BUFFER_SIZE (2 * 1024 * 1024) +#elif defined(__ia64) +#define CODE_GEN_BUFFER_SIZE (4 * 1024 * 1024) /* range of addl */ +#elif defined(__powerpc__) +#define CODE_GEN_BUFFER_SIZE (6 * 1024 * 1024) +#else +#define CODE_GEN_BUFFER_SIZE (16 * 1024 * 1024) +#endif + //#define CODE_GEN_BUFFER_SIZE (128 * 1024) -#if defined(__powerpc__) +/* estimated block size for TB allocation */ +/* XXX: use a per code average code fragment size and modulate it + according to the host CPU */ +#if defined(CONFIG_SOFTMMU) +#define CODE_GEN_AVG_BLOCK_SIZE 128 +#else +#define CODE_GEN_AVG_BLOCK_SIZE 64 +#endif + +#define CODE_GEN_MAX_BLOCKS (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE) + +#if defined(__powerpc__) +#define USE_DIRECT_JUMP +#endif +#if defined(__i386__) && !defined(_WIN32) #define USE_DIRECT_JUMP #endif typedef struct TranslationBlock { - unsigned long pc; /* simulated PC corresponding to this block (EIP + CS base) */ - unsigned long cs_base; /* CS base for this block */ + target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */ + target_ulong cs_base; /* CS base for this block */ unsigned int flags; /* flags defining in which context the code was generated */ uint16_t size; /* size of target code for this block (1 <= size <= TARGET_PAGE_SIZE) */ + uint16_t cflags; /* compile flags */ +#define CF_CODE_COPY 0x0001 /* block was generated in code copy mode */ +#define CF_TB_FP_USED 0x0002 /* fp ops are used in the TB */ +#define CF_FP_USED 0x0004 /* fp ops are used in the TB or in a chained TB */ +#define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */ + uint8_t *tc_ptr; /* pointer to the translated code */ - struct TranslationBlock *hash_next; /* next matching block */ - struct TranslationBlock *page_next[2]; /* next blocks in even/odd page */ + /* next matching tb for physical address. */ + struct TranslationBlock *phys_hash_next; + /* first and second physical page containing code. The lower bit + of the pointer tells the index in page_next[] */ + struct TranslationBlock *page_next[2]; + target_ulong page_addr[2]; + /* the following data are used to directly call another TB from the code of this one. */ uint16_t tb_next_offset[2]; /* offset of original jump target */ @@ -121,46 +196,29 @@ typedef struct TranslationBlock { struct TranslationBlock *jmp_first; } TranslationBlock; -static inline unsigned int tb_hash_func(unsigned long pc) +static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc) { - return pc & (CODE_GEN_HASH_SIZE - 1); + return (pc ^ (pc >> TB_JMP_CACHE_BITS)) & (TB_JMP_CACHE_SIZE - 1); } -TranslationBlock *tb_alloc(unsigned long pc); -void tb_flush(void); -void tb_link(TranslationBlock *tb); +static inline unsigned int tb_phys_hash_func(unsigned long pc) +{ + return pc & (CODE_GEN_PHYS_HASH_SIZE - 1); +} -extern TranslationBlock *tb_hash[CODE_GEN_HASH_SIZE]; +TranslationBlock *tb_alloc(target_ulong pc); +void tb_flush(CPUState *env); +void tb_link_phys(TranslationBlock *tb, + target_ulong phys_pc, target_ulong phys_page2); + +extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE]; extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE]; extern uint8_t *code_gen_ptr; -/* find a translation block in the translation cache. If not found, - return NULL and the pointer to the last element of the list in pptb */ -static inline TranslationBlock *tb_find(TranslationBlock ***pptb, - unsigned long pc, - unsigned long cs_base, - unsigned int flags) -{ - TranslationBlock **ptb, *tb; - unsigned int h; - - h = tb_hash_func(pc); - ptb = &tb_hash[h]; - for(;;) { - tb = *ptb; - if (!tb) - break; - if (tb->pc == pc && tb->cs_base == cs_base && tb->flags == flags) - return tb; - ptb = &tb->hash_next; - } - *pptb = ptb; - return NULL; -} +#if defined(USE_DIRECT_JUMP) #if defined(__powerpc__) - static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) { uint32_t val, *ptr; @@ -177,6 +235,14 @@ static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr asm volatile ("sync" : : : "memory"); asm volatile ("isync" : : : "memory"); } +#elif defined(__i386__) +static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr) +{ + /* patch the branch destination */ + *(uint32_t *)jmp_addr = addr - (jmp_addr + 4); + /* no need to flush icache explicitely */ +} +#endif static inline void tb_set_jmp_target(TranslationBlock *tb, int n, unsigned long addr) @@ -221,72 +287,76 @@ TranslationBlock *tb_find_pc(unsigned long pc_ptr); #define offsetof(type, field) ((size_t) &((type *)0)->field) #endif +#if defined(_WIN32) +#define ASM_DATA_SECTION ".section \".data\"\n" +#define ASM_PREVIOUS_SECTION ".section .text\n" +#elif defined(__APPLE__) +#define ASM_DATA_SECTION ".data\n" +#define ASM_PREVIOUS_SECTION ".text\n" +#else +#define ASM_DATA_SECTION ".section \".data\"\n" +#define ASM_PREVIOUS_SECTION ".previous\n" +#endif + +#define ASM_OP_LABEL_NAME(n, opname) \ + ASM_NAME(__op_label) #n "." ASM_NAME(opname) + #if defined(__powerpc__) -/* on PowerPC we patch the jump instruction directly */ -#define JUMP_TB(opname, tbparam, n, eip)\ +/* we patch the jump instruction directly */ +#define GOTO_TB(opname, tbparam, n)\ do {\ - asm volatile (".section \".data\"\n"\ - "__op_label" #n "." stringify(opname) ":\n"\ + asm volatile (ASM_DATA_SECTION\ + ASM_OP_LABEL_NAME(n, opname) ":\n"\ ".long 1f\n"\ - ".previous\n"\ - "b __op_jmp" #n "\n"\ + ASM_PREVIOUS_SECTION \ + "b " ASM_NAME(__op_jmp) #n "\n"\ "1:\n");\ - T0 = (long)(tbparam) + (n);\ - EIP = eip;\ - EXIT_TB();\ } while (0) -#define JUMP_TB2(opname, tbparam, n)\ +#elif defined(__i386__) && defined(USE_DIRECT_JUMP) + +/* we patch the jump instruction directly */ +#define GOTO_TB(opname, tbparam, n)\ do {\ - asm volatile ("b __op_jmp%0\n" : : "i" (n + 2));\ + asm volatile (".section .data\n"\ + ASM_OP_LABEL_NAME(n, opname) ":\n"\ + ".long 1f\n"\ + ASM_PREVIOUS_SECTION \ + "jmp " ASM_NAME(__op_jmp) #n "\n"\ + "1:\n");\ } while (0) #else /* jump to next block operations (more portable code, does not need cache flushing, but slower because of indirect jump) */ -#define JUMP_TB(opname, tbparam, n, eip)\ +#define GOTO_TB(opname, tbparam, n)\ do {\ - static void __attribute__((unused)) *__op_label ## n = &&label ## n;\ static void __attribute__((unused)) *dummy ## n = &&dummy_label ## n;\ + static void __attribute__((unused)) *__op_label ## n \ + __asm__(ASM_OP_LABEL_NAME(n, opname)) = &&label ## n;\ goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n]);\ -label ## n:\ - T0 = (long)(tbparam) + (n);\ - EIP = eip;\ -dummy_label ## n:\ - EXIT_TB();\ -} while (0) - -/* second jump to same destination 'n' */ -#define JUMP_TB2(opname, tbparam, n)\ -do {\ - goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n]);\ +label ## n: ;\ +dummy_label ## n: ;\ } while (0) #endif -/* physical memory access */ -#define IO_MEM_NB_ENTRIES 256 -#define TLB_INVALID_MASK (1 << 3) -#define IO_MEM_SHIFT 4 -#define IO_MEM_UNASSIGNED (1 << IO_MEM_SHIFT) - -unsigned long physpage_find(unsigned long page); - extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4]; extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4]; +extern void *io_mem_opaque[IO_MEM_NB_ENTRIES]; #ifdef __powerpc__ static inline int testandset (int *p) { int ret; __asm__ __volatile__ ( - "0: lwarx %0,0,%1 ;" - " xor. %0,%3,%0;" - " bne 1f;" - " stwcx. %2,0,%1;" - " bne- 0b;" + "0: lwarx %0,0,%1\n" + " xor. %0,%3,%0\n" + " bne 1f\n" + " stwcx. %2,0,%1\n" + " bne- 0b\n" "1: " : "=&r" (ret) : "r" (p), "r" (1), "r" (0) @@ -298,14 +368,26 @@ static inline int testandset (int *p) #ifdef __i386__ static inline int testandset (int *p) { - char ret; - long int readval; + long int readval = 0; - __asm__ __volatile__ ("lock; cmpxchgl %3, %1; sete %0" - : "=q" (ret), "=m" (*p), "=a" (readval) - : "r" (1), "m" (*p), "a" (0) - : "memory"); - return ret; + __asm__ __volatile__ ("lock; cmpxchgl %2, %0" + : "+m" (*p), "+a" (readval) + : "r" (1) + : "cc"); + return readval; +} +#endif + +#ifdef __x86_64__ +static inline int testandset (int *p) +{ + long int readval = 0; + + __asm__ __volatile__ ("lock; cmpxchgl %2, %0" + : "+m" (*p), "+a" (readval) + : "r" (1) + : "cc"); + return readval; } #endif @@ -376,7 +458,16 @@ static inline int testandset (int *p) : "=r" (ret) : "m" (p) : "cc","memory"); - return ret == 0; + return ret; +} +#endif + +#ifdef __ia64 +#include + +static inline int testandset (int *p) +{ + return __sync_lock_test_and_set (p, 1); } #endif @@ -384,7 +475,7 @@ typedef int spinlock_t; #define SPIN_LOCK_UNLOCKED 0 -#if 1 +#if defined(CONFIG_USER_ONLY) static inline void spin_lock(spinlock_t *lock) { while (testandset(lock)); @@ -416,10 +507,11 @@ static inline int spin_trylock(spinlock_t *lock) extern spinlock_t tb_lock; +extern int tb_invalidated_flag; -#if defined(TARGET_I386) && !defined(CONFIG_USER_ONLY) +#if !defined(CONFIG_USER_ONLY) -void tlb_fill(unsigned long addr, int is_write, int is_user, +void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr); #define ACCESS_TYPE 3 @@ -435,8 +527,79 @@ void tlb_fill(unsigned long addr, int is_write, int is_user, #define DATA_SIZE 4 #include "softmmu_header.h" +#define DATA_SIZE 8 +#include "softmmu_header.h" + #undef ACCESS_TYPE #undef MEMSUFFIX #undef env #endif + +#if defined(CONFIG_USER_ONLY) +static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr) +{ + return addr; +} +#else +/* NOTE: this function can trigger an exception */ +/* NOTE2: the returned address is not exactly the physical address: it + is the offset relative to phys_ram_base */ +static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr) +{ + int is_user, index, pd; + + index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); +#if defined(TARGET_I386) + is_user = ((env->hflags & HF_CPL_MASK) == 3); +#elif defined (TARGET_PPC) + is_user = msr_pr; +#elif defined (TARGET_MIPS) + is_user = ((env->hflags & MIPS_HFLAG_MODE) == MIPS_HFLAG_UM); +#elif defined (TARGET_SPARC) + is_user = (env->psrs == 0); +#elif defined (TARGET_ARM) + is_user = ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR); +#elif defined (TARGET_SH4) + is_user = ((env->sr & SR_MD) == 0); +#else +#error unimplemented CPU +#endif + if (__builtin_expect(env->tlb_table[is_user][index].addr_code != + (addr & TARGET_PAGE_MASK), 0)) { + ldub_code(addr); + } + pd = env->tlb_table[is_user][index].addr_code & ~TARGET_PAGE_MASK; + if (pd > IO_MEM_ROM) { + cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x%08lx\n", addr); + } + return addr + env->tlb_table[is_user][index].addend - (unsigned long)phys_ram_base; +} +#endif + + +#ifdef USE_KQEMU +#define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG | CODE_DIRTY_FLAG)) + +int kqemu_init(CPUState *env); +int kqemu_cpu_exec(CPUState *env); +void kqemu_flush_page(CPUState *env, target_ulong addr); +void kqemu_flush(CPUState *env, int global); +void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr); +void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr); +void kqemu_cpu_interrupt(CPUState *env); +void kqemu_record_dump(void); + +static inline int kqemu_is_ok(CPUState *env) +{ + return(env->kqemu_enabled && + (env->cr[0] & CR0_PE_MASK) && + !(env->hflags & HF_INHIBIT_IRQ_MASK) && + (env->eflags & IF_MASK) && + !(env->eflags & VM_MASK) && + (env->kqemu_enabled == 2 || + ((env->hflags & HF_CPL_MASK) == 3 && + (env->eflags & IOPL_MASK) != IOPL_MASK))); +} + +#endif