X-Git-Url: http://vcs.maemo.org/git/?a=blobdiff_plain;f=cpu-i386.h;h=e6318fb7f2ddcd177f4526d8afce6cfd1a4c7bfb;hb=4690764bba3a489d5180106d08970ced59113e22;hp=e528f61981a954a7919f51df8ca018ffdaf6dfa3;hpb=4b74fe1f0013c622693b26141c0ed031a284a45a;p=qemu diff --git a/cpu-i386.h b/cpu-i386.h index e528f61..e6318fb 100644 --- a/cpu-i386.h +++ b/cpu-i386.h @@ -1,9 +1,26 @@ -/* NOTE: this header is included in op-i386.c where global register - variable are used. Care must be used when including glibc headers. +/* + * i386 virtual CPU header + * + * Copyright (c) 2003 Fabrice Bellard + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */ #ifndef CPU_I386_H #define CPU_I386_H +#include "config.h" #include #define R_EAX 0 @@ -31,6 +48,25 @@ #define R_FS 4 #define R_GS 5 +/* segment descriptor fields */ +#define DESC_G_MASK (1 << 23) +#define DESC_B_SHIFT 22 +#define DESC_B_MASK (1 << DESC_B_SHIFT) +#define DESC_AVL_MASK (1 << 20) +#define DESC_P_MASK (1 << 15) +#define DESC_DPL_SHIFT 13 +#define DESC_S_MASK (1 << 12) +#define DESC_TYPE_SHIFT 8 +#define DESC_A_MASK (1 << 8) + +#define DESC_CS_MASK (1 << 11) +#define DESC_C_MASK (1 << 10) +#define DESC_R_MASK (1 << 9) + +#define DESC_E_MASK (1 << 10) +#define DESC_W_MASK (1 << 9) + +/* eflags masks */ #define CC_C 0x0001 #define CC_P 0x0004 #define CC_A 0x0010 @@ -38,36 +74,87 @@ #define CC_S 0x0080 #define CC_O 0x0800 -#define TRAP_FLAG 0x0100 -#define INTERRUPT_FLAG 0x0200 -#define DIRECTION_FLAG 0x0400 -#define IOPL_FLAG_MASK 0x3000 -#define NESTED_FLAG 0x4000 -#define BYTE_FL 0x8000 /* Intel reserved! */ -#define RF_FLAG 0x10000 -#define VM_FLAG 0x20000 -/* AC 0x40000 */ - -#define EXCP00_DIVZ 1 -#define EXCP01_SSTP 2 -#define EXCP02_NMI 3 -#define EXCP03_INT3 4 -#define EXCP04_INTO 5 -#define EXCP05_BOUND 6 -#define EXCP06_ILLOP 7 -#define EXCP07_PREX 8 -#define EXCP08_DBLE 9 -#define EXCP09_XERR 10 -#define EXCP0A_TSS 11 -#define EXCP0B_NOSEG 12 -#define EXCP0C_STACK 13 -#define EXCP0D_GPF 14 -#define EXCP0E_PAGE 15 -#define EXCP10_COPR 17 -#define EXCP11_ALGN 18 -#define EXCP12_MCHK 19 - -#define EXCP_SIGNAL 256 /* async signal */ +#define TF_MASK 0x00000100 +#define IF_MASK 0x00000200 +#define DF_MASK 0x00000400 +#define IOPL_MASK 0x00003000 +#define NT_MASK 0x00004000 +#define RF_MASK 0x00010000 +#define VM_MASK 0x00020000 +#define AC_MASK 0x00040000 +#define VIF_MASK 0x00080000 +#define VIP_MASK 0x00100000 +#define ID_MASK 0x00200000 + +#define CR0_PE_MASK (1 << 0) +#define CR0_TS_MASK (1 << 3) +#define CR0_WP_MASK (1 << 16) +#define CR0_AM_MASK (1 << 18) +#define CR0_PG_MASK (1 << 31) + +#define CR4_VME_MASK (1 << 0) +#define CR4_PVI_MASK (1 << 1) +#define CR4_TSD_MASK (1 << 2) +#define CR4_DE_MASK (1 << 3) +#define CR4_PSE_MASK (1 << 4) + +#define PG_PRESENT_BIT 0 +#define PG_RW_BIT 1 +#define PG_USER_BIT 2 +#define PG_PWT_BIT 3 +#define PG_PCD_BIT 4 +#define PG_ACCESSED_BIT 5 +#define PG_DIRTY_BIT 6 +#define PG_PSE_BIT 7 +#define PG_GLOBAL_BIT 8 + +#define PG_PRESENT_MASK (1 << PG_PRESENT_BIT) +#define PG_RW_MASK (1 << PG_RW_BIT) +#define PG_USER_MASK (1 << PG_USER_BIT) +#define PG_PWT_MASK (1 << PG_PWT_BIT) +#define PG_PCD_MASK (1 << PG_PCD_BIT) +#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT) +#define PG_DIRTY_MASK (1 << PG_DIRTY_BIT) +#define PG_PSE_MASK (1 << PG_PSE_BIT) +#define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT) + +#define PG_ERROR_W_BIT 1 + +#define PG_ERROR_P_MASK 0x01 +#define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT) +#define PG_ERROR_U_MASK 0x04 +#define PG_ERROR_RSVD_MASK 0x08 + +#define MSR_IA32_APICBASE 0x1b +#define MSR_IA32_APICBASE_BSP (1<<8) +#define MSR_IA32_APICBASE_ENABLE (1<<11) +#define MSR_IA32_APICBASE_BASE (0xfffff<<12) + +#define MSR_IA32_SYSENTER_CS 0x174 +#define MSR_IA32_SYSENTER_ESP 0x175 +#define MSR_IA32_SYSENTER_EIP 0x176 + +#define EXCP00_DIVZ 0 +#define EXCP01_SSTP 1 +#define EXCP02_NMI 2 +#define EXCP03_INT3 3 +#define EXCP04_INTO 4 +#define EXCP05_BOUND 5 +#define EXCP06_ILLOP 6 +#define EXCP07_PREX 7 +#define EXCP08_DBLE 8 +#define EXCP09_XERR 9 +#define EXCP0A_TSS 10 +#define EXCP0B_NOSEG 11 +#define EXCP0C_STACK 12 +#define EXCP0D_GPF 13 +#define EXCP0E_PAGE 14 +#define EXCP10_COPR 16 +#define EXCP11_ALGN 17 +#define EXCP12_MCHK 18 + +#define EXCP_INTERRUPT 256 /* async interruption */ +#define EXCP_HLT 257 /* hlt instruction reached */ enum { CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ @@ -123,11 +210,20 @@ typedef long double CPU86_LDouble; typedef double CPU86_LDouble; #endif +typedef struct SegmentCache { + uint32_t selector; + uint8_t *base; + uint32_t limit; + uint32_t flags; +} SegmentCache; + typedef struct CPUX86State { /* standard registers */ uint32_t regs[8]; - uint32_t pc; /* cs_case + eip value */ - uint32_t eflags; + uint32_t eip; + uint32_t eflags; /* eflags register. During CPU emulation, CC + flags and DF are set to zero because they are + stored elsewhere */ /* emulator internal eflags handling */ uint32_t cc_src; @@ -135,9 +231,6 @@ typedef struct CPUX86State { uint32_t cc_op; int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */ - /* segments */ - uint8_t *segs_base[6]; - /* FPU state */ unsigned int fpstt; /* top of stack index */ unsigned int fpus; @@ -145,105 +238,83 @@ typedef struct CPUX86State { uint8_t fptags[8]; /* 0 = valid, 1 = empty */ CPU86_LDouble fpregs[8]; - /* segments */ - uint32_t segs[6]; - /* emulator internal variables */ - CPU86_LDouble ft0; - - /* exception handling */ + union { + float f; + double d; + int i32; + int64_t i64; + } fp_convert; + + /* segments */ + SegmentCache segs[6]; /* selector values */ + SegmentCache ldt; + SegmentCache tr; + SegmentCache gdt; /* only base and limit are used */ + SegmentCache idt; /* only base and limit are used */ + + /* sysenter registers */ + uint32_t sysenter_cs; + uint32_t sysenter_esp; + uint32_t sysenter_eip; + + /* exception/interrupt handling */ jmp_buf jmp_env; int exception_index; + int error_code; + int exception_is_int; + int exception_next_eip; + struct TranslationBlock *current_tb; /* currently executing TB */ + uint32_t cr[5]; /* NOTE: cr1 is unused */ + uint32_t dr[8]; /* debug registers */ + int interrupt_request; + int user_mode_only; /* user mode only simulation */ + + /* user data */ + void *opaque; } CPUX86State; -static inline int ldub(void *ptr) -{ - return *(uint8_t *)ptr; -} - -static inline int ldsb(void *ptr) -{ - return *(int8_t *)ptr; -} - -static inline int lduw(void *ptr) -{ - return *(uint16_t *)ptr; -} - -static inline int ldsw(void *ptr) -{ - return *(int16_t *)ptr; -} - -static inline int ldl(void *ptr) -{ - return *(uint32_t *)ptr; -} - -static inline uint64_t ldq(void *ptr) -{ - return *(uint64_t *)ptr; -} - -static inline void stb(void *ptr, int v) -{ - *(uint8_t *)ptr = v; -} - -static inline void stw(void *ptr, int v) -{ - *(uint16_t *)ptr = v; -} - -static inline void stl(void *ptr, int v) -{ - *(uint32_t *)ptr = v; -} - -static inline void stq(void *ptr, int v) -{ - *(uint64_t *)ptr = v; -} - -/* float access */ - -static inline float ldfl(void *ptr) -{ - return *(float *)ptr; -} - -static inline double ldfq(void *ptr) -{ - return *(double *)ptr; -} - -static inline void stfl(void *ptr, float v) -{ - *(float *)ptr = v; -} - -static inline void stfq(void *ptr, double v) -{ - *(double *)ptr = v; -} - #ifndef IN_OP_I386 -void cpu_x86_outb(int addr, int val); -void cpu_x86_outw(int addr, int val); -void cpu_x86_outl(int addr, int val); -int cpu_x86_inb(int addr); -int cpu_x86_inw(int addr); -int cpu_x86_inl(int addr); +void cpu_x86_outb(CPUX86State *env, int addr, int val); +void cpu_x86_outw(CPUX86State *env, int addr, int val); +void cpu_x86_outl(CPUX86State *env, int addr, int val); +int cpu_x86_inb(CPUX86State *env, int addr); +int cpu_x86_inw(CPUX86State *env, int addr); +int cpu_x86_inl(CPUX86State *env, int addr); #endif CPUX86State *cpu_x86_init(void); int cpu_x86_exec(CPUX86State *s); void cpu_x86_close(CPUX86State *s); - -/* internal functions */ -int cpu_x86_gen_code(uint8_t *gen_code_buf, int *gen_code_size_ptr, - uint8_t *pc_start); +int cpu_x86_get_pic_interrupt(CPUX86State *s); + +/* needed to load some predefinied segment registers */ +void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector); + +/* simulate fsave/frstor */ +void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32); +void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32); + +/* you can call this signal handler from your SIGBUS and SIGSEGV + signal handlers to inform the virtual CPU of exceptions. non zero + is returned if the signal was handled by the virtual CPU. */ +struct siginfo; +int cpu_x86_signal_handler(int host_signum, struct siginfo *info, + void *puc); + +/* MMU defines */ +void cpu_x86_init_mmu(CPUX86State *env); +extern int phys_ram_size; +extern int phys_ram_fd; +extern uint8_t *phys_ram_base; + +/* used to debug */ +#define X86_DUMP_FPU 0x0001 /* dump FPU state too */ +#define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */ +void cpu_x86_dump_state(CPUX86State *env, FILE *f, int flags); + +#define TARGET_PAGE_BITS 12 +#include "cpu-all.h" #endif /* CPU_I386_H */