X-Git-Url: http://vcs.maemo.org/git/?a=blobdiff_plain;f=cpu-exec.c;h=c7cd6078878ec3de34612111ee3ac1f6227e9301;hb=51a36cb2cb38bee2834de8add532cb66e4e6b884;hp=053c0cc5dd0fdc27f6f1c70313e8dedd05de8a8c;hpb=d1d9f42119b2eb10e86f062e9e62dfcec3e199b1;p=qemu diff --git a/cpu-exec.c b/cpu-exec.c index 053c0cc..c7cd607 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -1,7 +1,7 @@ /* * i386 emulator main execution loop * - * Copyright (c) 2003 Fabrice Bellard + * Copyright (c) 2003-2005 Fabrice Bellard * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public @@ -47,6 +47,9 @@ void cpu_loop_exit(void) longjmp(env->jmp_env, 1); } #endif +#ifndef TARGET_SPARC +#define reg_T2 +#endif /* exit the current TB from a signal handler. The host registers are restored in a state compatible with the CPU emulator @@ -74,8 +77,12 @@ void cpu_resume_from_signal(CPUState *env1, void *puc) int cpu_exec(CPUState *env1) { - int saved_T0, saved_T1, saved_T2; + int saved_T0, saved_T1; +#if defined(reg_T2) + int saved_T2; +#endif CPUState *saved_env; +#if defined(TARGET_I386) #ifdef reg_EAX int saved_EAX; #endif @@ -100,21 +107,29 @@ int cpu_exec(CPUState *env1) #ifdef reg_EDI int saved_EDI; #endif +#elif defined(TARGET_SPARC) +#if defined(reg_REGWPTR) + uint32_t *saved_regwptr; +#endif +#endif #ifdef __sparc__ int saved_i7, tmp_T0; #endif int code_gen_size, ret, interrupt_request; void (*gen_func)(void); TranslationBlock *tb, **ptb; - uint8_t *tc_ptr, *cs_base, *pc; + target_ulong cs_base, pc; + uint8_t *tc_ptr; unsigned int flags; /* first we save global registers */ + saved_env = env; + env = env1; saved_T0 = T0; saved_T1 = T1; +#if defined(reg_T2) saved_T2 = T2; - saved_env = env; - env = env1; +#endif #ifdef __sparc__ /* we also save i7 because longjmp may not restore it */ asm volatile ("mov %%i7, %0" : "=r" (saved_i7)); @@ -123,37 +138,30 @@ int cpu_exec(CPUState *env1) #if defined(TARGET_I386) #ifdef reg_EAX saved_EAX = EAX; - EAX = env->regs[R_EAX]; #endif #ifdef reg_ECX saved_ECX = ECX; - ECX = env->regs[R_ECX]; #endif #ifdef reg_EDX saved_EDX = EDX; - EDX = env->regs[R_EDX]; #endif #ifdef reg_EBX saved_EBX = EBX; - EBX = env->regs[R_EBX]; #endif #ifdef reg_ESP saved_ESP = ESP; - ESP = env->regs[R_ESP]; #endif #ifdef reg_EBP saved_EBP = EBP; - EBP = env->regs[R_EBP]; #endif #ifdef reg_ESI saved_ESI = ESI; - ESI = env->regs[R_ESI]; #endif #ifdef reg_EDI saved_EDI = EDI; - EDI = env->regs[R_EDI]; #endif - + + env_to_regs(); /* put eflags in CPU temporary format */ CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); DF = 1 - (2 * ((env->eflags >> 10) & 1)); @@ -166,10 +174,15 @@ int cpu_exec(CPUState *env1) env->CF = (psr >> 29) & 1; env->NZF = (psr & 0xc0000000) ^ 0x40000000; env->VF = (psr << 3) & 0x80000000; - env->cpsr = psr & ~0xf0000000; + env->QF = (psr >> 27) & 1; + env->cpsr = psr & ~CACHED_CPSR_BITS; } #elif defined(TARGET_SPARC) +#if defined(reg_REGWPTR) + saved_regwptr = REGWPTR; +#endif #elif defined(TARGET_PPC) +#elif defined(TARGET_MIPS) #else #error unsupported target CPU #endif @@ -208,10 +221,40 @@ int cpu_exec(CPUState *env1) env->exception_next_eip, 0); #elif defined(TARGET_PPC) do_interrupt(env); +#elif defined(TARGET_MIPS) + do_interrupt(env); +#elif defined(TARGET_SPARC) + do_interrupt(env->exception_index); #endif } env->exception_index = -1; + } +#ifdef USE_KQEMU + if (kqemu_is_ok(env) && env->interrupt_request == 0) { + int ret; + env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); + ret = kqemu_cpu_exec(env); + /* put eflags in CPU temporary format */ + CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); + DF = 1 - (2 * ((env->eflags >> 10) & 1)); + CC_OP = CC_OP_EFLAGS; + env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); + if (ret == 1) { + /* exception */ + longjmp(env->jmp_env, 1); + } else if (ret == 2) { + /* softmmu execution needed */ + } else { + if (env->interrupt_request != 0) { + /* hardware interrupt will be executed just after */ + } else { + /* otherwise, we restart */ + longjmp(env->jmp_env, 1); + } + } } +#endif + T0 = 0; /* force lookup of first TB */ for(;;) { #ifdef __sparc__ @@ -261,6 +304,36 @@ int cpu_exec(CPUState *env1) env->interrupt_request &= ~CPU_INTERRUPT_TIMER; } } +#elif defined(TARGET_MIPS) + if ((interrupt_request & CPU_INTERRUPT_HARD) && + (env->CP0_Status & (1 << CP0St_IE)) && + (env->CP0_Cause & 0x0000FF00) && + !(env->hflags & MIPS_HFLAG_EXL) && + !(env->hflags & MIPS_HFLAG_ERL) && + !(env->hflags & MIPS_HFLAG_DM)) { + /* Raise it */ + env->exception_index = EXCP_EXT_INTERRUPT; + env->error_code = 0; + do_interrupt(env); + env->interrupt_request &= ~CPU_INTERRUPT_HARD; + } +#elif defined(TARGET_SPARC) + if ((interrupt_request & CPU_INTERRUPT_HARD) && + (env->psret != 0)) { + int pil = env->interrupt_index & 15; + int type = env->interrupt_index & 0xf0; + + if (((type == TT_EXTINT) && + (pil == 15 || pil > env->psrpil)) || + type != TT_EXTINT) { + env->interrupt_request &= ~CPU_INTERRUPT_HARD; + do_interrupt(env->interrupt_index); + env->interrupt_index = 0; + } + } else if (interrupt_request & CPU_INTERRUPT_TIMER) { + //do_interrupt(0, 0, 0, 0, 0); + env->interrupt_request &= ~CPU_INTERRUPT_TIMER; + } #endif if (interrupt_request & CPU_INTERRUPT_EXITTB) { env->interrupt_request &= ~CPU_INTERRUPT_EXITTB; @@ -279,28 +352,48 @@ int cpu_exec(CPUState *env1) } } #ifdef DEBUG_EXEC - if (loglevel & CPU_LOG_EXEC) { + if ((loglevel & CPU_LOG_EXEC)) { #if defined(TARGET_I386) /* restore flags in standard format */ +#ifdef reg_EAX env->regs[R_EAX] = EAX; +#endif +#ifdef reg_EBX env->regs[R_EBX] = EBX; +#endif +#ifdef reg_ECX env->regs[R_ECX] = ECX; +#endif +#ifdef reg_EDX env->regs[R_EDX] = EDX; +#endif +#ifdef reg_ESI env->regs[R_ESI] = ESI; +#endif +#ifdef reg_EDI env->regs[R_EDI] = EDI; +#endif +#ifdef reg_EBP env->regs[R_EBP] = EBP; +#endif +#ifdef reg_ESP env->regs[R_ESP] = ESP; +#endif env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); - cpu_x86_dump_state(env, logfile, X86_DUMP_CCOP); + cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP); env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); #elif defined(TARGET_ARM) env->cpsr = compute_cpsr(); - cpu_arm_dump_state(env, logfile, 0); - env->cpsr &= ~0xf0000000; + cpu_dump_state(env, logfile, fprintf, 0); + env->cpsr &= ~CACHED_CPSR_BITS; #elif defined(TARGET_SPARC) - cpu_sparc_dump_state (env, logfile, 0); + REGWPTR = env->regbase + (env->cwp * 16); + env->regwptr = REGWPTR; + cpu_dump_state(env, logfile, fprintf, 0); #elif defined(TARGET_PPC) - cpu_ppc_dump_state(env, logfile, 0); + cpu_dump_state(env, logfile, fprintf, 0); +#elif defined(TARGET_MIPS) + cpu_dump_state(env, logfile, fprintf, 0); #else #error unsupported target CPU #endif @@ -315,21 +408,31 @@ int cpu_exec(CPUState *env1) cs_base = env->segs[R_CS].base; pc = cs_base + env->eip; #elif defined(TARGET_ARM) - flags = 0; + flags = env->thumb | (env->vfp.vec_len << 1) + | (env->vfp.vec_stride << 4); cs_base = 0; - pc = (uint8_t *)env->regs[15]; + pc = env->regs[15]; #elif defined(TARGET_SPARC) - flags = 0; - cs_base = (uint8_t *)env->npc; - pc = (uint8_t *) env->pc; +#ifdef TARGET_SPARC64 + flags = (env->pstate << 2) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2); +#else + flags = env->psrs | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1); +#endif + cs_base = env->npc; + pc = env->pc; #elif defined(TARGET_PPC) - flags = 0; + flags = (msr_pr << MSR_PR) | (msr_fp << MSR_FP) | + (msr_se << MSR_SE) | (msr_le << MSR_LE); cs_base = 0; - pc = (uint8_t *)env->nip; + pc = env->nip; +#elif defined(TARGET_MIPS) + flags = env->hflags & MIPS_HFLAGS_TMASK; + cs_base = NULL; + pc = env->PC; #else #error unsupported CPU #endif - tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base, + tb = tb_find(&ptb, pc, cs_base, flags); if (!tb) { TranslationBlock **ptb1; @@ -340,9 +443,11 @@ int cpu_exec(CPUState *env1) spin_lock(&tb_lock); tb_invalidated_flag = 0; + + regs_to_env(); /* XXX: do it just before cpu_gen_code() */ /* find translated block using physical mappings */ - phys_pc = get_phys_addr_code(env, (unsigned long)pc); + phys_pc = get_phys_addr_code(env, pc); phys_page1 = phys_pc & TARGET_PAGE_MASK; phys_page2 = -1; h = tb_phys_hash_func(phys_pc); @@ -351,13 +456,13 @@ int cpu_exec(CPUState *env1) tb = *ptb1; if (!tb) goto not_found; - if (tb->pc == (unsigned long)pc && + if (tb->pc == pc && tb->page_addr[0] == phys_page1 && - tb->cs_base == (unsigned long)cs_base && + tb->cs_base == cs_base && tb->flags == flags) { /* check next page if needed */ if (tb->page_addr[1] != -1) { - virt_page2 = ((unsigned long)pc & TARGET_PAGE_MASK) + + virt_page2 = (pc & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE; phys_page2 = get_phys_addr_code(env, virt_page2); if (tb->page_addr[1] == phys_page2) @@ -370,27 +475,27 @@ int cpu_exec(CPUState *env1) } not_found: /* if no translated code available, then translate it now */ - tb = tb_alloc((unsigned long)pc); + tb = tb_alloc(pc); if (!tb) { /* flush must be done */ tb_flush(env); /* cannot fail at this point */ - tb = tb_alloc((unsigned long)pc); + tb = tb_alloc(pc); /* don't forget to invalidate previous TB info */ - ptb = &tb_hash[tb_hash_func((unsigned long)pc)]; + ptb = &tb_hash[tb_hash_func(pc)]; T0 = 0; } tc_ptr = code_gen_ptr; tb->tc_ptr = tc_ptr; - tb->cs_base = (unsigned long)cs_base; + tb->cs_base = cs_base; tb->flags = flags; cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size); code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1)); /* check next page if needed */ - virt_page2 = ((unsigned long)pc + tb->size - 1) & TARGET_PAGE_MASK; + virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK; phys_page2 = -1; - if (((unsigned long)pc & TARGET_PAGE_MASK) != virt_page2) { + if ((pc & TARGET_PAGE_MASK) != virt_page2) { phys_page2 = get_phys_addr_code(env, virt_page2); } tb_link_phys(tb, phys_pc, phys_page2); @@ -400,7 +505,7 @@ int cpu_exec(CPUState *env1) /* as some TB could have been invalidated because of memory exceptions while generating the code, we must recompute the hash index here */ - ptb = &tb_hash[tb_hash_func((unsigned long)pc)]; + ptb = &tb_hash[tb_hash_func(pc)]; while (*ptb != NULL) ptb = &(*ptb)->hash_next; T0 = 0; @@ -412,24 +517,25 @@ int cpu_exec(CPUState *env1) spin_unlock(&tb_lock); } #ifdef DEBUG_EXEC - if (loglevel & CPU_LOG_EXEC) { - fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n", - (long)tb->tc_ptr, (long)tb->pc, - lookup_symbol((void *)tb->pc)); + if ((loglevel & CPU_LOG_EXEC)) { + fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n", + (long)tb->tc_ptr, tb->pc, + lookup_symbol(tb->pc)); } #endif #ifdef __sparc__ T0 = tmp_T0; #endif /* see if we can patch the calling TB. */ - if (T0 != 0 + { + if (T0 != 0 #if defined(TARGET_I386) && defined(USE_CODE_COPY) && (tb->cflags & CF_CODE_COPY) == (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY) #endif ) { spin_lock(&tb_lock); - tb_add_jump((TranslationBlock *)(T0 & ~3), T0 & 3, tb); + tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb); #if defined(USE_CODE_COPY) /* propagates the FP use info */ ((TranslationBlock *)(T0 & ~3))->cflags |= @@ -437,6 +543,7 @@ int cpu_exec(CPUState *env1) #endif spin_unlock(&tb_lock); } + } tc_ptr = tb->tc_ptr; env->current_tb = tb; /* execute the generated code */ @@ -528,6 +635,15 @@ int cpu_exec(CPUState *env1) ); } } +#elif defined(__ia64) + struct fptr { + void *ip; + void *gp; + } fp; + + fp.ip = tc_ptr; + fp.gp = code_gen_buffer + 2 * (1 << 20); + (*(void (*)(void)) &fp)(); #else gen_func(); #endif @@ -543,6 +659,7 @@ int cpu_exec(CPUState *env1) #endif } } else { + env_to_regs(); } } /* for(;;) */ @@ -583,8 +700,13 @@ int cpu_exec(CPUState *env1) #endif #elif defined(TARGET_ARM) env->cpsr = compute_cpsr(); + /* XXX: Save/restore host fpu exception state?. */ #elif defined(TARGET_SPARC) +#if defined(reg_REGWPTR) + REGWPTR = saved_regwptr; +#endif #elif defined(TARGET_PPC) +#elif defined(TARGET_MIPS) #else #error unsupported target CPU #endif @@ -593,7 +715,9 @@ int cpu_exec(CPUState *env1) #endif T0 = saved_T0; T1 = saved_T1; +#if defined(reg_T2) T2 = saved_T2; +#endif env = saved_env; return ret; } @@ -622,7 +746,7 @@ void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector) if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) { selector &= 0xffff; cpu_x86_load_seg_cache(env, seg_reg, selector, - (uint8_t *)(selector << 4), 0xffff, 0); + (selector << 4), 0xffff, 0); } else { load_seg(seg_reg, selector); } @@ -636,7 +760,7 @@ void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32) saved_env = env; env = s; - helper_fsave(ptr, data32); + helper_fsave((target_ulong)ptr, data32); env = saved_env; } @@ -648,7 +772,7 @@ void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32) saved_env = env; env = s; - helper_frstor(ptr, data32); + helper_frstor((target_ulong)ptr, data32); env = saved_env; } @@ -718,19 +842,72 @@ static inline int handle_cpu_signal(unsigned long pc, unsigned long address, int is_write, sigset_t *old_set, void *puc) { - /* XXX: do more */ - return 0; + TranslationBlock *tb; + int ret; + + if (cpu_single_env) + env = cpu_single_env; /* XXX: find a correct solution for multithread */ +#if defined(DEBUG_SIGNAL) + printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", + pc, address, is_write, *(unsigned long *)old_set); +#endif + /* XXX: locking issue */ + if (is_write && page_unprotect(address, pc, puc)) { + return 1; + } + /* see if it is an MMU fault */ + ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0); + if (ret < 0) + return 0; /* not an MMU fault */ + if (ret == 0) + return 1; /* the MMU fault was handled without causing real CPU fault */ + /* now we have a real cpu fault */ + tb = tb_find_pc(pc); + if (tb) { + /* the PC is inside the translated code. It means that we have + a virtual CPU fault */ + cpu_restore_state(tb, env, pc, puc); + } + /* we restore the process signal mask as the sigreturn should + do it (XXX: use sigsetjmp) */ + sigprocmask(SIG_SETMASK, old_set, NULL); + cpu_loop_exit(); } #elif defined(TARGET_SPARC) static inline int handle_cpu_signal(unsigned long pc, unsigned long address, int is_write, sigset_t *old_set, void *puc) { + TranslationBlock *tb; + int ret; + + if (cpu_single_env) + env = cpu_single_env; /* XXX: find a correct solution for multithread */ +#if defined(DEBUG_SIGNAL) + printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", + pc, address, is_write, *(unsigned long *)old_set); +#endif /* XXX: locking issue */ if (is_write && page_unprotect(address, pc, puc)) { return 1; } - return 0; + /* see if it is an MMU fault */ + ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0); + if (ret < 0) + return 0; /* not an MMU fault */ + if (ret == 0) + return 1; /* the MMU fault was handled without causing real CPU fault */ + /* now we have a real cpu fault */ + tb = tb_find_pc(pc); + if (tb) { + /* the PC is inside the translated code. It means that we have + a virtual CPU fault */ + cpu_restore_state(tb, env, pc, puc); + } + /* we restore the process signal mask as the sigreturn should + do it (XXX: use sigsetjmp) */ + sigprocmask(SIG_SETMASK, old_set, NULL); + cpu_loop_exit(); } #elif defined (TARGET_PPC) static inline int handle_cpu_signal(unsigned long pc, unsigned long address, @@ -740,10 +917,58 @@ static inline int handle_cpu_signal(unsigned long pc, unsigned long address, TranslationBlock *tb; int ret; -#if 1 if (cpu_single_env) env = cpu_single_env; /* XXX: find a correct solution for multithread */ +#if defined(DEBUG_SIGNAL) + printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", + pc, address, is_write, *(unsigned long *)old_set); +#endif + /* XXX: locking issue */ + if (is_write && page_unprotect(address, pc, puc)) { + return 1; + } + + /* see if it is an MMU fault */ + ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0); + if (ret < 0) + return 0; /* not an MMU fault */ + if (ret == 0) + return 1; /* the MMU fault was handled without causing real CPU fault */ + + /* now we have a real cpu fault */ + tb = tb_find_pc(pc); + if (tb) { + /* the PC is inside the translated code. It means that we have + a virtual CPU fault */ + cpu_restore_state(tb, env, pc, puc); + } + if (ret == 1) { +#if 0 + printf("PF exception: NIP=0x%08x error=0x%x %p\n", + env->nip, env->error_code, tb); #endif + /* we restore the process signal mask as the sigreturn should + do it (XXX: use sigsetjmp) */ + sigprocmask(SIG_SETMASK, old_set, NULL); + do_raise_exception_err(env->exception_index, env->error_code); + } else { + /* activate soft MMU for this block */ + cpu_resume_from_signal(env, puc); + } + /* never comes here */ + return 1; +} + +#elif defined (TARGET_MIPS) +static inline int handle_cpu_signal(unsigned long pc, unsigned long address, + int is_write, sigset_t *old_set, + void *puc) +{ + TranslationBlock *tb; + int ret; + + if (cpu_single_env) + env = cpu_single_env; /* XXX: find a correct solution for multithread */ #if defined(DEBUG_SIGNAL) printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", pc, address, is_write, *(unsigned long *)old_set); @@ -783,6 +1008,7 @@ static inline int handle_cpu_signal(unsigned long pc, unsigned long address, /* never comes here */ return 1; } + #else #error unsupported target CPU #endif @@ -1020,6 +1246,40 @@ int cpu_signal_handler(int host_signum, struct siginfo *info, &uc->uc_sigmask, puc); } +#elif defined(__ia64) + +#ifndef __ISR_VALID + /* This ought to be in ... */ +# define __ISR_VALID 1 +# define si_flags _sifields._sigfault._si_pad0 +#endif + +int cpu_signal_handler(int host_signum, struct siginfo *info, void *puc) +{ + struct ucontext *uc = puc; + unsigned long ip; + int is_write = 0; + + ip = uc->uc_mcontext.sc_ip; + switch (host_signum) { + case SIGILL: + case SIGFPE: + case SIGSEGV: + case SIGBUS: + case SIGTRAP: + if (info->si_code && (info->si_flags & __ISR_VALID)) + /* ISR.W (write-access) is bit 33: */ + is_write = (info->si_isr >> 33) & 1; + break; + + default: + break; + } + return handle_cpu_signal(ip, (unsigned long)info->si_addr, + is_write, + &uc->uc_sigmask, puc); +} + #else #error host CPU specific signal handler needed