X-Git-Url: http://vcs.maemo.org/git/?a=blobdiff_plain;f=cpu-exec.c;h=b6df3bef18de4274df79523d032ff4591c89700e;hb=0986ac3be2989f37cec262f3370bac77999a52bf;hp=f411eccf8138a960dedc0a99abea8081544ad92b;hpb=b5ff1b3127119aa430a6fd309591d584803b7b6e;p=qemu diff --git a/cpu-exec.c b/cpu-exec.c index f411ecc..b6df3be 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -126,7 +126,7 @@ static TranslationBlock *tb_find_slow(target_ulong pc, /* cannot fail at this point */ tb = tb_alloc(pc); /* don't forget to invalidate previous TB info */ - T0 = 0; + tb_invalidated_flag = 1; } tc_ptr = code_gen_ptr; tb->tc_ptr = tc_ptr; @@ -144,12 +144,6 @@ static TranslationBlock *tb_find_slow(target_ulong pc, tb_link_phys(tb, phys_pc, phys_page2); found: - if (tb_invalidated_flag) { - /* as some TB could have been invalidated because - of memory exceptions while generating the code, we - must recompute the hash index here */ - T0 = 0; - } /* we add the TB in the virtual pc hash table */ env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb; spin_unlock(&tb_lock); @@ -175,6 +169,8 @@ static inline TranslationBlock *tb_find_fast(void) | (env->vfp.vec_stride << 4); if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) flags |= (1 << 6); + if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) + flags |= (1 << 7); cs_base = 0; pc = env->regs[15]; #elif defined(TARGET_SPARC) @@ -191,9 +187,13 @@ static inline TranslationBlock *tb_find_fast(void) cs_base = 0; pc = env->nip; #elif defined(TARGET_MIPS) - flags = env->hflags & MIPS_HFLAGS_TMASK; - cs_base = NULL; + flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK); + cs_base = 0; pc = env->PC; +#elif defined(TARGET_SH4) + flags = env->sr & (SR_MD | SR_RB); + cs_base = 0; /* XXXXX */ + pc = env->pc; #else #error unsupported CPU #endif @@ -201,6 +201,14 @@ static inline TranslationBlock *tb_find_fast(void) if (__builtin_expect(!tb || tb->pc != pc || tb->cs_base != cs_base || tb->flags != flags, 0)) { tb = tb_find_slow(pc, cs_base, flags); + /* Note: we do it here to avoid a gcc bug on Mac OS X when + doing it in tb_find_slow */ + if (tb_invalidated_flag) { + /* as some TB could have been invalidated because + of memory exceptions while generating the code, we + must recompute the hash index here */ + T0 = 0; + } } return tb; } @@ -265,11 +273,40 @@ int cpu_exec(CPUState *env1) } } #elif defined(TARGET_PPC) - if (env1->msr[MSR_POW]) { + if (env1->halted) { if (env1->msr[MSR_EE] && (env1->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER))) { - env1->msr[MSR_POW] = 0; + env1->halted = 0; + } else { + return EXCP_HALTED; + } + } +#elif defined(TARGET_SPARC) + if (env1->halted) { + if ((env1->interrupt_request & CPU_INTERRUPT_HARD) && + (env1->psret != 0)) { + env1->halted = 0; + } else { + return EXCP_HALTED; + } + } +#elif defined(TARGET_ARM) + if (env1->halted) { + /* An interrupt wakes the CPU even if the I and F CPSR bits are + set. */ + if (env1->interrupt_request + & (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD)) { + env1->halted = 0; + } else { + return EXCP_HALTED; + } + } +#elif defined(TARGET_MIPS) + if (env1->halted) { + if (env1->interrupt_request & + (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) { + env1->halted = 0; } else { return EXCP_HALTED; } @@ -330,6 +367,8 @@ int cpu_exec(CPUState *env1) #endif #elif defined(TARGET_PPC) #elif defined(TARGET_MIPS) +#elif defined(TARGET_SH4) + /* XXXXX */ #else #error unsupported target CPU #endif @@ -374,6 +413,8 @@ int cpu_exec(CPUState *env1) do_interrupt(env->exception_index); #elif defined(TARGET_ARM) do_interrupt(env); +#elif defined(TARGET_SH4) + do_interrupt(env); #endif } env->exception_index = -1; @@ -502,7 +543,10 @@ int cpu_exec(CPUState *env1) } else if (interrupt_request & CPU_INTERRUPT_TIMER) { //do_interrupt(0, 0, 0, 0, 0); env->interrupt_request &= ~CPU_INTERRUPT_TIMER; - } + } else if (interrupt_request & CPU_INTERRUPT_HALT) { + env1->halted = 1; + return EXCP_HALTED; + } #elif defined(TARGET_ARM) if (interrupt_request & CPU_INTERRUPT_FIQ && !(env->uncached_cpsr & CPSR_F)) { @@ -514,7 +558,11 @@ int cpu_exec(CPUState *env1) env->exception_index = EXCP_IRQ; do_interrupt(env); } +#elif defined(TARGET_SH4) + /* XXXXX */ #endif + /* Don't use the cached interupt_request value, + do_interrupt may have updated the EXITTB flag. */ if (env->interrupt_request & CPU_INTERRUPT_EXITTB) { env->interrupt_request &= ~CPU_INTERRUPT_EXITTB; /* ensure that no TB jump will be modified as @@ -572,6 +620,8 @@ int cpu_exec(CPUState *env1) cpu_dump_state(env, logfile, fprintf, 0); #elif defined(TARGET_MIPS) cpu_dump_state(env, logfile, fprintf, 0); +#elif defined(TARGET_SH4) + cpu_dump_state(env, logfile, fprintf, 0); #else #error unsupported target CPU #endif @@ -593,6 +643,9 @@ int cpu_exec(CPUState *env1) jump. */ { if (T0 != 0 && +#if USE_KQEMU + (env->kqemu_enabled != 2) && +#endif tb->page_addr[1] == -1 #if defined(TARGET_I386) && defined(USE_CODE_COPY) && (tb->cflags & CF_CODE_COPY) == @@ -722,6 +775,13 @@ int cpu_exec(CPUState *env1) T0 = 0; } #endif +#if defined(USE_KQEMU) +#define MIN_CYCLE_BEFORE_SWITCH (100 * 1000) + if (kqemu_is_ok(env) && + (cpu_get_time_fast() - env->last_io_time) >= MIN_CYCLE_BEFORE_SWITCH) { + cpu_loop_exit(); + } +#endif } } else { env_to_regs(); @@ -771,6 +831,8 @@ int cpu_exec(CPUState *env1) #endif #elif defined(TARGET_PPC) #elif defined(TARGET_MIPS) +#elif defined(TARGET_SH4) + /* XXXXX */ #else #error unsupported target CPU #endif @@ -867,7 +929,7 @@ static inline int handle_cpu_signal(unsigned long pc, unsigned long address, pc, address, is_write, *(unsigned long *)old_set); #endif /* XXX: locking issue */ - if (is_write && page_unprotect(address, pc, puc)) { + if (is_write && page_unprotect(h2g(address), pc, puc)) { return 1; } @@ -893,7 +955,7 @@ static inline int handle_cpu_signal(unsigned long pc, unsigned long address, /* we restore the process signal mask as the sigreturn should do it (XXX: use sigsetjmp) */ sigprocmask(SIG_SETMASK, old_set, NULL); - raise_exception_err(EXCP0E_PAGE, env->error_code); + raise_exception_err(env->exception_index, env->error_code); } else { /* activate soft MMU for this block */ env->hflags |= HF_SOFTMMU_MASK; @@ -918,7 +980,7 @@ static inline int handle_cpu_signal(unsigned long pc, unsigned long address, pc, address, is_write, *(unsigned long *)old_set); #endif /* XXX: locking issue */ - if (is_write && page_unprotect(address, pc, puc)) { + if (is_write && page_unprotect(h2g(address), pc, puc)) { return 1; } /* see if it is an MMU fault */ @@ -954,7 +1016,7 @@ static inline int handle_cpu_signal(unsigned long pc, unsigned long address, pc, address, is_write, *(unsigned long *)old_set); #endif /* XXX: locking issue */ - if (is_write && page_unprotect(address, pc, puc)) { + if (is_write && page_unprotect(h2g(address), pc, puc)) { return 1; } /* see if it is an MMU fault */ @@ -990,7 +1052,7 @@ static inline int handle_cpu_signal(unsigned long pc, unsigned long address, pc, address, is_write, *(unsigned long *)old_set); #endif /* XXX: locking issue */ - if (is_write && page_unprotect(address, pc, puc)) { + if (is_write && page_unprotect(h2g(address), pc, puc)) { return 1; } @@ -1040,12 +1102,12 @@ static inline int handle_cpu_signal(unsigned long pc, unsigned long address, pc, address, is_write, *(unsigned long *)old_set); #endif /* XXX: locking issue */ - if (is_write && page_unprotect(address, pc, puc)) { + if (is_write && page_unprotect(h2g(address), pc, puc)) { return 1; } /* see if it is an MMU fault */ - ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0); + ret = cpu_mips_handle_mmu_fault(env, address, is_write, 1, 0); if (ret < 0) return 0; /* not an MMU fault */ if (ret == 0) @@ -1075,6 +1137,55 @@ static inline int handle_cpu_signal(unsigned long pc, unsigned long address, return 1; } +#elif defined (TARGET_SH4) +static inline int handle_cpu_signal(unsigned long pc, unsigned long address, + int is_write, sigset_t *old_set, + void *puc) +{ + TranslationBlock *tb; + int ret; + + if (cpu_single_env) + env = cpu_single_env; /* XXX: find a correct solution for multithread */ +#if defined(DEBUG_SIGNAL) + printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n", + pc, address, is_write, *(unsigned long *)old_set); +#endif + /* XXX: locking issue */ + if (is_write && page_unprotect(h2g(address), pc, puc)) { + return 1; + } + + /* see if it is an MMU fault */ + ret = cpu_sh4_handle_mmu_fault(env, address, is_write, 1, 0); + if (ret < 0) + return 0; /* not an MMU fault */ + if (ret == 0) + return 1; /* the MMU fault was handled without causing real CPU fault */ + + /* now we have a real cpu fault */ + tb = tb_find_pc(pc); + if (tb) { + /* the PC is inside the translated code. It means that we have + a virtual CPU fault */ + cpu_restore_state(tb, env, pc, puc); + } + if (ret == 1) { +#if 0 + printf("PF exception: NIP=0x%08x error=0x%x %p\n", + env->nip, env->error_code, tb); +#endif + /* we restore the process signal mask as the sigreturn should + do it (XXX: use sigsetjmp) */ + sigprocmask(SIG_SETMASK, old_set, NULL); + // do_raise_exception_err(env->exception_index, env->error_code); + } else { + /* activate soft MMU for this block */ + cpu_resume_from_signal(env, puc); + } + /* never comes here */ + return 1; +} #else #error unsupported target CPU #endif @@ -1317,7 +1428,6 @@ int cpu_signal_handler(int host_signum, struct siginfo *info, #ifndef __ISR_VALID /* This ought to be in ... */ # define __ISR_VALID 1 -# define si_flags _sifields._sigfault._si_pad0 #endif int cpu_signal_handler(int host_signum, struct siginfo *info, void *puc) @@ -1333,7 +1443,7 @@ int cpu_signal_handler(int host_signum, struct siginfo *info, void *puc) case SIGSEGV: case SIGBUS: case SIGTRAP: - if (info->si_code && (info->si_flags & __ISR_VALID)) + if (info->si_code && (info->si_segvflags & __ISR_VALID)) /* ISR.W (write-access) is bit 33: */ is_write = (info->si_isr >> 33) & 1; break;