X-Git-Url: http://vcs.maemo.org/git/?a=blobdiff_plain;f=cpu-defs.h;h=fda3044bcd0b4885b0666e40654fa92c6f5d022b;hb=HEAD;hp=139dca2e79b7097f0e1f2717fb7eeb473207b56f;hpb=87ecb68bdf8a3e40ef885ddbb7ca1797dca40ebf;p=qemu diff --git a/cpu-defs.h b/cpu-defs.h index 139dca2..fda3044 100644 --- a/cpu-defs.h +++ b/cpu-defs.h @@ -15,7 +15,7 @@ * * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA */ #ifndef CPU_DEFS_H #define CPU_DEFS_H @@ -27,20 +27,15 @@ #include "config.h" #include #include +#include #include "osdep.h" +#include "sys-queue.h" +#include "targphys.h" #ifndef TARGET_LONG_BITS #error TARGET_LONG_BITS must be defined before including this header #endif -#ifndef TARGET_PHYS_ADDR_BITS -#if TARGET_LONG_BITS >= HOST_LONG_BITS -#define TARGET_PHYS_ADDR_BITS TARGET_LONG_BITS -#else -#define TARGET_PHYS_ADDR_BITS HOST_LONG_BITS -#endif -#endif - #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8) /* target_ulong is the type of a virtual address */ @@ -60,33 +55,12 @@ typedef uint64_t target_ulong; #error TARGET_LONG_SIZE undefined #endif -/* target_phys_addr_t is the type of a physical address (its size can - be different from 'target_ulong'). We have sizeof(target_phys_addr) - = max(sizeof(unsigned long), - sizeof(size_of_target_physical_address)) because we must pass a - host pointer to memory operations in some cases */ - -#if TARGET_PHYS_ADDR_BITS == 32 -typedef uint32_t target_phys_addr_t; -#define TARGET_FMT_plx "%08x" -#elif TARGET_PHYS_ADDR_BITS == 64 -typedef uint64_t target_phys_addr_t; -#define TARGET_FMT_plx "%016" PRIx64 -#else -#error TARGET_PHYS_ADDR_BITS undefined -#endif - -/* address in the RAM (different from a physical address) */ -typedef unsigned long ram_addr_t; - #define HOST_LONG_SIZE (HOST_LONG_BITS / 8) #define EXCP_INTERRUPT 0x10000 /* async interruption */ #define EXCP_HLT 0x10001 /* hlt instruction reached */ #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */ #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */ -#define MAX_BREAKPOINTS 32 -#define MAX_WATCHPOINTS 32 #define TB_JMP_CACHE_BITS 12 #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) @@ -102,50 +76,126 @@ typedef unsigned long ram_addr_t; #define CPU_TLB_BITS 8 #define CPU_TLB_SIZE (1 << CPU_TLB_BITS) +#if TARGET_PHYS_ADDR_BITS == 32 && TARGET_LONG_BITS == 32 +#define CPU_TLB_ENTRY_BITS 4 +#else +#define CPU_TLB_ENTRY_BITS 5 +#endif + typedef struct CPUTLBEntry { - /* bit 31 to TARGET_PAGE_BITS : virtual address - bit TARGET_PAGE_BITS-1..IO_MEM_SHIFT : if non zero, memory io - zone number + /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address + bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not + go directly to ram. bit 3 : indicates that the entry is invalid bit 2..0 : zero */ target_ulong addr_read; target_ulong addr_write; target_ulong addr_code; - /* addend to virtual address to get physical address */ + /* Addend to virtual address to get physical address. IO accesses + use the corresponding iotlb value. */ +#if TARGET_PHYS_ADDR_BITS == 64 + /* on i386 Linux make sure it is aligned */ + target_phys_addr_t addend __attribute__((aligned(8))); +#else target_phys_addr_t addend; +#endif + /* padding to get a power of two size */ + uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) - + (sizeof(target_ulong) * 3 + + ((-sizeof(target_ulong) * 3) & (sizeof(target_phys_addr_t) - 1)) + + sizeof(target_phys_addr_t))]; } CPUTLBEntry; +#ifdef WORDS_BIGENDIAN +typedef struct icount_decr_u16 { + uint16_t high; + uint16_t low; +} icount_decr_u16; +#else +typedef struct icount_decr_u16 { + uint16_t low; + uint16_t high; +} icount_decr_u16; +#endif + +struct kvm_run; +struct KVMState; + +typedef struct CPUBreakpoint { + target_ulong pc; + int flags; /* BP_* */ + TAILQ_ENTRY(CPUBreakpoint) entry; +} CPUBreakpoint; + +typedef struct CPUWatchpoint { + target_ulong vaddr; + target_ulong len_mask; + int flags; /* BP_* */ + TAILQ_ENTRY(CPUWatchpoint) entry; +} CPUWatchpoint; + +#define CPU_TEMP_BUF_NLONGS 128 #define CPU_COMMON \ struct TranslationBlock *current_tb; /* currently executing TB */ \ /* soft mmu support */ \ - /* in order to avoid passing too many arguments to the memory \ - write helpers, we store some rarely used information in the CPU \ + /* in order to avoid passing too many arguments to the MMIO \ + helpers, we store some rarely used information in the CPU \ context) */ \ - unsigned long mem_write_pc; /* host pc at which the memory was \ - written */ \ - target_ulong mem_write_vaddr; /* target virtual addr at which the \ - memory was written */ \ + unsigned long mem_io_pc; /* host pc at which the memory was \ + accessed */ \ + target_ulong mem_io_vaddr; /* target virtual addr at which the \ + memory was accessed */ \ + uint32_t halted; /* Nonzero if the CPU is in suspend state */ \ + uint32_t stop; /* Stop request */ \ + uint32_t stopped; /* Artificially stopped */ \ + uint32_t interrupt_request; \ + volatile sig_atomic_t exit_request; \ /* The meaning of the MMU modes is defined in the target code. */ \ CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \ + target_phys_addr_t iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \ struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \ + /* buffer for temporaries in the code generator */ \ + long temp_buf[CPU_TEMP_BUF_NLONGS]; \ + \ + int64_t icount_extra; /* Instructions until next timer event. */ \ + /* Number of cycles left, with interrupt flag in high bit. \ + This allows a single read-compare-cbranch-write sequence to test \ + for both decrementer underflow and exceptions. */ \ + union { \ + uint32_t u32; \ + icount_decr_u16 u16; \ + } icount_decr; \ + uint32_t can_do_io; /* nonzero if memory mapped IO is safe. */ \ \ /* from this point: preserved by CPU reset */ \ /* ice debug support */ \ - target_ulong breakpoints[MAX_BREAKPOINTS]; \ - int nb_breakpoints; \ + TAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; \ int singlestep_enabled; \ \ - struct { \ - target_ulong vaddr; \ - target_phys_addr_t addend; \ - } watchpoint[MAX_WATCHPOINTS]; \ - int nb_watchpoints; \ - int watchpoint_hit; \ + TAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; \ + CPUWatchpoint *watchpoint_hit; \ + \ + struct GDBRegisterState *gdb_regs; \ \ - void *next_cpu; /* next CPU sharing TB cache */ \ + /* Core interrupt code */ \ + jmp_buf jmp_env; \ + int exception_index; \ + \ + CPUState *next_cpu; /* next CPU sharing TB cache */ \ int cpu_index; /* CPU index (informative) */ \ + uint32_t host_tid; /* host thread ID */ \ + int numa_node; /* NUMA node this cpu is belonging to */ \ + int running; /* Nonzero if cpu is currently running(usermode). */ \ /* user data */ \ - void *opaque; + void *opaque; \ + \ + uint32_t created; \ + struct QemuThread *thread; \ + struct QemuCond *halt_cond; \ + const char *cpu_model_str; \ + struct KVMState *kvm_state; \ + struct kvm_run *kvm_run; \ + int kvm_fd; #endif