X-Git-Url: http://vcs.maemo.org/git/?a=blobdiff_plain;f=cpu-all.h;h=9b617fcc7c5b188b3478eaa3cfb447095b7e1fdc;hb=75d62a585629cdc1ae0d530189653cb1d8d9c53c;hp=b374fe86b059d2e3573b097045949652d2e0639b;hpb=ba3c64fb476d57c35013970ac444f04f35893ca9;p=qemu diff --git a/cpu-all.h b/cpu-all.h index b374fe8..9b617fc 100644 --- a/cpu-all.h +++ b/cpu-all.h @@ -584,22 +584,41 @@ static inline void stfq_be_p(void *ptr, float64 v) /* MMU memory access macros */ +#if defined(CONFIG_USER_ONLY) +/* On some host systems the guest address space is reserved on the host. + * This allows the guest address space to be offset to a convenient location. + */ +//#define GUEST_BASE 0x20000000 +#define GUEST_BASE 0 + +/* All direct uses of g2h and h2g need to go away for usermode softmmu. */ +#define g2h(x) ((void *)((unsigned long)(x) + GUEST_BASE)) +#define h2g(x) ((target_ulong)(x - GUEST_BASE)) + +#define saddr(x) g2h(x) +#define laddr(x) g2h(x) + +#else /* !CONFIG_USER_ONLY */ /* NOTE: we use double casts if pointers and target_ulong have different sizes */ -#define ldub_raw(p) ldub_p((uint8_t *)(long)(p)) -#define ldsb_raw(p) ldsb_p((uint8_t *)(long)(p)) -#define lduw_raw(p) lduw_p((uint8_t *)(long)(p)) -#define ldsw_raw(p) ldsw_p((uint8_t *)(long)(p)) -#define ldl_raw(p) ldl_p((uint8_t *)(long)(p)) -#define ldq_raw(p) ldq_p((uint8_t *)(long)(p)) -#define ldfl_raw(p) ldfl_p((uint8_t *)(long)(p)) -#define ldfq_raw(p) ldfq_p((uint8_t *)(long)(p)) -#define stb_raw(p, v) stb_p((uint8_t *)(long)(p), v) -#define stw_raw(p, v) stw_p((uint8_t *)(long)(p), v) -#define stl_raw(p, v) stl_p((uint8_t *)(long)(p), v) -#define stq_raw(p, v) stq_p((uint8_t *)(long)(p), v) -#define stfl_raw(p, v) stfl_p((uint8_t *)(long)(p), v) -#define stfq_raw(p, v) stfq_p((uint8_t *)(long)(p), v) +#define saddr(x) (uint8_t *)(long)(x) +#define laddr(x) (uint8_t *)(long)(x) +#endif + +#define ldub_raw(p) ldub_p(laddr((p))) +#define ldsb_raw(p) ldsb_p(laddr((p))) +#define lduw_raw(p) lduw_p(laddr((p))) +#define ldsw_raw(p) ldsw_p(laddr((p))) +#define ldl_raw(p) ldl_p(laddr((p))) +#define ldq_raw(p) ldq_p(laddr((p))) +#define ldfl_raw(p) ldfl_p(laddr((p))) +#define ldfq_raw(p) ldfq_p(laddr((p))) +#define stb_raw(p, v) stb_p(saddr((p)), v) +#define stw_raw(p, v) stw_p(saddr((p)), v) +#define stl_raw(p, v) stl_p(saddr((p)), v) +#define stq_raw(p, v) stq_p(saddr((p)), v) +#define stfl_raw(p, v) stfl_p(saddr((p)), v) +#define stfq_raw(p, v) stfq_p(saddr((p)), v) #if defined(CONFIG_USER_ONLY) @@ -648,6 +667,7 @@ static inline void stfq_be_p(void *ptr, float64 v) #define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1) #define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK) +/* ??? These should be the larger of unsigned long and target_ulong. */ extern unsigned long qemu_real_host_page_size; extern unsigned long qemu_host_page_bits; extern unsigned long qemu_host_page_size; @@ -666,9 +686,9 @@ extern unsigned long qemu_host_page_mask; #define PAGE_WRITE_ORG 0x0010 void page_dump(FILE *f); -int page_get_flags(unsigned long address); -void page_set_flags(unsigned long start, unsigned long end, int flags); -void page_unprotect_range(uint8_t *data, unsigned long data_size); +int page_get_flags(target_ulong address); +void page_set_flags(target_ulong start, target_ulong end, int flags); +void page_unprotect_range(target_ulong data, target_ulong data_size); #define SINGLE_CPU_DEFINES #ifdef SINGLE_CPU_DEFINES @@ -705,6 +725,13 @@ void page_unprotect_range(uint8_t *data, unsigned long data_size); #define cpu_gen_code cpu_ppc_gen_code #define cpu_signal_handler cpu_ppc_signal_handler +#elif defined(TARGET_M68K) +#define CPUState CPUM68KState +#define cpu_init cpu_m68k_init +#define cpu_exec cpu_m68k_exec +#define cpu_gen_code cpu_m68k_gen_code +#define cpu_signal_handler cpu_m68k_signal_handler + #elif defined(TARGET_MIPS) #define CPUState CPUMIPSState #define cpu_init cpu_mips_init @@ -712,6 +739,13 @@ void page_unprotect_range(uint8_t *data, unsigned long data_size); #define cpu_gen_code cpu_mips_gen_code #define cpu_signal_handler cpu_mips_signal_handler +#elif defined(TARGET_SH4) +#define CPUState CPUSH4State +#define cpu_init cpu_sh4_init +#define cpu_exec cpu_sh4_exec +#define cpu_gen_code cpu_sh4_gen_code +#define cpu_signal_handler cpu_sh4_signal_handler + #else #error unsupported target CPU @@ -720,9 +754,14 @@ void page_unprotect_range(uint8_t *data, unsigned long data_size); #endif /* SINGLE_CPU_DEFINES */ +CPUState *cpu_copy(CPUState *env); + void cpu_dump_state(CPUState *env, FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...), int flags); +void cpu_dump_statistics (CPUState *env, FILE *f, + int (*cpu_fprintf)(FILE *f, const char *fmt, ...), + int flags); void cpu_abort(CPUState *env, const char *fmt, ...); extern CPUState *first_cpu; @@ -735,10 +774,14 @@ extern int code_copy_enabled; #define CPU_INTERRUPT_TIMER 0x08 /* internal timer exception pending */ #define CPU_INTERRUPT_FIQ 0x10 /* Fast interrupt pending. */ #define CPU_INTERRUPT_HALT 0x20 /* CPU halt wanted */ +#define CPU_INTERRUPT_SMI 0x40 /* (x86 only) SMI interrupt pending */ +#define CPU_INTERRUPT_DEBUG 0x80 /* Debug event occured. */ void cpu_interrupt(CPUState *s, int mask); void cpu_reset_interrupt(CPUState *env, int mask); +int cpu_watchpoint_insert(CPUState *env, target_ulong addr); +int cpu_watchpoint_remove(CPUState *env, target_ulong addr); int cpu_breakpoint_insert(CPUState *env, target_ulong pc); int cpu_breakpoint_remove(CPUState *env, target_ulong pc); void cpu_single_step(CPUState *env, int enabled); @@ -801,6 +844,10 @@ extern uint8_t *phys_ram_dirty; #define IO_MEM_ROM (1 << IO_MEM_SHIFT) /* hardcoded offset */ #define IO_MEM_UNASSIGNED (2 << IO_MEM_SHIFT) #define IO_MEM_NOTDIRTY (4 << IO_MEM_SHIFT) /* used internally, never use directly */ +/* acts like a ROM when read and like a device when written. As an + exception, the write memory callback gets the ram offset instead of + the physical address */ +#define IO_MEM_ROMD (1) typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value); typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr); @@ -808,6 +855,9 @@ typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr); void cpu_register_physical_memory(target_phys_addr_t start_addr, unsigned long size, unsigned long phys_offset); +uint32_t cpu_get_physical_page_desc(target_phys_addr_t addr); +ram_addr_t qemu_ram_alloc(unsigned int size); +void qemu_ram_free(ram_addr_t addr); int cpu_register_io_memory(int io_index, CPUReadMemoryFunc **mem_read, CPUWriteMemoryFunc **mem_write, @@ -837,6 +887,8 @@ void stw_phys(target_phys_addr_t addr, uint32_t val); void stl_phys(target_phys_addr_t addr, uint32_t val); void stq_phys(target_phys_addr_t addr, uint64_t val); +void cpu_physical_memory_write_rom(target_phys_addr_t addr, + const uint8_t *buf, int len); int cpu_memory_rw_debug(CPUState *env, target_ulong addr, uint8_t *buf, int len, int is_write); @@ -867,4 +919,125 @@ void cpu_tlb_update_dirty(CPUState *env); void dump_exec_info(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); +/*******************************************/ +/* host CPU ticks (if available) */ + +#if defined(__powerpc__) + +static inline uint32_t get_tbl(void) +{ + uint32_t tbl; + asm volatile("mftb %0" : "=r" (tbl)); + return tbl; +} + +static inline uint32_t get_tbu(void) +{ + uint32_t tbl; + asm volatile("mftbu %0" : "=r" (tbl)); + return tbl; +} + +static inline int64_t cpu_get_real_ticks(void) +{ + uint32_t l, h, h1; + /* NOTE: we test if wrapping has occurred */ + do { + h = get_tbu(); + l = get_tbl(); + h1 = get_tbu(); + } while (h != h1); + return ((int64_t)h << 32) | l; +} + +#elif defined(__i386__) + +static inline int64_t cpu_get_real_ticks(void) +{ + int64_t val; + asm volatile ("rdtsc" : "=A" (val)); + return val; +} + +#elif defined(__x86_64__) + +static inline int64_t cpu_get_real_ticks(void) +{ + uint32_t low,high; + int64_t val; + asm volatile("rdtsc" : "=a" (low), "=d" (high)); + val = high; + val <<= 32; + val |= low; + return val; +} + +#elif defined(__ia64) + +static inline int64_t cpu_get_real_ticks(void) +{ + int64_t val; + asm volatile ("mov %0 = ar.itc" : "=r"(val) :: "memory"); + return val; +} + +#elif defined(__s390__) + +static inline int64_t cpu_get_real_ticks(void) +{ + int64_t val; + asm volatile("stck 0(%1)" : "=m" (val) : "a" (&val) : "cc"); + return val; +} + +#elif defined(__sparc_v9__) + +static inline int64_t cpu_get_real_ticks (void) +{ +#if defined(_LP64) + uint64_t rval; + asm volatile("rd %%tick,%0" : "=r"(rval)); + return rval; +#else + union { + uint64_t i64; + struct { + uint32_t high; + uint32_t low; + } i32; + } rval; + asm volatile("rd %%tick,%1; srlx %1,32,%0" + : "=r"(rval.i32.high), "=r"(rval.i32.low)); + return rval.i64; +#endif +} +#else +/* The host CPU doesn't have an easily accessible cycle counter. + Just return a monotonically increasing vlue. This will be totally wrong, + but hopefully better than nothing. */ +static inline int64_t cpu_get_real_ticks (void) +{ + static int64_t ticks = 0; + return ticks++; +} +#endif + +/* profiling */ +#ifdef CONFIG_PROFILER +static inline int64_t profile_getclock(void) +{ + return cpu_get_real_ticks(); +} + +extern int64_t kqemu_time, kqemu_time_start; +extern int64_t qemu_time, qemu_time_start; +extern int64_t tlb_flush_time; +extern int64_t kqemu_exec_count; +extern int64_t dev_time; +extern int64_t kqemu_ret_int_count; +extern int64_t kqemu_ret_excp_count; +extern int64_t kqemu_ret_intr_count; + +#endif + #endif /* CPU_ALL_H */