#include <signal.h>
#include <assert.h>
-#include "disas.h"
-
-#define DEBUG_DISAS
-
-#define IN_OP_I386
#include "cpu-i386.h"
#include "exec.h"
+#include "disas.h"
/* XXX: move that elsewhere */
static uint16_t *gen_opc_ptr;
static uint32_t *gen_opparam_ptr;
-int __op_param1, __op_param2, __op_param3;
-#ifdef USE_DIRECT_JUMP
-int __op_jmp0, __op_jmp1;
-#endif
-
-#ifdef __i386__
-static inline void flush_icache_range(unsigned long start, unsigned long stop)
-{
-}
-#endif
-
-#ifdef __s390__
-static inline void flush_icache_range(unsigned long start, unsigned long stop)
-{
-}
-#endif
-
-#ifdef __ia64__
-static inline void flush_icache_range(unsigned long start, unsigned long stop)
-{
-}
-#endif
-
-#ifdef __powerpc__
-
-#define MIN_CACHE_LINE_SIZE 8 /* conservative value */
-
-static void inline flush_icache_range(unsigned long start, unsigned long stop)
-{
- unsigned long p;
-
- p = start & ~(MIN_CACHE_LINE_SIZE - 1);
- stop = (stop + MIN_CACHE_LINE_SIZE - 1) & ~(MIN_CACHE_LINE_SIZE - 1);
-
- for (p = start; p < stop; p += MIN_CACHE_LINE_SIZE) {
- asm volatile ("dcbst 0,%0" : : "r"(p) : "memory");
- }
- asm volatile ("sync" : : : "memory");
- for (p = start; p < stop; p += MIN_CACHE_LINE_SIZE) {
- asm volatile ("icbi 0,%0" : : "r"(p) : "memory");
- }
- asm volatile ("sync" : : : "memory");
- asm volatile ("isync" : : : "memory");
-}
-#endif
-
-#ifdef __alpha__
-static inline void flush_icache_range(unsigned long start, unsigned long stop)
-{
- asm ("imb");
-}
-#endif
-
-#ifdef __sparc__
-
-static void inline flush_icache_range(unsigned long start, unsigned long stop)
-{
- unsigned long p;
-
- p = start & ~(8UL - 1UL);
- stop = (stop + (8UL - 1UL)) & ~(8UL - 1UL);
-
- for (; p < stop; p += 8)
- __asm__ __volatile__("flush\t%0" : : "r" (p));
-}
-
-#endif
-
-#ifdef __arm__
-static inline void flush_icache_range(unsigned long start, unsigned long stop)
-{
- register unsigned long _beg __asm ("a1") = start;
- register unsigned long _end __asm ("a2") = stop;
- register unsigned long _flg __asm ("a3") = 0;
- __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
-}
-#endif
-
-extern FILE *logfile;
-extern int loglevel;
#define PREFIX_REPZ 0x01
#define PREFIX_REPNZ 0x02
int cpl;
int iopl;
int tf; /* TF cpu flag */
- TranslationBlock *tb;
+ struct TranslationBlock *tb;
} DisasContext;
/* i386 arith/logic operations */
NB_OPS,
};
-#include "dyngen.h"
-#include "op-i386.h"
+#include "gen-op-i386.h"
/* operand size */
enum {
if (s->addseg && override < 0)
override = R_DS;
if (override >= 0) {
- gen_op_movl_A0_seg(offsetof(CPUX86State,seg_cache[override].base));
+ gen_op_movl_A0_seg(offsetof(CPUX86State,segs[override].base));
index = 3 + ot;
} else {
index = ot;
} else {
if (override < 0)
override = R_DS;
- gen_op_movl_A0_seg(offsetof(CPUX86State,seg_cache[override].base));
+ gen_op_movl_A0_seg(offsetof(CPUX86State,segs[override].base));
/* 16 address, always override */
index = 6 + ot;
}
else
override = R_DS;
}
- gen_op_addl_A0_seg(offsetof(CPUX86State,seg_cache[override].base));
+ gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
}
} else {
switch (mod) {
else
override = R_DS;
}
- gen_op_addl_A0_seg(offsetof(CPUX86State,seg_cache[override].base));
+ gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
}
}
if (!s->vm86)
gen_op_movl_seg_T0(seg_reg, cur_eip);
else
- gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[seg_reg]),
- offsetof(CPUX86State,seg_cache[seg_reg].base));
+ gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[seg_reg]));
if (!s->addseg && seg_reg < R_FS)
s->is_jmp = 2; /* abort translation because the register may
have a non zero base */
gen_op_andl_A0_ffff();
gen_op_movl_T1_A0();
if (s->addseg)
- gen_op_addl_A0_seg(offsetof(CPUX86State,seg_cache[R_SS].base));
+ gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
}
/* NOTE: wrap around in 16 bit not fully handled */
gen_op_andl_A0_ffff();
gen_op_movl_T1_A0();
if (s->addseg)
- gen_op_addl_A0_seg(offsetof(CPUX86State,seg_cache[R_SS].base));
+ gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
for(i = 0;i < 8; i++) {
gen_op_mov_TN_reg[OT_LONG][0][7 - i]();
gen_op_st_T0_A0[OT_WORD + s->dflag]();
gen_op_movl_T1_A0();
gen_op_addl_T1_im(16 << s->dflag);
if (s->addseg)
- gen_op_addl_A0_seg(offsetof(CPUX86State,seg_cache[R_SS].base));
+ gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
for(i = 0;i < 8; i++) {
/* ESP is not reloaded */
if (i != 3) {
gen_op_andl_A0_ffff();
gen_op_movl_T1_A0();
if (s->addseg)
- gen_op_addl_A0_seg(offsetof(CPUX86State,seg_cache[R_SS].base));
+ gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
/* push bp */
gen_op_mov_TN_reg[OT_LONG][0][R_EBP]();
gen_op_st_T0_A0[ot]();
gen_op_ld_T1_A0[ot]();
gen_op_addl_A0_im(1 << (ot - OT_WORD + 1));
gen_op_lduw_T0_A0();
- gen_movl_seg_T0(s, R_CS, pc_start - s->cs_base);
- gen_op_movl_T0_T1();
- gen_op_jmp_T0();
+ if (!s->vm86) {
+ /* we compute EIP to handle the exception case */
+ gen_op_jmp_im(pc_start - s->cs_base);
+ gen_op_ljmp_T0_T1();
+ } else {
+ gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[R_CS]));
+ gen_op_movl_T0_T1();
+ gen_op_jmp_T0();
+ }
s->is_jmp = 1;
break;
case 6: /* push Ev */
override = R_DS;
}
if (must_add_seg) {
- gen_op_addl_A0_seg(offsetof(CPUX86State,seg_cache[override].base));
+ gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
}
}
if ((b & 2) == 0) {
override = R_DS;
}
if (must_add_seg) {
- gen_op_addl_A0_seg(offsetof(CPUX86State,seg_cache[override].base));
+ gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
}
}
gen_op_ldub_T0_A0();
break;
case 0x1c:
switch(rm) {
+ case 0: /* feni (287 only, just do nop here) */
+ break;
+ case 1: /* fdisi (287 only, just do nop here) */
+ break;
case 2: /* fclex */
gen_op_fclex();
break;
case 3: /* fninit */
gen_op_fninit();
break;
+ case 4: /* fsetpm (287 only, just do nop here) */
+ break;
default:
goto illegal_op;
}
/* change cs and pc */
gen_op_movl_T0_im(selector);
- gen_movl_seg_T0(s, R_CS, pc_start - s->cs_base);
- gen_op_jmp_im((unsigned long)offset);
+ if (!s->vm86) {
+ /* we compute EIP to handle the exception case */
+ gen_op_jmp_im(pc_start - s->cs_base);
+ gen_op_movl_T1_im(offset);
+ gen_op_ljmp_T0_T1();
+ } else {
+ gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[R_CS]));
+ gen_op_jmp_im((unsigned long)offset);
+ }
s->is_jmp = 1;
}
break;
/* XXX: if cpl == 0, then should do something else */
gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
break;
+ case 0x100:
+ modrm = ldub(s->pc++);
+ mod = (modrm >> 6) & 3;
+ op = (modrm >> 3) & 7;
+ switch(op) {
+ case 0: /* sldt */
+ gen_op_movl_T0_env(offsetof(CPUX86State,ldt.selector));
+ ot = OT_WORD;
+ if (mod == 3)
+ ot += s->dflag;
+ gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
+ break;
+ case 2: /* lldt */
+ if (s->cpl != 0) {
+ gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
+ } else {
+ gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
+ gen_op_jmp_im(pc_start - s->cs_base);
+ gen_op_lldt_T0();
+ }
+ break;
+ case 1: /* str */
+ gen_op_movl_T0_env(offsetof(CPUX86State,tr.selector));
+ ot = OT_WORD;
+ if (mod == 3)
+ ot += s->dflag;
+ gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
+ break;
+ case 3: /* ltr */
+ if (s->cpl != 0) {
+ gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
+ } else {
+ gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
+ gen_op_jmp_im(pc_start - s->cs_base);
+ gen_op_ltr_T0();
+ }
+ break;
+ case 4: /* verr */
+ case 5: /* verw */
+ default:
+ goto illegal_op;
+ }
+ break;
+ case 0x101:
+ modrm = ldub(s->pc++);
+ mod = (modrm >> 6) & 3;
+ op = (modrm >> 3) & 7;
+ switch(op) {
+ case 0: /* sgdt */
+ case 1: /* sidt */
+ if (mod == 3)
+ goto illegal_op;
+ gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+ if (op == 0)
+ gen_op_movl_T0_env(offsetof(CPUX86State,gdt.limit));
+ else
+ gen_op_movl_T0_env(offsetof(CPUX86State,idt.limit));
+ gen_op_stw_T0_A0();
+ gen_op_addl_A0_im(2);
+ if (op == 0)
+ gen_op_movl_T0_env(offsetof(CPUX86State,gdt.base));
+ else
+ gen_op_movl_T0_env(offsetof(CPUX86State,idt.base));
+ if (!s->dflag)
+ gen_op_andl_T0_im(0xffffff);
+ gen_op_stl_T0_A0();
+ break;
+ case 2: /* lgdt */
+ case 3: /* lidt */
+ if (mod == 3)
+ goto illegal_op;
+ if (s->cpl != 0) {
+ gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
+ } else {
+ gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+ gen_op_lduw_T1_A0();
+ gen_op_addl_A0_im(2);
+ gen_op_ldl_T0_A0();
+ if (!s->dflag)
+ gen_op_andl_T0_im(0xffffff);
+ if (op == 2) {
+ gen_op_movl_env_T0(offsetof(CPUX86State,gdt.base));
+ gen_op_movl_env_T1(offsetof(CPUX86State,gdt.limit));
+ } else {
+ gen_op_movl_env_T0(offsetof(CPUX86State,idt.base));
+ gen_op_movl_env_T1(offsetof(CPUX86State,idt.limit));
+ }
+ }
+ break;
+ case 4: /* smsw */
+ gen_op_movl_T0_env(offsetof(CPUX86State,cr[0]));
+ gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 1);
+ break;
+ case 6: /* lmsw */
+ if (s->cpl != 0) {
+ gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
+ } else {
+ gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
+ gen_op_lmsw_T0();
+ }
+ break;
+ default:
+ goto illegal_op;
+ }
+ break;
case 0x102: /* lar */
case 0x103: /* lsl */
if (s->vm86)
s->cc_op = CC_OP_EFLAGS;
gen_op_mov_reg_T1[ot][reg]();
break;
+ case 0x118:
+ modrm = ldub(s->pc++);
+ mod = (modrm >> 6) & 3;
+ op = (modrm >> 3) & 7;
+ switch(op) {
+ case 0: /* prefetchnta */
+ case 1: /* prefetchnt0 */
+ case 2: /* prefetchnt0 */
+ case 3: /* prefetchnt0 */
+ if (mod == 3)
+ goto illegal_op;
+ gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+ /* nothing more to do */
+ break;
+ default:
+ goto illegal_op;
+ }
+ break;
+ case 0x120: /* mov reg, crN */
+ case 0x122: /* mov crN, reg */
+ if (s->cpl != 0) {
+ gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
+ } else {
+ modrm = ldub(s->pc++);
+ if ((modrm & 0xc0) != 0xc0)
+ goto illegal_op;
+ rm = modrm & 7;
+ reg = (modrm >> 3) & 7;
+ switch(reg) {
+ case 0:
+ case 2:
+ case 3:
+ case 4:
+ if (b & 2) {
+ gen_op_mov_TN_reg[OT_LONG][0][rm]();
+ gen_op_movl_crN_T0(reg);
+ s->is_jmp = 2;
+ } else {
+ gen_op_movl_T0_env(offsetof(CPUX86State,cr[reg]));
+ gen_op_mov_reg_T0[OT_LONG][rm]();
+ }
+ break;
+ default:
+ goto illegal_op;
+ }
+ }
+ break;
+ case 0x121: /* mov reg, drN */
+ case 0x123: /* mov drN, reg */
+ if (s->cpl != 0) {
+ gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
+ } else {
+ modrm = ldub(s->pc++);
+ if ((modrm & 0xc0) != 0xc0)
+ goto illegal_op;
+ rm = modrm & 7;
+ reg = (modrm >> 3) & 7;
+ /* XXX: do it dynamically with CR4.DE bit */
+ if (reg == 4 || reg == 5)
+ goto illegal_op;
+ if (b & 2) {
+ gen_op_mov_TN_reg[OT_LONG][0][rm]();
+ gen_op_movl_drN_T0(reg);
+ s->is_jmp = 2;
+ } else {
+ gen_op_movl_T0_env(offsetof(CPUX86State,dr[reg]));
+ gen_op_mov_reg_T0[OT_LONG][rm]();
+ }
+ }
+ break;
+ case 0x106: /* clts */
+ if (s->cpl != 0) {
+ gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
+ } else {
+ gen_op_clts();
+ }
+ break;
default:
goto illegal_op;
}
}
}
-
-#ifdef DEBUG_DISAS
-static const char *op_str[] = {
-#define DEF(s, n, copy_size) #s,
-#include "opc-i386.h"
-#undef DEF
-};
-
-static uint8_t op_nb_args[] = {
-#define DEF(s, n, copy_size) n,
-#include "opc-i386.h"
-#undef DEF
-};
-
-static void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf)
-{
- const uint16_t *opc_ptr;
- const uint32_t *opparam_ptr;
- int c, n, i;
-
- opc_ptr = opc_buf;
- opparam_ptr = opparam_buf;
- for(;;) {
- c = *opc_ptr++;
- n = op_nb_args[c];
- fprintf(logfile, "0x%04x: %s",
- (int)(opc_ptr - opc_buf - 1), op_str[c]);
- for(i = 0; i < n; i++) {
- fprintf(logfile, " 0x%x", opparam_ptr[i]);
- }
- fprintf(logfile, "\n");
- if (c == INDEX_op_end)
- break;
- opparam_ptr += n;
- }
-}
-
-#endif
-
-/* XXX: make safe guess about sizes */
-#define MAX_OP_PER_INSTR 32
-#define OPC_BUF_SIZE 512
-#define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
-
-#define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3)
-
-static uint16_t gen_opc_buf[OPC_BUF_SIZE];
-static uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
-static uint32_t gen_opc_pc[OPC_BUF_SIZE];
-static uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
-
/* generate intermediate code in gen_opc_buf and gen_opparam_buf for
basic block 'tb'. If search_pc is TRUE, also generate PC
information for each intermediate instruction. */
-static inline int gen_intermediate_code(TranslationBlock *tb, int search_pc)
+int gen_intermediate_code(TranslationBlock *tb, int search_pc)
{
DisasContext dc1, *dc = &dc1;
uint8_t *pc_ptr;
gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
gen_opparam_ptr = gen_opparam_buf;
- dc->is_jmp = 0;
+ dc->is_jmp = DISAS_NEXT;
pc_ptr = pc_start;
lj = -1;
do {
} while (!dc->is_jmp && gen_opc_ptr < gen_opc_end &&
(pc_ptr - pc_start) < (TARGET_PAGE_SIZE - 32));
/* we must store the eflags state if it is not already done */
- if (dc->is_jmp != 3) {
+ if (dc->is_jmp != DISAS_TB_JUMP) {
if (dc->cc_op != CC_OP_DYNAMIC)
gen_op_set_cc_op(dc->cc_op);
- if (dc->is_jmp != 1) {
+ if (dc->is_jmp != DISAS_JUMP) {
/* we add an additionnal jmp to update the simulated PC */
gen_op_jmp_im(ret - (unsigned long)dc->cs_base);
}
/* indicate that the hash table must be used to find the next TB */
gen_op_movl_T0_0();
}
-
*gen_opc_ptr = INDEX_op_end;
#ifdef DEBUG_DISAS
if (loglevel) {
fprintf(logfile, "----------------\n");
fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
- disas(logfile, pc_start, pc_ptr - pc_start,
- dc->code32 ? DISAS_I386_I386 : DISAS_I386_I8086);
+ disas(logfile, pc_start, pc_ptr - pc_start, 0, !dc->code32);
fprintf(logfile, "\n");
fprintf(logfile, "OP:\n");
return 0;
}
-
-/* return non zero if the very first instruction is invalid so that
- the virtual CPU can trigger an exception.
-
- '*gen_code_size_ptr' contains the size of the generated code (host
- code).
-*/
-int cpu_x86_gen_code(TranslationBlock *tb,
- int max_code_size, int *gen_code_size_ptr)
-{
- uint8_t *gen_code_buf;
- int gen_code_size;
-
- if (gen_intermediate_code(tb, 0) < 0)
- return -1;
-
- /* generate machine code */
- tb->tb_next_offset[0] = 0xffff;
- tb->tb_next_offset[1] = 0xffff;
- gen_code_buf = tb->tc_ptr;
- gen_code_size = dyngen_code(gen_code_buf, tb->tb_next_offset,
-#ifdef USE_DIRECT_JUMP
- tb->tb_jmp_offset,
-#else
- NULL,
-#endif
- gen_opc_buf, gen_opparam_buf);
- flush_icache_range((unsigned long)gen_code_buf, (unsigned long)(gen_code_buf + gen_code_size));
-
- *gen_code_size_ptr = gen_code_size;
-#ifdef DEBUG_DISAS
- if (loglevel) {
- fprintf(logfile, "OUT: [size=%d]\n", *gen_code_size_ptr);
- disas(logfile, gen_code_buf, *gen_code_size_ptr, DISAS_TARGET);
- fprintf(logfile, "\n");
- fflush(logfile);
- }
-#endif
- return 0;
-}
-
-static const unsigned short opc_copy_size[] = {
-#define DEF(s, n, copy_size) copy_size,
-#include "opc-i386.h"
-#undef DEF
-};
-
-/* The simulated PC corresponding to
- 'searched_pc' in the generated code is searched. 0 is returned if
- found. *found_pc contains the found PC.
- */
-int cpu_x86_search_pc(TranslationBlock *tb,
- uint32_t *found_pc, unsigned long searched_pc)
-{
- int j, c;
- unsigned long tc_ptr;
- uint16_t *opc_ptr;
-
- if (gen_intermediate_code(tb, 1) < 0)
- return -1;
-
- /* find opc index corresponding to search_pc */
- tc_ptr = (unsigned long)tb->tc_ptr;
- if (searched_pc < tc_ptr)
- return -1;
- j = 0;
- opc_ptr = gen_opc_buf;
- for(;;) {
- c = *opc_ptr;
- if (c == INDEX_op_end)
- return -1;
- tc_ptr += opc_copy_size[c];
- if (searched_pc < tc_ptr)
- break;
- opc_ptr++;
- }
- j = opc_ptr - gen_opc_buf;
- /* now find start of instruction before */
- while (gen_opc_instr_start[j] == 0)
- j--;
- *found_pc = gen_opc_pc[j];
- return 0;
-}
-
-
CPUX86State *cpu_x86_init(void)
{
CPUX86State *env;
int i;
static int inited;
- cpu_x86_tblocks_init();
+ cpu_exec_init();
env = malloc(sizeof(CPUX86State));
if (!env)
if (!inited) {
inited = 1;
optimize_flags_init();
- page_init();
}
return env;
}
eflags & CC_P ? 'P' : '-',
eflags & CC_C ? 'C' : '-');
fprintf(f, "CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x\n",
- env->segs[R_CS],
- env->segs[R_SS],
- env->segs[R_DS],
- env->segs[R_ES],
- env->segs[R_FS],
- env->segs[R_GS]);
+ env->segs[R_CS].selector,
+ env->segs[R_SS].selector,
+ env->segs[R_DS].selector,
+ env->segs[R_ES].selector,
+ env->segs[R_FS].selector,
+ env->segs[R_GS].selector);
if (flags & X86_DUMP_CCOP) {
if ((unsigned)env->cc_op < CC_OP_NB)
strcpy(cc_op_name, cc_op_str[env->cc_op]);