#define IN_OP_I386
#include "cpu-i386.h"
-
-#ifndef offsetof
-#define offsetof(type, field) ((size_t) &((type *)0)->field)
-#endif
+#include "exec.h"
/* XXX: move that elsewhere */
static uint16_t *gen_opc_ptr;
static uint32_t *gen_opparam_ptr;
int __op_param1, __op_param2, __op_param3;
+#ifdef USE_DIRECT_JUMP
+int __op_jmp0, __op_jmp1;
+#endif
#ifdef __i386__
static inline void flush_icache_range(unsigned long start, unsigned long stop)
}
#endif
+#ifdef __ia64__
+static inline void flush_icache_range(unsigned long start, unsigned long stop)
+{
+}
+#endif
+
#ifdef __powerpc__
#define MIN_CACHE_LINE_SIZE 8 /* conservative value */
stop = (stop + MIN_CACHE_LINE_SIZE - 1) & ~(MIN_CACHE_LINE_SIZE - 1);
for (p = start; p < stop; p += MIN_CACHE_LINE_SIZE) {
- asm ("dcbst 0,%0;" : : "r"(p) : "memory");
+ asm volatile ("dcbst 0,%0" : : "r"(p) : "memory");
}
- asm ("sync");
+ asm volatile ("sync" : : : "memory");
for (p = start; p < stop; p += MIN_CACHE_LINE_SIZE) {
- asm ("icbi 0,%0; sync;" : : "r"(p) : "memory");
+ asm volatile ("icbi 0,%0" : : "r"(p) : "memory");
}
- asm ("sync");
- asm ("isync");
+ asm volatile ("sync" : : : "memory");
+ asm volatile ("isync" : : : "memory");
+}
+#endif
+
+#ifdef __alpha__
+static inline void flush_icache_range(unsigned long start, unsigned long stop)
+{
+ asm ("imb");
+}
+#endif
+
+#ifdef __sparc__
+
+static void inline flush_icache_range(unsigned long start, unsigned long stop)
+{
+ unsigned long p;
+
+ p = start & ~(8UL - 1UL);
+ stop = (stop + (8UL - 1UL)) & ~(8UL - 1UL);
+
+ for (; p < stop; p += 8)
+ __asm__ __volatile__("flush\t%0" : : "r" (p));
+}
+
+#endif
+
+#ifdef __arm__
+static inline void flush_icache_range(unsigned long start, unsigned long stop)
+{
+ register unsigned long _beg __asm ("a1") = start;
+ register unsigned long _end __asm ("a2") = stop;
+ register unsigned long _flg __asm ("a3") = 0;
+ __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
}
#endif
#define PREFIX_LOCK 0x04
#define PREFIX_DATA 0x08
#define PREFIX_ADR 0x10
-#define PREFIX_FWAIT 0x20
typedef struct DisasContext {
/* current insn context */
int addseg; /* non zero if either DS/ES/SS have a non zero base */
int f_st; /* currently unused */
int vm86; /* vm86 mode */
+ int cpl;
+ int iopl;
+ int tf; /* TF cpu flag */
+ TranslationBlock *tb;
} DisasContext;
/* i386 arith/logic operations */
};
enum {
-#define DEF(s, n) INDEX_op_ ## s,
+#define DEF(s, n, copy_size) INDEX_op_ ## s,
#include "opc-i386.h"
#undef DEF
NB_OPS,
};
+#include "dyngen.h"
#include "op-i386.h"
/* operand size */
typedef void (GenOpFunc)(void);
typedef void (GenOpFunc1)(long);
typedef void (GenOpFunc2)(long, long);
+typedef void (GenOpFunc3)(long, long, long);
static GenOpFunc *gen_op_mov_reg_T0[3][8] = {
[OT_BYTE] = {
JCC_LE,
};
-static GenOpFunc2 *gen_jcc_slow[8] = {
- gen_op_jo_cc,
- gen_op_jb_cc,
- gen_op_jz_cc,
- gen_op_jbe_cc,
- gen_op_js_cc,
- gen_op_jp_cc,
- gen_op_jl_cc,
- gen_op_jle_cc,
-};
-
-static GenOpFunc2 *gen_jcc_sub[3][8] = {
+static GenOpFunc3 *gen_jcc_sub[3][8] = {
[OT_BYTE] = {
NULL,
gen_op_jb_subb,
static inline void gen_jcc(DisasContext *s, int b, int val, int next_eip)
{
+ TranslationBlock *tb;
int inv, jcc_op;
- GenOpFunc2 *func;
+ GenOpFunc3 *func;
inv = b & 1;
jcc_op = (b >> 1) & 7;
case CC_OP_SUBW:
case CC_OP_SUBL:
func = gen_jcc_sub[s->cc_op - CC_OP_SUBB][jcc_op];
- if (!func)
- goto slow_jcc;
break;
/* some jumps are easy to compute */
func = gen_jcc_sub[(s->cc_op - CC_OP_ADDB) % 3][jcc_op];
break;
default:
- goto slow_jcc;
+ func = NULL;
+ break;
}
break;
default:
- slow_jcc:
- if (s->cc_op != CC_OP_DYNAMIC)
- gen_op_set_cc_op(s->cc_op);
- func = gen_jcc_slow[jcc_op];
+ func = NULL;
break;
}
+
+ if (s->cc_op != CC_OP_DYNAMIC)
+ gen_op_set_cc_op(s->cc_op);
+
+ if (!func) {
+ gen_setcc_slow[jcc_op]();
+ func = gen_op_jcc;
+ }
+
+ tb = s->tb;
if (!inv) {
- func(val, next_eip);
+ func((long)tb, val, next_eip);
} else {
- func(next_eip, val);
+ func((long)tb, next_eip, val);
}
+ s->is_jmp = 3;
}
static void gen_setcc(DisasContext *s, int b)
}
/* move T0 to seg_reg and compute if the CPU state may change */
-static void gen_movl_seg_T0(DisasContext *s, int seg_reg)
+static void gen_movl_seg_T0(DisasContext *s, int seg_reg, unsigned int cur_eip)
{
- gen_op_movl_seg_T0(seg_reg);
+ if (!s->vm86)
+ gen_op_movl_seg_T0(seg_reg, cur_eip);
+ else
+ gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[seg_reg]),
+ offsetof(CPUX86State,seg_cache[seg_reg].base));
if (!s->addseg && seg_reg < R_FS)
s->is_jmp = 2; /* abort translation because the register may
have a non zero base */
}
}
-static void gen_pop_update(DisasContext *s)
+static inline void gen_stack_update(DisasContext *s, int addend)
{
if (s->ss32) {
- if (s->dflag)
- gen_op_addl_ESP_4();
- else
+ if (addend == 2)
gen_op_addl_ESP_2();
+ else if (addend == 4)
+ gen_op_addl_ESP_4();
+ else
+ gen_op_addl_ESP_im(addend);
} else {
- if (s->dflag)
+ if (addend == 2)
+ gen_op_addw_ESP_2();
+ else if (addend == 4)
gen_op_addw_ESP_4();
else
- gen_op_addw_ESP_2();
+ gen_op_addw_ESP_im(addend);
}
}
+static void gen_pop_update(DisasContext *s)
+{
+ gen_stack_update(s, 2 << s->dflag);
+}
+
+static void gen_stack_A0(DisasContext *s)
+{
+ gen_op_movl_A0_ESP();
+ if (!s->ss32)
+ gen_op_andl_A0_ffff();
+ gen_op_movl_T1_A0();
+ if (s->addseg)
+ gen_op_addl_A0_seg(offsetof(CPUX86State,seg_cache[R_SS].base));
+}
+
/* NOTE: wrap around in 16 bit not fully handled */
static void gen_pusha(DisasContext *s)
{
gen_op_mov_reg_T1[ot][R_ESP]();
}
+static void gen_exception(DisasContext *s, int trapno, unsigned int cur_eip)
+{
+ if (s->cc_op != CC_OP_DYNAMIC)
+ gen_op_set_cc_op(s->cc_op);
+ gen_op_jmp_im(cur_eip);
+ gen_op_raise_exception(trapno);
+ s->is_jmp = 1;
+}
+
+/* an interrupt is different from an exception because of the
+ priviledge checks */
+static void gen_interrupt(DisasContext *s, int intno,
+ unsigned int cur_eip, unsigned int next_eip)
+{
+ if (s->cc_op != CC_OP_DYNAMIC)
+ gen_op_set_cc_op(s->cc_op);
+ gen_op_jmp_im(cur_eip);
+ gen_op_raise_interrupt(intno, next_eip);
+ s->is_jmp = 1;
+}
+
+/* generate a jump to eip. No segment change must happen before as a
+ direct call to the next block may occur */
+static void gen_jmp(DisasContext *s, unsigned int eip)
+{
+ TranslationBlock *tb = s->tb;
+
+ if (s->cc_op != CC_OP_DYNAMIC)
+ gen_op_set_cc_op(s->cc_op);
+ gen_op_jmp_tb_next((long)tb, eip);
+ s->is_jmp = 3;
+}
+
/* return the next pc address. Return -1 if no insn found. *is_jmp_ptr
is set to true if the instruction sets the PC (last instruction of
a basic block) */
case 0x67:
prefixes |= PREFIX_ADR;
goto next_byte;
- case 0x9b:
- prefixes |= PREFIX_FWAIT;
- goto next_byte;
}
if (prefixes & PREFIX_DATA)
case 6: /* div */
switch(ot) {
case OT_BYTE:
- gen_op_divb_AL_T0();
+ gen_op_divb_AL_T0(pc_start - s->cs_base);
break;
case OT_WORD:
- gen_op_divw_AX_T0();
+ gen_op_divw_AX_T0(pc_start - s->cs_base);
break;
default:
case OT_LONG:
- gen_op_divl_EAX_T0();
+ gen_op_divl_EAX_T0(pc_start - s->cs_base);
break;
}
break;
case 7: /* idiv */
switch(ot) {
case OT_BYTE:
- gen_op_idivb_AL_T0();
+ gen_op_idivb_AL_T0(pc_start - s->cs_base);
break;
case OT_WORD:
- gen_op_idivw_AX_T0();
+ gen_op_idivw_AX_T0(pc_start - s->cs_base);
break;
default:
case OT_LONG:
- gen_op_idivl_EAX_T0();
+ gen_op_idivl_EAX_T0(pc_start - s->cs_base);
break;
}
break;
gen_op_ld_T1_A0[ot]();
gen_op_addl_A0_im(1 << (ot - OT_WORD + 1));
gen_op_lduw_T0_A0();
- gen_movl_seg_T0(s, R_CS);
+ gen_movl_seg_T0(s, R_CS, pc_start - s->cs_base);
gen_op_movl_T0_T1();
gen_op_jmp_T0();
s->is_jmp = 1;
gen_op_ld_T1_A0[ot]();
gen_op_addl_A0_im(1 << (ot - OT_WORD + 1));
gen_op_lduw_T0_A0();
- gen_movl_seg_T0(s, R_CS);
+ gen_movl_seg_T0(s, R_CS, pc_start - s->cs_base);
gen_op_movl_T0_T1();
gen_op_jmp_T0();
s->is_jmp = 1;
}
break;
case 0xc9: /* leave */
- /* XXX: exception not precise (ESP is update before potential exception) */
+ /* XXX: exception not precise (ESP is updated before potential exception) */
if (s->ss32) {
gen_op_mov_TN_reg[OT_LONG][0][R_EBP]();
gen_op_mov_reg_T0[OT_LONG][R_ESP]();
case 0x17: /* pop ss */
case 0x1f: /* pop ds */
gen_pop_T0(s);
- gen_movl_seg_T0(s, b >> 3);
+ gen_movl_seg_T0(s, b >> 3, pc_start - s->cs_base);
gen_pop_update(s);
break;
case 0x1a1: /* pop fs */
case 0x1a9: /* pop gs */
gen_pop_T0(s);
- gen_movl_seg_T0(s, (b >> 3) & 7);
+ gen_movl_seg_T0(s, (b >> 3) & 7, pc_start - s->cs_base);
gen_pop_update(s);
break;
gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
if (reg >= 6 || reg == R_CS)
goto illegal_op;
- gen_movl_seg_T0(s, reg);
+ gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
break;
case 0x8c: /* mov Gv, seg */
ot = dflag ? OT_LONG : OT_WORD;
gen_op_addl_A0_im(1 << (ot - OT_WORD + 1));
/* load the segment first to handle exceptions properly */
gen_op_lduw_T0_A0();
- gen_movl_seg_T0(s, op);
+ gen_movl_seg_T0(s, op, pc_start - s->cs_base);
/* then put the data */
gen_op_mov_reg_T1[ot][reg]();
break;
break;
}
break;
+ case 0x0c: /* fldenv mem */
+ gen_op_fldenv_A0(s->dflag);
+ break;
case 0x0d: /* fldcw mem */
gen_op_fldcw_A0();
break;
+ case 0x0e: /* fnstenv mem */
+ gen_op_fnstenv_A0(s->dflag);
+ break;
case 0x0f: /* fnstcw mem */
gen_op_fnstcw_A0();
break;
gen_op_fstt_ST0_A0();
gen_op_fpop();
break;
+ case 0x2c: /* frstor mem */
+ gen_op_frstor_A0(s->dflag);
+ break;
+ case 0x2e: /* fnsave mem */
+ gen_op_fnsave_A0(s->dflag);
+ break;
case 0x2f: /* fnstsw mem */
gen_op_fnstsw_A0();
break;
goto illegal_op;
}
break;
+ case 0x1d: /* fucomi */
+ if (s->cc_op != CC_OP_DYNAMIC)
+ gen_op_set_cc_op(s->cc_op);
+ gen_op_fmov_FT0_STN(opreg);
+ gen_op_fucomi_ST0_FT0();
+ s->cc_op = CC_OP_EFLAGS;
+ break;
+ case 0x1e: /* fcomi */
+ if (s->cc_op != CC_OP_DYNAMIC)
+ gen_op_set_cc_op(s->cc_op);
+ gen_op_fmov_FT0_STN(opreg);
+ gen_op_fcomi_ST0_FT0();
+ s->cc_op = CC_OP_EFLAGS;
+ break;
case 0x2a: /* fst sti */
gen_op_fmov_STN_ST0(opreg);
break;
goto illegal_op;
}
break;
+ case 0x3d: /* fucomip */
+ if (s->cc_op != CC_OP_DYNAMIC)
+ gen_op_set_cc_op(s->cc_op);
+ gen_op_fmov_FT0_STN(opreg);
+ gen_op_fucomi_ST0_FT0();
+ gen_op_fpop();
+ s->cc_op = CC_OP_EFLAGS;
+ break;
+ case 0x3e: /* fcomip */
+ if (s->cc_op != CC_OP_DYNAMIC)
+ gen_op_set_cc_op(s->cc_op);
+ gen_op_fmov_FT0_STN(opreg);
+ gen_op_fcomi_ST0_FT0();
+ gen_op_fpop();
+ s->cc_op = CC_OP_EFLAGS;
+ break;
default:
goto illegal_op;
}
break;
case 0x6c: /* insS */
case 0x6d:
- if ((b & 1) == 0)
- ot = OT_BYTE;
- else
- ot = dflag ? OT_LONG : OT_WORD;
- if (prefixes & PREFIX_REPZ) {
- gen_string_es(s, ot, gen_op_ins + 9);
+ if (s->cpl > s->iopl || s->vm86) {
+ /* NOTE: even for (E)CX = 0 the exception is raised */
+ gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
} else {
- gen_string_es(s, ot, gen_op_ins);
+ if ((b & 1) == 0)
+ ot = OT_BYTE;
+ else
+ ot = dflag ? OT_LONG : OT_WORD;
+ if (prefixes & PREFIX_REPZ) {
+ gen_string_es(s, ot, gen_op_ins + 9);
+ } else {
+ gen_string_es(s, ot, gen_op_ins);
+ }
}
break;
case 0x6e: /* outsS */
case 0x6f:
- if ((b & 1) == 0)
- ot = OT_BYTE;
- else
- ot = dflag ? OT_LONG : OT_WORD;
- if (prefixes & PREFIX_REPZ) {
- gen_string_ds(s, ot, gen_op_outs + 9);
+ if (s->cpl > s->iopl || s->vm86) {
+ /* NOTE: even for (E)CX = 0 the exception is raised */
+ gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
} else {
- gen_string_ds(s, ot, gen_op_outs);
+ if ((b & 1) == 0)
+ ot = OT_BYTE;
+ else
+ ot = dflag ? OT_LONG : OT_WORD;
+ if (prefixes & PREFIX_REPZ) {
+ gen_string_ds(s, ot, gen_op_outs + 9);
+ } else {
+ gen_string_ds(s, ot, gen_op_outs);
+ }
}
break;
/* port I/O */
case 0xe4:
case 0xe5:
- if ((b & 1) == 0)
- ot = OT_BYTE;
- else
- ot = dflag ? OT_LONG : OT_WORD;
- val = ldub(s->pc++);
- gen_op_movl_T0_im(val);
- gen_op_in[ot]();
- gen_op_mov_reg_T1[ot][R_EAX]();
+ if (s->cpl > s->iopl || s->vm86) {
+ gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
+ } else {
+ if ((b & 1) == 0)
+ ot = OT_BYTE;
+ else
+ ot = dflag ? OT_LONG : OT_WORD;
+ val = ldub(s->pc++);
+ gen_op_movl_T0_im(val);
+ gen_op_in[ot]();
+ gen_op_mov_reg_T1[ot][R_EAX]();
+ }
break;
case 0xe6:
case 0xe7:
- if ((b & 1) == 0)
- ot = OT_BYTE;
- else
- ot = dflag ? OT_LONG : OT_WORD;
- val = ldub(s->pc++);
- gen_op_movl_T0_im(val);
- gen_op_mov_TN_reg[ot][1][R_EAX]();
- gen_op_out[ot]();
+ if (s->cpl > s->iopl || s->vm86) {
+ gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
+ } else {
+ if ((b & 1) == 0)
+ ot = OT_BYTE;
+ else
+ ot = dflag ? OT_LONG : OT_WORD;
+ val = ldub(s->pc++);
+ gen_op_movl_T0_im(val);
+ gen_op_mov_TN_reg[ot][1][R_EAX]();
+ gen_op_out[ot]();
+ }
break;
case 0xec:
case 0xed:
- if ((b & 1) == 0)
- ot = OT_BYTE;
- else
- ot = dflag ? OT_LONG : OT_WORD;
- gen_op_mov_TN_reg[OT_WORD][0][R_EDX]();
- gen_op_in[ot]();
- gen_op_mov_reg_T1[ot][R_EAX]();
+ if (s->cpl > s->iopl || s->vm86) {
+ gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
+ } else {
+ if ((b & 1) == 0)
+ ot = OT_BYTE;
+ else
+ ot = dflag ? OT_LONG : OT_WORD;
+ gen_op_mov_TN_reg[OT_WORD][0][R_EDX]();
+ gen_op_in[ot]();
+ gen_op_mov_reg_T1[ot][R_EAX]();
+ }
break;
case 0xee:
case 0xef:
- if ((b & 1) == 0)
- ot = OT_BYTE;
- else
- ot = dflag ? OT_LONG : OT_WORD;
- gen_op_mov_TN_reg[OT_WORD][0][R_EDX]();
- gen_op_mov_TN_reg[ot][1][R_EAX]();
- gen_op_out[ot]();
+ if (s->cpl > s->iopl || s->vm86) {
+ gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
+ } else {
+ if ((b & 1) == 0)
+ ot = OT_BYTE;
+ else
+ ot = dflag ? OT_LONG : OT_WORD;
+ gen_op_mov_TN_reg[OT_WORD][0][R_EDX]();
+ gen_op_mov_TN_reg[ot][1][R_EAX]();
+ gen_op_out[ot]();
+ }
break;
/************************/
val = ldsw(s->pc);
s->pc += 2;
gen_pop_T0(s);
- if (s->ss32)
- gen_op_addl_ESP_im(val + (2 << s->dflag));
- else
- gen_op_addw_ESP_im(val + (2 << s->dflag));
+ gen_stack_update(s, val + (2 << s->dflag));
if (s->dflag == 0)
gen_op_andl_T0_ffff();
gen_op_jmp_T0();
s->is_jmp = 1;
break;
case 0xca: /* lret im */
- /* XXX: not restartable */
val = ldsw(s->pc);
s->pc += 2;
+ do_lret:
+ gen_stack_A0(s);
/* pop offset */
- gen_pop_T0(s);
+ gen_op_ld_T0_A0[1 + s->dflag]();
if (s->dflag == 0)
gen_op_andl_T0_ffff();
+ /* NOTE: keeping EIP updated is not a problem in case of
+ exception */
gen_op_jmp_T0();
- gen_pop_update(s);
/* pop selector */
- gen_pop_T0(s);
- gen_movl_seg_T0(s, R_CS);
- gen_pop_update(s);
+ gen_op_addl_A0_im(2 << s->dflag);
+ gen_op_ld_T0_A0[1 + s->dflag]();
+ gen_movl_seg_T0(s, R_CS, pc_start - s->cs_base);
/* add stack offset */
- if (s->ss32)
- gen_op_addl_ESP_im(val + (2 << s->dflag));
- else
- gen_op_addw_ESP_im(val + (2 << s->dflag));
+ gen_stack_update(s, val + (4 << s->dflag));
s->is_jmp = 1;
break;
case 0xcb: /* lret */
- /* XXX: not restartable */
- /* pop offset */
- gen_pop_T0(s);
- if (s->dflag == 0)
- gen_op_andl_T0_ffff();
- gen_op_jmp_T0();
- gen_pop_update(s);
- /* pop selector */
- gen_pop_T0(s);
- gen_movl_seg_T0(s, R_CS);
- gen_pop_update(s);
- s->is_jmp = 1;
- break;
+ val = 0;
+ goto do_lret;
case 0xcf: /* iret */
- /* XXX: not restartable */
- /* pop offset */
- gen_pop_T0(s);
- if (s->dflag == 0)
- gen_op_andl_T0_ffff();
- gen_op_jmp_T0();
- gen_pop_update(s);
- /* pop selector */
- gen_pop_T0(s);
- gen_movl_seg_T0(s, R_CS);
- gen_pop_update(s);
- /* pop eflags */
- gen_pop_T0(s);
- if (s->dflag) {
- if (s->vm86)
- gen_op_movl_eflags_T0_vm(pc_start - s->cs_base);
- else
- gen_op_movl_eflags_T0();
+ if (s->vm86 && s->iopl != 3) {
+ gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
} else {
- if (s->vm86)
- gen_op_movw_eflags_T0_vm(pc_start - s->cs_base);
- else
+ /* XXX: not restartable */
+ gen_stack_A0(s);
+ /* pop offset */
+ gen_op_ld_T0_A0[1 + s->dflag]();
+ if (s->dflag == 0)
+ gen_op_andl_T0_ffff();
+ /* NOTE: keeping EIP updated is not a problem in case of
+ exception */
+ gen_op_jmp_T0();
+ /* pop selector */
+ gen_op_addl_A0_im(2 << s->dflag);
+ gen_op_ld_T0_A0[1 + s->dflag]();
+ /* pop eflags */
+ gen_op_addl_A0_im(2 << s->dflag);
+ gen_op_ld_T1_A0[1 + s->dflag]();
+ gen_movl_seg_T0(s, R_CS, pc_start - s->cs_base);
+ gen_op_movl_T0_T1();
+ if (s->dflag) {
+ gen_op_movl_eflags_T0();
+ } else {
gen_op_movw_eflags_T0();
+ }
+ gen_stack_update(s, (6 << s->dflag));
+ s->cc_op = CC_OP_EFLAGS;
}
- gen_pop_update(s);
- s->cc_op = CC_OP_EFLAGS;
s->is_jmp = 1;
break;
case 0xe8: /* call im */
val &= 0xffff;
gen_op_movl_T0_im(next_eip);
gen_push_T0(s);
- gen_op_jmp_im(val);
- s->is_jmp = 1;
+ gen_jmp(s, val);
}
break;
case 0x9a: /* lcall im */
{
unsigned int selector, offset;
+ /* XXX: not restartable */
ot = dflag ? OT_LONG : OT_WORD;
offset = insn_get(s, ot);
/* change cs and pc */
gen_op_movl_T0_im(selector);
- gen_movl_seg_T0(s, R_CS);
+ gen_movl_seg_T0(s, R_CS, pc_start - s->cs_base);
gen_op_jmp_im((unsigned long)offset);
s->is_jmp = 1;
}
val += s->pc - s->cs_base;
if (s->dflag == 0)
val = val & 0xffff;
- gen_op_jmp_im(val);
- s->is_jmp = 1;
+ gen_jmp(s, val);
break;
case 0xea: /* ljmp im */
{
/* change cs and pc */
gen_op_movl_T0_im(selector);
- gen_movl_seg_T0(s, R_CS);
+ gen_movl_seg_T0(s, R_CS, pc_start - s->cs_base);
gen_op_jmp_im((unsigned long)offset);
s->is_jmp = 1;
}
val += s->pc - s->cs_base;
if (s->dflag == 0)
val = val & 0xffff;
- gen_op_jmp_im(val);
- s->is_jmp = 1;
+ gen_jmp(s, val);
break;
case 0x70 ... 0x7f: /* jcc Jb */
val = (int8_t)insn_get(s, OT_BYTE);
if (s->dflag == 0)
val &= 0xffff;
gen_jcc(s, b, val, next_eip);
- s->is_jmp = 1;
break;
case 0x190 ... 0x19f: /* setcc Gv */
/************************/
/* flags */
case 0x9c: /* pushf */
- if (s->cc_op != CC_OP_DYNAMIC)
- gen_op_set_cc_op(s->cc_op);
- if (s->vm86)
- gen_op_movl_T0_eflags_vm();
- else
+ if (s->vm86 && s->iopl != 3) {
+ gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
+ } else {
+ if (s->cc_op != CC_OP_DYNAMIC)
+ gen_op_set_cc_op(s->cc_op);
gen_op_movl_T0_eflags();
- gen_push_T0(s);
+ gen_push_T0(s);
+ }
break;
case 0x9d: /* popf */
- gen_pop_T0(s);
- if (s->dflag) {
- if (s->vm86)
- gen_op_movl_eflags_T0_vm(pc_start - s->cs_base);
- else
- gen_op_movl_eflags_T0();
+ if (s->vm86 && s->iopl != 3) {
+ gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
} else {
- if (s->vm86)
- gen_op_movw_eflags_T0_vm(pc_start - s->cs_base);
- else
+ gen_pop_T0(s);
+ if (s->dflag) {
+ gen_op_movl_eflags_T0();
+ } else {
gen_op_movw_eflags_T0();
+ }
+ gen_pop_update(s);
+ s->cc_op = CC_OP_EFLAGS;
+ s->is_jmp = 2; /* abort translation because TF flag may change */
}
- gen_pop_update(s);
- s->cc_op = CC_OP_EFLAGS;
break;
case 0x9e: /* sahf */
gen_op_mov_TN_reg[OT_BYTE][0][R_AH]();
/* misc */
case 0x90: /* nop */
break;
+ case 0x9b: /* fwait */
+ break;
case 0xcc: /* int3 */
- gen_op_int3((long)pc_start);
- s->is_jmp = 1;
+ gen_interrupt(s, EXCP03_INT3, pc_start - s->cs_base, s->pc - s->cs_base);
break;
case 0xcd: /* int N */
val = ldub(s->pc++);
- /* XXX: currently we ignore the interrupt number */
- gen_op_int_im(pc_start - s->cs_base);
- s->is_jmp = 1;
+ /* XXX: add error code for vm86 GPF */
+ if (!s->vm86)
+ gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base);
+ else
+ gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
break;
case 0xce: /* into */
if (s->cc_op != CC_OP_DYNAMIC)
gen_op_set_cc_op(s->cc_op);
- gen_op_into();
+ gen_op_into(s->pc - s->cs_base);
break;
case 0xfa: /* cli */
- if (s->vm86)
- gen_op_cli_vm();
- else
- gen_op_cli();
+ if (!s->vm86) {
+ if (s->cpl <= s->iopl) {
+ gen_op_cli();
+ } else {
+ gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
+ }
+ } else {
+ if (s->iopl == 3) {
+ gen_op_cli();
+ } else {
+ gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
+ }
+ }
break;
case 0xfb: /* sti */
- if (s->vm86)
- gen_op_sti_vm(pc_start - s->cs_base);
- else
- gen_op_sti();
+ if (!s->vm86) {
+ if (s->cpl <= s->iopl) {
+ gen_op_sti();
+ } else {
+ gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
+ }
+ } else {
+ if (s->iopl == 3) {
+ gen_op_sti();
+ } else {
+ gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
+ }
+ }
break;
case 0x62: /* bound */
ot = dflag ? OT_LONG : OT_WORD;
gen_op_mov_reg_T0[ot][reg]();
gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
if (ot == OT_WORD)
- gen_op_boundw();
+ gen_op_boundw(pc_start - s->cs_base);
else
- gen_op_boundl();
+ gen_op_boundl(pc_start - s->cs_base);
break;
case 0x1c8 ... 0x1cf: /* bswap reg */
reg = b & 7;
case 0x1a2: /* cpuid */
gen_op_cpuid();
break;
+ case 0xf4: /* hlt */
+ /* XXX: if cpl == 0, then should do something else */
+ gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
+ break;
+ case 0x102: /* lar */
+ case 0x103: /* lsl */
+ if (s->vm86)
+ goto illegal_op;
+ ot = dflag ? OT_LONG : OT_WORD;
+ modrm = ldub(s->pc++);
+ reg = (modrm >> 3) & 7;
+ gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
+ gen_op_mov_TN_reg[ot][1][reg]();
+ if (s->cc_op != CC_OP_DYNAMIC)
+ gen_op_set_cc_op(s->cc_op);
+ if (b == 0x102)
+ gen_op_lar();
+ else
+ gen_op_lsl();
+ s->cc_op = CC_OP_EFLAGS;
+ gen_op_mov_reg_T1[ot][reg]();
+ break;
default:
goto illegal_op;
}
[INDEX_op_sbbw_T0_T1_cc] = CC_C,
[INDEX_op_sbbl_T0_T1_cc] = CC_C,
- [INDEX_op_into] = CC_O,
+ /* subtle: due to the incl/decl implementation, C is used */
+ [INDEX_op_incl_T0_cc] = CC_C,
+ [INDEX_op_decl_T0_cc] = CC_C,
- [INDEX_op_jo_cc] = CC_O,
- [INDEX_op_jb_cc] = CC_C,
- [INDEX_op_jz_cc] = CC_Z,
- [INDEX_op_jbe_cc] = CC_Z | CC_C,
- [INDEX_op_js_cc] = CC_S,
- [INDEX_op_jp_cc] = CC_P,
- [INDEX_op_jl_cc] = CC_O | CC_S,
- [INDEX_op_jle_cc] = CC_O | CC_S | CC_Z,
+ [INDEX_op_into] = CC_O,
[INDEX_op_jb_subb] = CC_C,
[INDEX_op_jb_subw] = CC_C,
[INDEX_op_setle_T0_subl] = CC_O | CC_S | CC_Z,
[INDEX_op_movl_T0_eflags] = CC_OSZAPC,
- [INDEX_op_movl_T0_eflags_vm] = CC_OSZAPC,
[INDEX_op_cmc] = CC_C,
[INDEX_op_salc] = CC_C,
[INDEX_op_xorl_T0_T1_cc] = CC_OSZAPC,
[INDEX_op_cmpl_T0_T1_cc] = CC_OSZAPC,
[INDEX_op_negl_T0_cc] = CC_OSZAPC,
- [INDEX_op_incl_T0_cc] = CC_OSZAP,
- [INDEX_op_decl_T0_cc] = CC_OSZAP,
+ /* subtle: due to the incl/decl implementation, C is used */
+ [INDEX_op_incl_T0_cc] = CC_OSZAPC,
+ [INDEX_op_decl_T0_cc] = CC_OSZAPC,
[INDEX_op_testl_T0_T1_cc] = CC_OSZAPC,
[INDEX_op_mulb_AL_T0] = CC_OSZAPC,
[INDEX_op_movb_eflags_T0] = CC_S | CC_Z | CC_A | CC_P | CC_C,
[INDEX_op_movw_eflags_T0] = CC_OSZAPC,
- [INDEX_op_movw_eflags_T0_vm] = CC_OSZAPC,
[INDEX_op_movl_eflags_T0] = CC_OSZAPC,
- [INDEX_op_movl_eflags_T0_vm] = CC_OSZAPC,
[INDEX_op_clc] = CC_C,
[INDEX_op_stc] = CC_C,
[INDEX_op_cmc] = CC_C,
[INDEX_op_cmpxchgl_T0_T1_EAX_cc] = CC_OSZAPC,
[INDEX_op_cmpxchg8b] = CC_Z,
+ [INDEX_op_lar] = CC_Z,
+ [INDEX_op_lsl] = CC_Z,
+ [INDEX_op_fcomi_ST0_FT0] = CC_Z | CC_P | CC_C,
+ [INDEX_op_fucomi_ST0_FT0] = CC_Z | CC_P | CC_C,
};
/* simpler form of an operation if no flags need to be generated */
#ifdef DEBUG_DISAS
static const char *op_str[] = {
-#define DEF(s, n) #s,
+#define DEF(s, n, copy_size) #s,
#include "opc-i386.h"
#undef DEF
};
static uint8_t op_nb_args[] = {
-#define DEF(s, n) n,
+#define DEF(s, n, copy_size) n,
#include "opc-i386.h"
#undef DEF
};
for(;;) {
c = *opc_ptr++;
n = op_nb_args[c];
- fprintf(logfile, "0x%04x: %s", opc_ptr - opc_buf - 1, op_str[c]);
+ fprintf(logfile, "0x%04x: %s",
+ (int)(opc_ptr - opc_buf - 1), op_str[c]);
for(i = 0; i < n; i++) {
fprintf(logfile, " 0x%x", opparam_ptr[i]);
}
#endif
-/* XXX: make this buffer thread safe */
/* XXX: make safe guess about sizes */
#define MAX_OP_PER_INSTR 32
#define OPC_BUF_SIZE 512
static uint16_t gen_opc_buf[OPC_BUF_SIZE];
static uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
+static uint32_t gen_opc_pc[OPC_BUF_SIZE];
+static uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
-/* return non zero if the very first instruction is invalid so that
- the virtual CPU can trigger an exception. */
-int cpu_x86_gen_code(uint8_t *gen_code_buf, int max_code_size,
- int *gen_code_size_ptr,
- uint8_t *pc_start, uint8_t *cs_base, int flags)
+/* generate intermediate code in gen_opc_buf and gen_opparam_buf for
+ basic block 'tb'. If search_pc is TRUE, also generate PC
+ information for each intermediate instruction. */
+static inline int gen_intermediate_code(TranslationBlock *tb, int search_pc)
{
DisasContext dc1, *dc = &dc1;
uint8_t *pc_ptr;
uint16_t *gen_opc_end;
- int gen_code_size;
+ int flags, j, lj;
long ret;
+ uint8_t *pc_start;
+ uint8_t *cs_base;
/* generate intermediate code */
-
+ pc_start = (uint8_t *)tb->pc;
+ cs_base = (uint8_t *)tb->cs_base;
+ flags = tb->flags;
+
dc->code32 = (flags >> GEN_FLAG_CODE32_SHIFT) & 1;
dc->ss32 = (flags >> GEN_FLAG_SS32_SHIFT) & 1;
dc->addseg = (flags >> GEN_FLAG_ADDSEG_SHIFT) & 1;
dc->f_st = (flags >> GEN_FLAG_ST_SHIFT) & 7;
dc->vm86 = (flags >> GEN_FLAG_VM_SHIFT) & 1;
+ dc->cpl = (flags >> GEN_FLAG_CPL_SHIFT) & 3;
+ dc->iopl = (flags >> GEN_FLAG_IOPL_SHIFT) & 3;
+ dc->tf = (flags >> GEN_FLAG_TF_SHIFT) & 1;
dc->cc_op = CC_OP_DYNAMIC;
dc->cs_base = cs_base;
+ dc->tb = tb;
gen_opc_ptr = gen_opc_buf;
gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
dc->is_jmp = 0;
pc_ptr = pc_start;
+ lj = -1;
do {
+ if (search_pc) {
+ j = gen_opc_ptr - gen_opc_buf;
+ if (lj < j) {
+ lj++;
+ while (lj < j)
+ gen_opc_instr_start[lj++] = 0;
+ gen_opc_pc[lj] = (uint32_t)pc_ptr;
+ gen_opc_instr_start[lj] = 1;
+ }
+ }
ret = disas_insn(dc, pc_ptr);
if (ret == -1) {
/* we trigger an illegal instruction operation only if it
break;
}
pc_ptr = (void *)ret;
- } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end);
+ /* if single step mode, we generate only one instruction and
+ generate an exception */
+ if (dc->tf)
+ break;
+ } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end &&
+ (pc_ptr - pc_start) < (TARGET_PAGE_SIZE - 32));
/* we must store the eflags state if it is not already done */
- if (dc->cc_op != CC_OP_DYNAMIC)
- gen_op_set_cc_op(dc->cc_op);
- if (dc->is_jmp != 1) {
- /* we add an additionnal jmp to update the simulated PC */
- gen_op_jmp_im(ret - (unsigned long)dc->cs_base);
+ if (dc->is_jmp != 3) {
+ if (dc->cc_op != CC_OP_DYNAMIC)
+ gen_op_set_cc_op(dc->cc_op);
+ if (dc->is_jmp != 1) {
+ /* we add an additionnal jmp to update the simulated PC */
+ gen_op_jmp_im(ret - (unsigned long)dc->cs_base);
+ }
+ }
+ if (dc->tf) {
+ gen_op_raise_exception(EXCP01_SSTP);
}
+ if (dc->is_jmp != 3) {
+ /* indicate that the hash table must be used to find the next TB */
+ gen_op_movl_T0_0();
+ }
+
*gen_opc_ptr = INDEX_op_end;
#ifdef DEBUG_DISAS
disas(logfile, pc_start, pc_ptr - pc_start,
dc->code32 ? DISAS_I386_I386 : DISAS_I386_I8086);
fprintf(logfile, "\n");
-
+
fprintf(logfile, "OP:\n");
dump_ops(gen_opc_buf, gen_opparam_buf);
fprintf(logfile, "\n");
fprintf(logfile, "\n");
}
#endif
+ if (!search_pc)
+ tb->size = pc_ptr - pc_start;
+ return 0;
+}
+
+
+/* return non zero if the very first instruction is invalid so that
+ the virtual CPU can trigger an exception.
+
+ '*gen_code_size_ptr' contains the size of the generated code (host
+ code).
+*/
+int cpu_x86_gen_code(TranslationBlock *tb,
+ int max_code_size, int *gen_code_size_ptr)
+{
+ uint8_t *gen_code_buf;
+ int gen_code_size;
+
+ if (gen_intermediate_code(tb, 0) < 0)
+ return -1;
/* generate machine code */
- gen_code_size = dyngen_code(gen_code_buf, gen_opc_buf, gen_opparam_buf);
+ tb->tb_next_offset[0] = 0xffff;
+ tb->tb_next_offset[1] = 0xffff;
+ gen_code_buf = tb->tc_ptr;
+ gen_code_size = dyngen_code(gen_code_buf, tb->tb_next_offset,
+#ifdef USE_DIRECT_JUMP
+ tb->tb_jmp_offset,
+#else
+ NULL,
+#endif
+ gen_opc_buf, gen_opparam_buf);
flush_icache_range((unsigned long)gen_code_buf, (unsigned long)(gen_code_buf + gen_code_size));
+
*gen_code_size_ptr = gen_code_size;
-
#ifdef DEBUG_DISAS
if (loglevel) {
fprintf(logfile, "OUT: [size=%d]\n", *gen_code_size_ptr);
- disas(logfile, gen_code_buf, *gen_code_size_ptr, DISAS_TARGET);
+ disas(logfile, gen_code_buf, *gen_code_size_ptr, DISAS_TARGET);
fprintf(logfile, "\n");
fflush(logfile);
}
return 0;
}
+static const unsigned short opc_copy_size[] = {
+#define DEF(s, n, copy_size) copy_size,
+#include "opc-i386.h"
+#undef DEF
+};
+
+/* The simulated PC corresponding to
+ 'searched_pc' in the generated code is searched. 0 is returned if
+ found. *found_pc contains the found PC.
+ */
+int cpu_x86_search_pc(TranslationBlock *tb,
+ uint32_t *found_pc, unsigned long searched_pc)
+{
+ int j, c;
+ unsigned long tc_ptr;
+ uint16_t *opc_ptr;
+
+ if (gen_intermediate_code(tb, 1) < 0)
+ return -1;
+
+ /* find opc index corresponding to search_pc */
+ tc_ptr = (unsigned long)tb->tc_ptr;
+ if (searched_pc < tc_ptr)
+ return -1;
+ j = 0;
+ opc_ptr = gen_opc_buf;
+ for(;;) {
+ c = *opc_ptr;
+ if (c == INDEX_op_end)
+ return -1;
+ tc_ptr += opc_copy_size[c];
+ if (searched_pc < tc_ptr)
+ break;
+ opc_ptr++;
+ }
+ j = opc_ptr - gen_opc_buf;
+ /* now find start of instruction before */
+ while (gen_opc_instr_start[j] == 0)
+ j--;
+ *found_pc = gen_opc_pc[j];
+ return 0;
+}
+
+
CPUX86State *cpu_x86_init(void)
{
CPUX86State *env;
if (!inited) {
inited = 1;
optimize_flags_init();
+ page_init();
}
return env;
}
{
free(env);
}
+
+static const char *cc_op_str[] = {
+ "DYNAMIC",
+ "EFLAGS",
+ "MUL",
+ "ADDB",
+ "ADDW",
+ "ADDL",
+ "ADCB",
+ "ADCW",
+ "ADCL",
+ "SUBB",
+ "SUBW",
+ "SUBL",
+ "SBBB",
+ "SBBW",
+ "SBBL",
+ "LOGICB",
+ "LOGICW",
+ "LOGICL",
+ "INCB",
+ "INCW",
+ "INCL",
+ "DECB",
+ "DECW",
+ "DECL",
+ "SHLB",
+ "SHLW",
+ "SHLL",
+ "SARB",
+ "SARW",
+ "SARL",
+};
+
+void cpu_x86_dump_state(CPUX86State *env, FILE *f, int flags)
+{
+ int eflags;
+ char cc_op_name[32];
+
+ eflags = env->eflags;
+ fprintf(f, "EAX=%08x EBX=%08x ECX=%08x EDX=%08x\n"
+ "ESI=%08x EDI=%08x EBP=%08x ESP=%08x\n"
+ "EIP=%08x EFL=%08x [%c%c%c%c%c%c%c]\n",
+ env->regs[R_EAX], env->regs[R_EBX], env->regs[R_ECX], env->regs[R_EDX],
+ env->regs[R_ESI], env->regs[R_EDI], env->regs[R_EBP], env->regs[R_ESP],
+ env->eip, eflags,
+ eflags & DF_MASK ? 'D' : '-',
+ eflags & CC_O ? 'O' : '-',
+ eflags & CC_S ? 'S' : '-',
+ eflags & CC_Z ? 'Z' : '-',
+ eflags & CC_A ? 'A' : '-',
+ eflags & CC_P ? 'P' : '-',
+ eflags & CC_C ? 'C' : '-');
+ fprintf(f, "CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x\n",
+ env->segs[R_CS],
+ env->segs[R_SS],
+ env->segs[R_DS],
+ env->segs[R_ES],
+ env->segs[R_FS],
+ env->segs[R_GS]);
+ if (flags & X86_DUMP_CCOP) {
+ if ((unsigned)env->cc_op < CC_OP_NB)
+ strcpy(cc_op_name, cc_op_str[env->cc_op]);
+ else
+ snprintf(cc_op_name, sizeof(cc_op_name), "[%d]", env->cc_op);
+ fprintf(f, "CCS=%08x CCD=%08x CCO=%-8s\n",
+ env->cc_src, env->cc_dst, cc_op_name);
+ }
+ if (flags & X86_DUMP_FPU) {
+ fprintf(f, "ST0=%f ST1=%f ST2=%f ST3=%f\n",
+ (double)env->fpregs[0],
+ (double)env->fpregs[1],
+ (double)env->fpregs[2],
+ (double)env->fpregs[3]);
+ fprintf(f, "ST4=%f ST5=%f ST6=%f ST7=%f\n",
+ (double)env->fpregs[4],
+ (double)env->fpregs[5],
+ (double)env->fpregs[7],
+ (double)env->fpregs[8]);
+ }
+}
projects / qemu / blobdiff