#ifdef TARGET_SPARC64
static TCGv cpu_xcc, cpu_asi, cpu_fprs, cpu_gsr;
static TCGv cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr;
-static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver;
+static TCGv cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver, cpu_softint;
#else
static TCGv cpu_wim;
#endif
goto jmp_insn;
gen_movl_TN_reg(rd, cpu_gsr);
break;
+ case 0x16: /* Softint */
+ tcg_gen_ext_i32_tl(cpu_dst, cpu_softint);
+ gen_movl_TN_reg(rd, cpu_dst);
+ break;
case 0x17: /* Tick compare */
gen_movl_TN_reg(rd, cpu_tick_cmpr);
break;
case 0x12: /* Dispatch Control */
case 0x14: /* Softint set, WO */
case 0x15: /* Softint clear, WO */
- case 0x16: /* Softint write */
#endif
default:
goto illegal_insn;
goto jmp_insn;
tcg_gen_xor_tl(cpu_gsr, cpu_src1, cpu_src2);
break;
+ case 0x14: /* Softint set */
+ if (!supervisor(dc))
+ goto illegal_insn;
+ tcg_gen_xor_tl(cpu_tmp64, cpu_src1, cpu_src2);
+ tcg_gen_helper_0_1(helper_set_softint,
+ cpu_tmp64);
+ break;
+ case 0x15: /* Softint clear */
+ if (!supervisor(dc))
+ goto illegal_insn;
+ tcg_gen_xor_tl(cpu_tmp64, cpu_src1, cpu_src2);
+ tcg_gen_helper_0_1(helper_clear_softint,
+ cpu_tmp64);
+ break;
+ case 0x16: /* Softint write */
+ if (!supervisor(dc))
+ goto illegal_insn;
+ tcg_gen_xor_tl(cpu_tmp64, cpu_src1, cpu_src2);
+ tcg_gen_helper_0_1(helper_write_softint,
+ cpu_tmp64);
+ break;
case 0x17: /* Tick compare */
#if !defined(CONFIG_USER_ONLY)
if (!supervisor(dc))
case 0x11: /* Performance Instrumentation
Counter */
case 0x12: /* Dispatch Control */
- case 0x14: /* Softint set */
- case 0x15: /* Softint clear */
- case 0x16: /* Softint write */
#endif
default:
goto illegal_insn;
offsetof(CPUState, ssr), "ssr");
cpu_ver = tcg_global_mem_new(TCG_TYPE_TL, TCG_AREG0,
offsetof(CPUState, version), "ver");
+ cpu_softint = tcg_global_mem_new(TCG_TYPE_I32, TCG_AREG0,
+ offsetof(CPUState, softint),
+ "softint");
#else
cpu_wim = tcg_global_mem_new(TCG_TYPE_I32,
TCG_AREG0, offsetof(CPUState, wim),