* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#include "exec.h"
+#include "host-utils.h"
+#include "helper.h"
-#include "op_helper.h"
-
-#define MEMSUFFIX _raw
-#include "op_helper.h"
-#include "op_helper_mem.h"
-#if !defined(CONFIG_USER_ONLY)
-#define MEMSUFFIX _user
-#include "op_helper.h"
-#include "op_helper_mem.h"
-#define MEMSUFFIX _kernel
-#include "op_helper.h"
-#include "op_helper_mem.h"
-#endif
+#include "helper_regs.h"
//#define DEBUG_OP
//#define DEBUG_EXCEPTIONS
/*****************************************************************************/
/* Exceptions processing helpers */
-void do_raise_exception_err (uint32_t exception, int error_code)
+void helper_raise_exception_err (uint32_t exception, uint32_t error_code)
{
#if 0
printf("Raise exception %3x code : %d\n", exception, error_code);
#endif
- switch (exception) {
- case POWERPC_EXCP_PROGRAM:
- if (error_code == POWERPC_EXCP_FP && msr_fe0 == 0 && msr_fe1 == 0)
- return;
- break;
- default:
- break;
- }
env->exception_index = exception;
env->error_code = error_code;
cpu_loop_exit();
}
-void do_raise_exception (uint32_t exception)
-{
- do_raise_exception_err(exception, 0);
-}
-
-void cpu_dump_EA (target_ulong EA);
-void do_print_mem_EA (target_ulong EA)
+void helper_raise_exception (uint32_t exception)
{
- cpu_dump_EA(EA);
+ helper_raise_exception_err(exception, 0);
}
/*****************************************************************************/
/* Registers load and stores */
-void do_load_cr (void)
+target_ulong helper_load_cr (void)
{
- T0 = (env->crf[0] << 28) |
- (env->crf[1] << 24) |
- (env->crf[2] << 20) |
- (env->crf[3] << 16) |
- (env->crf[4] << 12) |
- (env->crf[5] << 8) |
- (env->crf[6] << 4) |
- (env->crf[7] << 0);
+ return (env->crf[0] << 28) |
+ (env->crf[1] << 24) |
+ (env->crf[2] << 20) |
+ (env->crf[3] << 16) |
+ (env->crf[4] << 12) |
+ (env->crf[5] << 8) |
+ (env->crf[6] << 4) |
+ (env->crf[7] << 0);
}
-void do_store_cr (uint32_t mask)
+void helper_store_cr (target_ulong val, uint32_t mask)
{
int i, sh;
for (i = 0, sh = 7; i < 8; i++, sh--) {
if (mask & (1 << sh))
- env->crf[i] = (T0 >> (sh * 4)) & 0xFUL;
+ env->crf[i] = (val >> (sh * 4)) & 0xFUL;
}
}
-void do_load_xer (void)
+/*****************************************************************************/
+/* SPR accesses */
+void helper_load_dump_spr (uint32_t sprn)
{
- T0 = (xer_so << XER_SO) |
- (xer_ov << XER_OV) |
- (xer_ca << XER_CA) |
- (xer_bc << XER_BC) |
- (xer_cmp << XER_CMP);
+ if (loglevel != 0) {
+ fprintf(logfile, "Read SPR %d %03x => " ADDRX "\n",
+ sprn, sprn, env->spr[sprn]);
+ }
}
-void do_store_xer (void)
+void helper_store_dump_spr (uint32_t sprn)
{
- xer_so = (T0 >> XER_SO) & 0x01;
- xer_ov = (T0 >> XER_OV) & 0x01;
- xer_ca = (T0 >> XER_CA) & 0x01;
- xer_cmp = (T0 >> XER_CMP) & 0xFF;
- xer_bc = (T0 >> XER_BC) & 0x7F;
+ if (loglevel != 0) {
+ fprintf(logfile, "Write SPR %d %03x <= " ADDRX "\n",
+ sprn, sprn, env->spr[sprn]);
+ }
}
-#if defined(TARGET_PPC64)
-void do_store_pri (int prio)
+target_ulong helper_load_tbl (void)
{
- env->spr[SPR_PPR] &= ~0x001C000000000000ULL;
- env->spr[SPR_PPR] |= ((uint64_t)prio & 0x7) << 50;
+ return cpu_ppc_load_tbl(env);
}
-#endif
-void do_load_fpscr (void)
+target_ulong helper_load_tbu (void)
{
- /* The 32 MSB of the target fpr are undefined.
- * They'll be zero...
- */
- union {
- float64 d;
- struct {
- uint32_t u[2];
- } s;
- } u;
- int i;
-
-#if defined(WORDS_BIGENDIAN)
-#define WORD0 0
-#define WORD1 1
-#else
-#define WORD0 1
-#define WORD1 0
-#endif
- u.s.u[WORD0] = 0;
- u.s.u[WORD1] = 0;
- for (i = 0; i < 8; i++)
- u.s.u[WORD1] |= env->fpscr[i] << (4 * i);
- FT0 = u.d;
+ return cpu_ppc_load_tbu(env);
}
-void do_store_fpscr (uint32_t mask)
+target_ulong helper_load_atbl (void)
{
- /*
- * We use only the 32 LSB of the incoming fpr
- */
- union {
- double d;
- struct {
- uint32_t u[2];
- } s;
- } u;
- int i, rnd_type;
-
- u.d = FT0;
- if (mask & 0x80)
- env->fpscr[0] = (env->fpscr[0] & 0x9) | ((u.s.u[WORD1] >> 28) & ~0x9);
- for (i = 1; i < 7; i++) {
- if (mask & (1 << (7 - i)))
- env->fpscr[i] = (u.s.u[WORD1] >> (4 * (7 - i))) & 0xF;
- }
- /* TODO: update FEX & VX */
- /* Set rounding mode */
- switch (env->fpscr[0] & 0x3) {
- case 0:
- /* Best approximation (round to nearest) */
- rnd_type = float_round_nearest_even;
- break;
- case 1:
- /* Smaller magnitude (round toward zero) */
- rnd_type = float_round_to_zero;
- break;
- case 2:
- /* Round toward +infinite */
- rnd_type = float_round_up;
- break;
- default:
- case 3:
- /* Round toward -infinite */
- rnd_type = float_round_down;
- break;
- }
- set_float_rounding_mode(rnd_type, &env->fp_status);
+ return cpu_ppc_load_atbl(env);
}
-target_ulong ppc_load_dump_spr (int sprn)
+target_ulong helper_load_atbu (void)
{
- if (loglevel != 0) {
- fprintf(logfile, "Read SPR %d %03x => " ADDRX "\n",
- sprn, sprn, env->spr[sprn]);
- }
+ return cpu_ppc_load_atbu(env);
+}
- return env->spr[sprn];
+target_ulong helper_load_601_rtcl (void)
+{
+ return cpu_ppc601_load_rtcl(env);
}
-void ppc_store_dump_spr (int sprn, target_ulong val)
+target_ulong helper_load_601_rtcu (void)
{
- if (loglevel != 0) {
- fprintf(logfile, "Write SPR %d %03x => " ADDRX " <= " ADDRX "\n",
- sprn, sprn, env->spr[sprn], val);
- }
- env->spr[sprn] = val;
+ return cpu_ppc601_load_rtcu(env);
}
-/*****************************************************************************/
-/* Fixed point operations helpers */
-#if defined(TARGET_PPC64)
-static void add128 (uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b)
+#if !defined(CONFIG_USER_ONLY)
+#if defined (TARGET_PPC64)
+void helper_store_asr (target_ulong val)
{
- *plow += a;
- /* carry test */
- if (*plow < a)
- (*phigh)++;
- *phigh += b;
+ ppc_store_asr(env, val);
}
+#endif
-static void neg128 (uint64_t *plow, uint64_t *phigh)
+void helper_store_sdr1 (target_ulong val)
{
- *plow = ~*plow;
- *phigh = ~*phigh;
- add128(plow, phigh, 1, 0);
+ ppc_store_sdr1(env, val);
}
-static void mul64 (uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b)
+void helper_store_tbl (target_ulong val)
{
- uint32_t a0, a1, b0, b1;
- uint64_t v;
+ cpu_ppc_store_tbl(env, val);
+}
- a0 = a;
- a1 = a >> 32;
+void helper_store_tbu (target_ulong val)
+{
+ cpu_ppc_store_tbu(env, val);
+}
- b0 = b;
- b1 = b >> 32;
+void helper_store_atbl (target_ulong val)
+{
+ cpu_ppc_store_atbl(env, val);
+}
- v = (uint64_t)a0 * (uint64_t)b0;
- *plow = v;
- *phigh = 0;
+void helper_store_atbu (target_ulong val)
+{
+ cpu_ppc_store_atbu(env, val);
+}
- v = (uint64_t)a0 * (uint64_t)b1;
- add128(plow, phigh, v << 32, v >> 32);
+void helper_store_601_rtcl (target_ulong val)
+{
+ cpu_ppc601_store_rtcl(env, val);
+}
- v = (uint64_t)a1 * (uint64_t)b0;
- add128(plow, phigh, v << 32, v >> 32);
+void helper_store_601_rtcu (target_ulong val)
+{
+ cpu_ppc601_store_rtcu(env, val);
+}
- v = (uint64_t)a1 * (uint64_t)b1;
- *phigh += v;
-#if defined(DEBUG_MULDIV)
- printf("mul: 0x%016llx * 0x%016llx = 0x%016llx%016llx\n",
- a, b, *phigh, *plow);
-#endif
+target_ulong helper_load_decr (void)
+{
+ return cpu_ppc_load_decr(env);
}
-void do_mul64 (uint64_t *plow, uint64_t *phigh)
+void helper_store_decr (target_ulong val)
{
- mul64(plow, phigh, T0, T1);
+ cpu_ppc_store_decr(env, val);
}
-static void imul64 (uint64_t *plow, uint64_t *phigh, int64_t a, int64_t b)
+void helper_store_hid0_601 (target_ulong val)
{
- int sa, sb;
+ target_ulong hid0;
- sa = (a < 0);
- if (sa)
- a = -a;
- sb = (b < 0);
- if (sb)
- b = -b;
- mul64(plow, phigh, a, b);
- if (sa ^ sb) {
- neg128(plow, phigh);
+ hid0 = env->spr[SPR_HID0];
+ if ((val ^ hid0) & 0x00000008) {
+ /* Change current endianness */
+ env->hflags &= ~(1 << MSR_LE);
+ env->hflags_nmsr &= ~(1 << MSR_LE);
+ env->hflags_nmsr |= (1 << MSR_LE) & (((val >> 3) & 1) << MSR_LE);
+ env->hflags |= env->hflags_nmsr;
+ if (loglevel != 0) {
+ fprintf(logfile, "%s: set endianness to %c => " ADDRX "\n",
+ __func__, val & 0x8 ? 'l' : 'b', env->hflags);
+ }
}
+ env->spr[SPR_HID0] = (uint32_t)val;
}
-void do_imul64 (uint64_t *plow, uint64_t *phigh)
+void helper_store_403_pbr (uint32_t num, target_ulong value)
{
- imul64(plow, phigh, T0, T1);
+ if (likely(env->pb[num] != value)) {
+ env->pb[num] = value;
+ /* Should be optimized */
+ tlb_flush(env, 1);
+ }
}
-#endif
-void do_adde (void)
+target_ulong helper_load_40x_pit (void)
{
- T2 = T0;
- T0 += T1 + xer_ca;
- if (likely(!((uint32_t)T0 < (uint32_t)T2 ||
- (xer_ca == 1 && (uint32_t)T0 == (uint32_t)T2)))) {
- xer_ca = 0;
- } else {
- xer_ca = 1;
- }
+ return load_40x_pit(env);
}
-#if defined(TARGET_PPC64)
-void do_adde_64 (void)
+void helper_store_40x_pit (target_ulong val)
{
- T2 = T0;
- T0 += T1 + xer_ca;
- if (likely(!((uint64_t)T0 < (uint64_t)T2 ||
- (xer_ca == 1 && (uint64_t)T0 == (uint64_t)T2)))) {
- xer_ca = 0;
- } else {
- xer_ca = 1;
- }
+ store_40x_pit(env, val);
}
-#endif
-void do_addmeo (void)
+void helper_store_40x_dbcr0 (target_ulong val)
{
- T1 = T0;
- T0 += xer_ca + (-1);
- if (likely(!((uint32_t)T1 &
- ((uint32_t)T1 ^ (uint32_t)T0) & (1UL << 31)))) {
- xer_ov = 0;
- } else {
- xer_ov = 1;
- xer_so = 1;
- }
- if (likely(T1 != 0))
- xer_ca = 1;
+ store_40x_dbcr0(env, val);
}
-#if defined(TARGET_PPC64)
-void do_addmeo_64 (void)
+void helper_store_40x_sler (target_ulong val)
{
- T1 = T0;
- T0 += xer_ca + (-1);
- if (likely(!((uint64_t)T1 &
- ((uint64_t)T1 ^ (uint64_t)T0) & (1ULL << 63)))) {
- xer_ov = 0;
- } else {
- xer_ov = 1;
- xer_so = 1;
- }
- if (likely(T1 != 0))
- xer_ca = 1;
+ store_40x_sler(env, val);
}
-#endif
-void do_divwo (void)
+void helper_store_booke_tcr (target_ulong val)
{
- if (likely(!(((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) ||
- (int32_t)T1 == 0))) {
- xer_ov = 0;
- T0 = (int32_t)T0 / (int32_t)T1;
- } else {
- xer_ov = 1;
- xer_so = 1;
- T0 = (-1) * ((uint32_t)T0 >> 31);
- }
+ store_booke_tcr(env, val);
}
-#if defined(TARGET_PPC64)
-void do_divdo (void)
+void helper_store_booke_tsr (target_ulong val)
{
- if (likely(!(((int64_t)T0 == INT64_MIN && (int64_t)T1 == -1ULL) ||
- (int64_t)T1 == 0))) {
- xer_ov = 0;
- T0 = (int64_t)T0 / (int64_t)T1;
- } else {
- xer_ov = 1;
- xer_so = 1;
- T0 = (-1ULL) * ((uint64_t)T0 >> 63);
- }
+ store_booke_tsr(env, val);
}
-#endif
-void do_divwuo (void)
+void helper_store_ibatu (uint32_t nr, target_ulong val)
{
- if (likely((uint32_t)T1 != 0)) {
- xer_ov = 0;
- T0 = (uint32_t)T0 / (uint32_t)T1;
- } else {
- xer_ov = 1;
- xer_so = 1;
- T0 = 0;
- }
+ ppc_store_ibatu(env, nr, val);
}
-#if defined(TARGET_PPC64)
-void do_divduo (void)
+void helper_store_ibatl (uint32_t nr, target_ulong val)
{
- if (likely((uint64_t)T1 != 0)) {
- xer_ov = 0;
- T0 = (uint64_t)T0 / (uint64_t)T1;
- } else {
- xer_ov = 1;
- xer_so = 1;
- T0 = 0;
- }
+ ppc_store_ibatl(env, nr, val);
}
-#endif
-void do_mullwo (void)
+void helper_store_dbatu (uint32_t nr, target_ulong val)
{
- int64_t res = (int64_t)T0 * (int64_t)T1;
+ ppc_store_dbatu(env, nr, val);
+}
- if (likely((int32_t)res == res)) {
- xer_ov = 0;
- } else {
- xer_ov = 1;
- xer_so = 1;
- }
- T0 = (int32_t)res;
+void helper_store_dbatl (uint32_t nr, target_ulong val)
+{
+ ppc_store_dbatl(env, nr, val);
}
-#if defined(TARGET_PPC64)
-void do_mulldo (void)
+void helper_store_601_batl (uint32_t nr, target_ulong val)
{
- int64_t th;
- uint64_t tl;
+ ppc_store_ibatl_601(env, nr, val);
+}
- do_imul64(&tl, &th);
- if (likely(th == 0)) {
- xer_ov = 0;
- } else {
- xer_ov = 1;
- xer_so = 1;
- }
- T0 = (int64_t)tl;
+void helper_store_601_batu (uint32_t nr, target_ulong val)
+{
+ ppc_store_ibatu_601(env, nr, val);
}
#endif
-void do_nego (void)
+/*****************************************************************************/
+/* Memory load and stores */
+
+static always_inline target_ulong addr_add(target_ulong addr, target_long arg)
{
- if (likely((int32_t)T0 != INT32_MIN)) {
- xer_ov = 0;
- T0 = -(int32_t)T0;
- } else {
- xer_ov = 1;
- xer_so = 1;
+#if defined(TARGET_PPC64)
+ if (!msr_sf)
+ return (uint32_t)(addr + arg);
+ else
+#endif
+ return addr + arg;
+}
+
+void helper_lmw (target_ulong addr, uint32_t reg)
+{
+ for (; reg < 32; reg++) {
+ if (msr_le)
+ env->gpr[reg] = bswap32(ldl(addr));
+ else
+ env->gpr[reg] = ldl(addr);
+ addr = addr_add(addr, 4);
}
}
-#if defined(TARGET_PPC64)
-void do_nego_64 (void)
+void helper_stmw (target_ulong addr, uint32_t reg)
{
- if (likely((int64_t)T0 != INT64_MIN)) {
- xer_ov = 0;
- T0 = -(int64_t)T0;
- } else {
- xer_ov = 1;
- xer_so = 1;
+ for (; reg < 32; reg++) {
+ if (msr_le)
+ stl(addr, bswap32((uint32_t)env->gpr[reg]));
+ else
+ stl(addr, (uint32_t)env->gpr[reg]);
+ addr = addr_add(addr, 4);
}
}
-#endif
-void do_subfe (void)
+void helper_lsw(target_ulong addr, uint32_t nb, uint32_t reg)
{
- T0 = T1 + ~T0 + xer_ca;
- if (likely((uint32_t)T0 >= (uint32_t)T1 &&
- (xer_ca == 0 || (uint32_t)T0 != (uint32_t)T1))) {
- xer_ca = 0;
- } else {
- xer_ca = 1;
+ int sh;
+ for (; nb > 3; nb -= 4) {
+ env->gpr[reg] = ldl(addr);
+ reg = (reg + 1) % 32;
+ addr = addr_add(addr, 4);
+ }
+ if (unlikely(nb > 0)) {
+ env->gpr[reg] = 0;
+ for (sh = 24; nb > 0; nb--, sh -= 8) {
+ env->gpr[reg] |= ldub(addr) << sh;
+ addr = addr_add(addr, 1);
+ }
+ }
+}
+/* PPC32 specification says we must generate an exception if
+ * rA is in the range of registers to be loaded.
+ * In an other hand, IBM says this is valid, but rA won't be loaded.
+ * For now, I'll follow the spec...
+ */
+void helper_lswx(target_ulong addr, uint32_t reg, uint32_t ra, uint32_t rb)
+{
+ if (likely(xer_bc != 0)) {
+ if (unlikely((ra != 0 && reg < ra && (reg + xer_bc) > ra) ||
+ (reg < rb && (reg + xer_bc) > rb))) {
+ helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
+ POWERPC_EXCP_INVAL |
+ POWERPC_EXCP_INVAL_LSWX);
+ } else {
+ helper_lsw(addr, xer_bc, reg);
+ }
}
}
-#if defined(TARGET_PPC64)
-void do_subfe_64 (void)
+void helper_stsw(target_ulong addr, uint32_t nb, uint32_t reg)
{
- T0 = T1 + ~T0 + xer_ca;
- if (likely((uint64_t)T0 >= (uint64_t)T1 &&
- (xer_ca == 0 || (uint64_t)T0 != (uint64_t)T1))) {
- xer_ca = 0;
- } else {
- xer_ca = 1;
+ int sh;
+ for (; nb > 3; nb -= 4) {
+ stl(addr, env->gpr[reg]);
+ reg = (reg + 1) % 32;
+ addr = addr_add(addr, 4);
+ }
+ if (unlikely(nb > 0)) {
+ for (sh = 24; nb > 0; nb--, sh -= 8) {
+ stb(addr, (env->gpr[reg] >> sh) & 0xFF);
+ addr = addr_add(addr, 1);
+ }
}
}
-#endif
-void do_subfmeo (void)
+static void do_dcbz(target_ulong addr, int dcache_line_size)
{
- T1 = T0;
- T0 = ~T0 + xer_ca - 1;
- if (likely(!((uint32_t)~T1 & ((uint32_t)~T1 ^ (uint32_t)T0) &
- (1UL << 31)))) {
- xer_ov = 0;
- } else {
- xer_ov = 1;
- xer_so = 1;
+ addr &= ~(dcache_line_size - 1);
+ int i;
+ for (i = 0 ; i < dcache_line_size ; i += 4) {
+ stl(addr + i , 0);
+ }
+ if (env->reserve == addr)
+ env->reserve = (target_ulong)-1ULL;
+}
+
+void helper_dcbz(target_ulong addr)
+{
+ do_dcbz(addr, env->dcache_line_size);
+}
+
+void helper_dcbz_970(target_ulong addr)
+{
+ if (((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1)
+ do_dcbz(addr, 32);
+ else
+ do_dcbz(addr, env->dcache_line_size);
+}
+
+void helper_icbi(target_ulong addr)
+{
+ uint32_t tmp;
+
+ addr &= ~(env->dcache_line_size - 1);
+ /* Invalidate one cache line :
+ * PowerPC specification says this is to be treated like a load
+ * (not a fetch) by the MMU. To be sure it will be so,
+ * do the load "by hand".
+ */
+ tmp = ldl(addr);
+ tb_invalidate_page_range(addr, addr + env->icache_line_size);
+}
+
+// XXX: to be tested
+target_ulong helper_lscbx (target_ulong addr, uint32_t reg, uint32_t ra, uint32_t rb)
+{
+ int i, c, d;
+ d = 24;
+ for (i = 0; i < xer_bc; i++) {
+ c = ldub(addr);
+ addr = addr_add(addr, 1);
+ /* ra (if not 0) and rb are never modified */
+ if (likely(reg != rb && (ra == 0 || reg != ra))) {
+ env->gpr[reg] = (env->gpr[reg] & ~(0xFF << d)) | (c << d);
+ }
+ if (unlikely(c == xer_cmp))
+ break;
+ if (likely(d != 0)) {
+ d -= 8;
+ } else {
+ d = 24;
+ reg++;
+ reg = reg & 0x1F;
+ }
}
- if (likely((uint32_t)T1 != UINT32_MAX))
- xer_ca = 1;
+ return i;
}
+/*****************************************************************************/
+/* Fixed point operations helpers */
#if defined(TARGET_PPC64)
-void do_subfmeo_64 (void)
+
+/* multiply high word */
+uint64_t helper_mulhd (uint64_t arg1, uint64_t arg2)
+{
+ uint64_t tl, th;
+
+ muls64(&tl, &th, arg1, arg2);
+ return th;
+}
+
+/* multiply high word unsigned */
+uint64_t helper_mulhdu (uint64_t arg1, uint64_t arg2)
+{
+ uint64_t tl, th;
+
+ mulu64(&tl, &th, arg1, arg2);
+ return th;
+}
+
+uint64_t helper_mulldo (uint64_t arg1, uint64_t arg2)
{
- T1 = T0;
- T0 = ~T0 + xer_ca - 1;
- if (likely(!((uint64_t)~T1 & ((uint64_t)~T1 ^ (uint64_t)T0) &
- (1ULL << 63)))) {
- xer_ov = 0;
+ int64_t th;
+ uint64_t tl;
+
+ muls64(&tl, (uint64_t *)&th, arg1, arg2);
+ /* If th != 0 && th != -1, then we had an overflow */
+ if (likely((uint64_t)(th + 1) <= 1)) {
+ env->xer &= ~(1 << XER_OV);
} else {
- xer_ov = 1;
- xer_so = 1;
+ env->xer |= (1 << XER_OV) | (1 << XER_SO);
}
- if (likely((uint64_t)T1 != UINT64_MAX))
- xer_ca = 1;
+ return (int64_t)tl;
}
#endif
-void do_subfzeo (void)
+target_ulong helper_cntlzw (target_ulong t)
{
- T1 = T0;
- T0 = ~T0 + xer_ca;
- if (likely(!(((uint32_t)~T1 ^ UINT32_MAX) &
- ((uint32_t)(~T1) ^ (uint32_t)T0) & (1UL << 31)))) {
- xer_ov = 0;
- } else {
- xer_ov = 1;
- xer_so = 1;
- }
- if (likely((uint32_t)T0 >= (uint32_t)~T1)) {
- xer_ca = 0;
- } else {
- xer_ca = 1;
- }
+ return clz32(t);
}
#if defined(TARGET_PPC64)
-void do_subfzeo_64 (void)
+target_ulong helper_cntlzd (target_ulong t)
{
- T1 = T0;
- T0 = ~T0 + xer_ca;
- if (likely(!(((uint64_t)~T1 ^ UINT64_MAX) &
- ((uint64_t)(~T1) ^ (uint64_t)T0) & (1ULL << 63)))) {
- xer_ov = 0;
- } else {
- xer_ov = 1;
- xer_so = 1;
- }
- if (likely((uint64_t)T0 >= (uint64_t)~T1)) {
- xer_ca = 0;
- } else {
- xer_ca = 1;
- }
+ return clz64(t);
}
#endif
/* shift right arithmetic helper */
-void do_sraw (void)
+target_ulong helper_sraw (target_ulong value, target_ulong shift)
{
int32_t ret;
- if (likely(!(T1 & 0x20UL))) {
- if (likely((uint32_t)T1 != 0)) {
- ret = (int32_t)T0 >> (T1 & 0x1fUL);
- if (likely(ret >= 0 || ((int32_t)T0 & ((1 << T1) - 1)) == 0)) {
- xer_ca = 0;
+ if (likely(!(shift & 0x20))) {
+ if (likely((uint32_t)shift != 0)) {
+ shift &= 0x1f;
+ ret = (int32_t)value >> shift;
+ if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
+ env->xer &= ~(1 << XER_CA);
} else {
- xer_ca = 1;
+ env->xer |= (1 << XER_CA);
}
} else {
- ret = T0;
- xer_ca = 0;
+ ret = (int32_t)value;
+ env->xer &= ~(1 << XER_CA);
}
} else {
- ret = (-1) * ((uint32_t)T0 >> 31);
- if (likely(ret >= 0 || ((uint32_t)T0 & ~0x80000000UL) == 0)) {
- xer_ca = 0;
+ ret = (int32_t)value >> 31;
+ if (ret) {
+ env->xer |= (1 << XER_CA);
} else {
- xer_ca = 1;
+ env->xer &= ~(1 << XER_CA);
}
}
- T0 = ret;
+ return (target_long)ret;
}
#if defined(TARGET_PPC64)
-void do_srad (void)
+target_ulong helper_srad (target_ulong value, target_ulong shift)
{
int64_t ret;
- if (likely(!(T1 & 0x40UL))) {
- if (likely((uint64_t)T1 != 0)) {
- ret = (int64_t)T0 >> (T1 & 0x3FUL);
- if (likely(ret >= 0 || ((int64_t)T0 & ((1 << T1) - 1)) == 0)) {
- xer_ca = 0;
+ if (likely(!(shift & 0x40))) {
+ if (likely((uint64_t)shift != 0)) {
+ shift &= 0x3f;
+ ret = (int64_t)value >> shift;
+ if (likely(ret >= 0 || (value & ((1 << shift) - 1)) == 0)) {
+ env->xer &= ~(1 << XER_CA);
} else {
- xer_ca = 1;
+ env->xer |= (1 << XER_CA);
}
} else {
- ret = T0;
- xer_ca = 0;
+ ret = (int64_t)value;
+ env->xer &= ~(1 << XER_CA);
}
} else {
- ret = (-1) * ((uint64_t)T0 >> 63);
- if (likely(ret >= 0 || ((uint64_t)T0 & ~0x8000000000000000ULL) == 0)) {
- xer_ca = 0;
+ ret = (int64_t)value >> 63;
+ if (ret) {
+ env->xer |= (1 << XER_CA);
} else {
- xer_ca = 1;
+ env->xer &= ~(1 << XER_CA);
}
}
- T0 = ret;
+ return ret;
}
#endif
-static always_inline int popcnt (uint32_t val)
-{
- int i;
-
- for (i = 0; val != 0;)
- val = val ^ (val - 1);
-
- return i;
-}
-
-void do_popcntb (void)
+target_ulong helper_popcntb (target_ulong val)
{
- uint32_t ret;
- int i;
-
- ret = 0;
- for (i = 0; i < 32; i += 8)
- ret |= popcnt((T0 >> i) & 0xFF) << i;
- T0 = ret;
+ val = (val & 0x55555555) + ((val >> 1) & 0x55555555);
+ val = (val & 0x33333333) + ((val >> 2) & 0x33333333);
+ val = (val & 0x0f0f0f0f) + ((val >> 4) & 0x0f0f0f0f);
+ return val;
}
#if defined(TARGET_PPC64)
-void do_popcntb_64 (void)
+target_ulong helper_popcntb_64 (target_ulong val)
{
- uint64_t ret;
- int i;
-
- ret = 0;
- for (i = 0; i < 64; i += 8)
- ret |= popcnt((T0 >> i) & 0xFF) << i;
- T0 = ret;
+ val = (val & 0x5555555555555555ULL) + ((val >> 1) & 0x5555555555555555ULL);
+ val = (val & 0x3333333333333333ULL) + ((val >> 2) & 0x3333333333333333ULL);
+ val = (val & 0x0f0f0f0f0f0f0f0fULL) + ((val >> 4) & 0x0f0f0f0f0f0f0f0fULL);
+ return val;
}
#endif
/*****************************************************************************/
/* Floating point operations helpers */
-void do_fctiw (void)
-{
- union {
- double d;
- uint64_t i;
- } p;
-
- p.i = float64_to_int32(FT0, &env->fp_status);
-#if USE_PRECISE_EMULATION
- /* XXX: higher bits are not supposed to be significant.
- * to make tests easier, return the same as a real PowerPC 750 (aka G3)
- */
- p.i |= 0xFFF80000ULL << 32;
-#endif
- FT0 = p.d;
-}
-
-void do_fctiwz (void)
-{
- union {
- double d;
- uint64_t i;
- } p;
-
- p.i = float64_to_int32_round_to_zero(FT0, &env->fp_status);
-#if USE_PRECISE_EMULATION
- /* XXX: higher bits are not supposed to be significant.
- * to make tests easier, return the same as a real PowerPC 750 (aka G3)
- */
- p.i |= 0xFFF80000ULL << 32;
-#endif
- FT0 = p.d;
-}
-
-#if defined(TARGET_PPC64)
-void do_fcfid (void)
-{
- union {
- double d;
- uint64_t i;
- } p;
-
- p.d = FT0;
- FT0 = int64_to_float64(p.i, &env->fp_status);
-}
-
-void do_fctid (void)
+uint64_t helper_float32_to_float64(uint32_t arg)
{
- union {
- double d;
- uint64_t i;
- } p;
-
- p.i = float64_to_int64(FT0, &env->fp_status);
- FT0 = p.d;
+ CPU_FloatU f;
+ CPU_DoubleU d;
+ f.l = arg;
+ d.d = float32_to_float64(f.f, &env->fp_status);
+ return d.ll;
}
-void do_fctidz (void)
+uint32_t helper_float64_to_float32(uint64_t arg)
{
- union {
- double d;
- uint64_t i;
- } p;
-
- p.i = float64_to_int64_round_to_zero(FT0, &env->fp_status);
- FT0 = p.d;
+ CPU_FloatU f;
+ CPU_DoubleU d;
+ d.ll = arg;
+ f.f = float64_to_float32(d.d, &env->fp_status);
+ return f.l;
}
-#endif
-
-static always_inline void do_fri (int rounding_mode)
+static always_inline int isden (float64 d)
{
- int curmode;
+ CPU_DoubleU u;
- curmode = env->fp_status.float_rounding_mode;
- set_float_rounding_mode(rounding_mode, &env->fp_status);
- FT0 = float64_round_to_int(FT0, &env->fp_status);
- set_float_rounding_mode(curmode, &env->fp_status);
-}
+ u.d = d;
-void do_frin (void)
-{
- do_fri(float_round_nearest_even);
+ return ((u.ll >> 52) & 0x7FF) == 0;
}
-void do_friz (void)
+uint32_t helper_compute_fprf (uint64_t arg, uint32_t set_fprf)
{
- do_fri(float_round_to_zero);
+ CPU_DoubleU farg;
+ int isneg;
+ int ret;
+ farg.ll = arg;
+ isneg = float64_is_neg(farg.d);
+ if (unlikely(float64_is_nan(farg.d))) {
+ if (float64_is_signaling_nan(farg.d)) {
+ /* Signaling NaN: flags are undefined */
+ ret = 0x00;
+ } else {
+ /* Quiet NaN */
+ ret = 0x11;
+ }
+ } else if (unlikely(float64_is_infinity(farg.d))) {
+ /* +/- infinity */
+ if (isneg)
+ ret = 0x09;
+ else
+ ret = 0x05;
+ } else {
+ if (float64_is_zero(farg.d)) {
+ /* +/- zero */
+ if (isneg)
+ ret = 0x12;
+ else
+ ret = 0x02;
+ } else {
+ if (isden(farg.d)) {
+ /* Denormalized numbers */
+ ret = 0x10;
+ } else {
+ /* Normalized numbers */
+ ret = 0x00;
+ }
+ if (isneg) {
+ ret |= 0x08;
+ } else {
+ ret |= 0x04;
+ }
+ }
+ }
+ if (set_fprf) {
+ /* We update FPSCR_FPRF */
+ env->fpscr &= ~(0x1F << FPSCR_FPRF);
+ env->fpscr |= ret << FPSCR_FPRF;
+ }
+ /* We just need fpcc to update Rc1 */
+ return ret & 0xF;
+}
+
+/* Floating-point invalid operations exception */
+static always_inline uint64_t fload_invalid_op_excp (int op)
+{
+ uint64_t ret = 0;
+ int ve;
+
+ ve = fpscr_ve;
+ switch (op) {
+ case POWERPC_EXCP_FP_VXSNAN:
+ env->fpscr |= 1 << FPSCR_VXSNAN;
+ break;
+ case POWERPC_EXCP_FP_VXSOFT:
+ env->fpscr |= 1 << FPSCR_VXSOFT;
+ break;
+ case POWERPC_EXCP_FP_VXISI:
+ /* Magnitude subtraction of infinities */
+ env->fpscr |= 1 << FPSCR_VXISI;
+ goto update_arith;
+ case POWERPC_EXCP_FP_VXIDI:
+ /* Division of infinity by infinity */
+ env->fpscr |= 1 << FPSCR_VXIDI;
+ goto update_arith;
+ case POWERPC_EXCP_FP_VXZDZ:
+ /* Division of zero by zero */
+ env->fpscr |= 1 << FPSCR_VXZDZ;
+ goto update_arith;
+ case POWERPC_EXCP_FP_VXIMZ:
+ /* Multiplication of zero by infinity */
+ env->fpscr |= 1 << FPSCR_VXIMZ;
+ goto update_arith;
+ case POWERPC_EXCP_FP_VXVC:
+ /* Ordered comparison of NaN */
+ env->fpscr |= 1 << FPSCR_VXVC;
+ env->fpscr &= ~(0xF << FPSCR_FPCC);
+ env->fpscr |= 0x11 << FPSCR_FPCC;
+ /* We must update the target FPR before raising the exception */
+ if (ve != 0) {
+ env->exception_index = POWERPC_EXCP_PROGRAM;
+ env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_VXVC;
+ /* Update the floating-point enabled exception summary */
+ env->fpscr |= 1 << FPSCR_FEX;
+ /* Exception is differed */
+ ve = 0;
+ }
+ break;
+ case POWERPC_EXCP_FP_VXSQRT:
+ /* Square root of a negative number */
+ env->fpscr |= 1 << FPSCR_VXSQRT;
+ update_arith:
+ env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
+ if (ve == 0) {
+ /* Set the result to quiet NaN */
+ ret = 0xFFF8000000000000ULL;
+ env->fpscr &= ~(0xF << FPSCR_FPCC);
+ env->fpscr |= 0x11 << FPSCR_FPCC;
+ }
+ break;
+ case POWERPC_EXCP_FP_VXCVI:
+ /* Invalid conversion */
+ env->fpscr |= 1 << FPSCR_VXCVI;
+ env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
+ if (ve == 0) {
+ /* Set the result to quiet NaN */
+ ret = 0xFFF8000000000000ULL;
+ env->fpscr &= ~(0xF << FPSCR_FPCC);
+ env->fpscr |= 0x11 << FPSCR_FPCC;
+ }
+ break;
+ }
+ /* Update the floating-point invalid operation summary */
+ env->fpscr |= 1 << FPSCR_VX;
+ /* Update the floating-point exception summary */
+ env->fpscr |= 1 << FPSCR_FX;
+ if (ve != 0) {
+ /* Update the floating-point enabled exception summary */
+ env->fpscr |= 1 << FPSCR_FEX;
+ if (msr_fe0 != 0 || msr_fe1 != 0)
+ helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_FP | op);
+ }
+ return ret;
+}
+
+static always_inline void float_zero_divide_excp (void)
+{
+ env->fpscr |= 1 << FPSCR_ZX;
+ env->fpscr &= ~((1 << FPSCR_FR) | (1 << FPSCR_FI));
+ /* Update the floating-point exception summary */
+ env->fpscr |= 1 << FPSCR_FX;
+ if (fpscr_ze != 0) {
+ /* Update the floating-point enabled exception summary */
+ env->fpscr |= 1 << FPSCR_FEX;
+ if (msr_fe0 != 0 || msr_fe1 != 0) {
+ helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
+ POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX);
+ }
+ }
}
-void do_frip (void)
+static always_inline void float_overflow_excp (void)
{
- do_fri(float_round_up);
+ env->fpscr |= 1 << FPSCR_OX;
+ /* Update the floating-point exception summary */
+ env->fpscr |= 1 << FPSCR_FX;
+ if (fpscr_oe != 0) {
+ /* XXX: should adjust the result */
+ /* Update the floating-point enabled exception summary */
+ env->fpscr |= 1 << FPSCR_FEX;
+ /* We must update the target FPR before raising the exception */
+ env->exception_index = POWERPC_EXCP_PROGRAM;
+ env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
+ } else {
+ env->fpscr |= 1 << FPSCR_XX;
+ env->fpscr |= 1 << FPSCR_FI;
+ }
}
-void do_frim (void)
+static always_inline void float_underflow_excp (void)
{
- do_fri(float_round_down);
+ env->fpscr |= 1 << FPSCR_UX;
+ /* Update the floating-point exception summary */
+ env->fpscr |= 1 << FPSCR_FX;
+ if (fpscr_ue != 0) {
+ /* XXX: should adjust the result */
+ /* Update the floating-point enabled exception summary */
+ env->fpscr |= 1 << FPSCR_FEX;
+ /* We must update the target FPR before raising the exception */
+ env->exception_index = POWERPC_EXCP_PROGRAM;
+ env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
+ }
}
-#if USE_PRECISE_EMULATION
-void do_fmadd (void)
+static always_inline void float_inexact_excp (void)
{
-#ifdef FLOAT128
- float128 ft0_128, ft1_128;
-
- ft0_128 = float64_to_float128(FT0, &env->fp_status);
- ft1_128 = float64_to_float128(FT1, &env->fp_status);
- ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
- ft1_128 = float64_to_float128(FT2, &env->fp_status);
- ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
- FT0 = float128_to_float64(ft0_128, &env->fp_status);
-#else
- /* This is OK on x86 hosts */
- FT0 = (FT0 * FT1) + FT2;
-#endif
+ env->fpscr |= 1 << FPSCR_XX;
+ /* Update the floating-point exception summary */
+ env->fpscr |= 1 << FPSCR_FX;
+ if (fpscr_xe != 0) {
+ /* Update the floating-point enabled exception summary */
+ env->fpscr |= 1 << FPSCR_FEX;
+ /* We must update the target FPR before raising the exception */
+ env->exception_index = POWERPC_EXCP_PROGRAM;
+ env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
+ }
}
-void do_fmsub (void)
+static always_inline void fpscr_set_rounding_mode (void)
{
-#ifdef FLOAT128
- float128 ft0_128, ft1_128;
-
- ft0_128 = float64_to_float128(FT0, &env->fp_status);
- ft1_128 = float64_to_float128(FT1, &env->fp_status);
- ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
- ft1_128 = float64_to_float128(FT2, &env->fp_status);
- ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
- FT0 = float128_to_float64(ft0_128, &env->fp_status);
-#else
- /* This is OK on x86 hosts */
- FT0 = (FT0 * FT1) - FT2;
-#endif
-}
-#endif /* USE_PRECISE_EMULATION */
+ int rnd_type;
-void do_fnmadd (void)
-{
-#if USE_PRECISE_EMULATION
-#ifdef FLOAT128
- float128 ft0_128, ft1_128;
-
- ft0_128 = float64_to_float128(FT0, &env->fp_status);
- ft1_128 = float64_to_float128(FT1, &env->fp_status);
- ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
- ft1_128 = float64_to_float128(FT2, &env->fp_status);
- ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
- FT0 = float128_to_float64(ft0_128, &env->fp_status);
-#else
- /* This is OK on x86 hosts */
- FT0 = (FT0 * FT1) + FT2;
-#endif
-#else
- FT0 = float64_mul(FT0, FT1, &env->fp_status);
- FT0 = float64_add(FT0, FT2, &env->fp_status);
-#endif
- if (likely(!isnan(FT0)))
- FT0 = float64_chs(FT0);
+ /* Set rounding mode */
+ switch (fpscr_rn) {
+ case 0:
+ /* Best approximation (round to nearest) */
+ rnd_type = float_round_nearest_even;
+ break;
+ case 1:
+ /* Smaller magnitude (round toward zero) */
+ rnd_type = float_round_to_zero;
+ break;
+ case 2:
+ /* Round toward +infinite */
+ rnd_type = float_round_up;
+ break;
+ default:
+ case 3:
+ /* Round toward -infinite */
+ rnd_type = float_round_down;
+ break;
+ }
+ set_float_rounding_mode(rnd_type, &env->fp_status);
}
-void do_fnmsub (void)
+void helper_fpscr_clrbit (uint32_t bit)
{
-#if USE_PRECISE_EMULATION
-#ifdef FLOAT128
- float128 ft0_128, ft1_128;
-
- ft0_128 = float64_to_float128(FT0, &env->fp_status);
- ft1_128 = float64_to_float128(FT1, &env->fp_status);
- ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
- ft1_128 = float64_to_float128(FT2, &env->fp_status);
- ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
- FT0 = float128_to_float64(ft0_128, &env->fp_status);
-#else
- /* This is OK on x86 hosts */
- FT0 = (FT0 * FT1) - FT2;
-#endif
-#else
- FT0 = float64_mul(FT0, FT1, &env->fp_status);
- FT0 = float64_sub(FT0, FT2, &env->fp_status);
-#endif
- if (likely(!isnan(FT0)))
- FT0 = float64_chs(FT0);
-}
+ int prev;
-void do_fsqrt (void)
-{
- FT0 = float64_sqrt(FT0, &env->fp_status);
+ prev = (env->fpscr >> bit) & 1;
+ env->fpscr &= ~(1 << bit);
+ if (prev == 1) {
+ switch (bit) {
+ case FPSCR_RN1:
+ case FPSCR_RN:
+ fpscr_set_rounding_mode();
+ break;
+ default:
+ break;
+ }
+ }
}
-void do_fre (void)
+void helper_fpscr_setbit (uint32_t bit)
{
- union {
- double d;
- uint64_t i;
- } p;
+ int prev;
- if (likely(isnormal(FT0))) {
- FT0 = float64_div(1.0, FT0, &env->fp_status);
- } else {
- p.d = FT0;
- if (p.i == 0x8000000000000000ULL) {
- p.i = 0xFFF0000000000000ULL;
- } else if (p.i == 0x0000000000000000ULL) {
- p.i = 0x7FF0000000000000ULL;
- } else if (isnan(FT0)) {
- p.i = 0x7FF8000000000000ULL;
- } else if (FT0 < 0.0) {
- p.i = 0x8000000000000000ULL;
- } else {
- p.i = 0x0000000000000000ULL;
+ prev = (env->fpscr >> bit) & 1;
+ env->fpscr |= 1 << bit;
+ if (prev == 0) {
+ switch (bit) {
+ case FPSCR_VX:
+ env->fpscr |= 1 << FPSCR_FX;
+ if (fpscr_ve)
+ goto raise_ve;
+ case FPSCR_OX:
+ env->fpscr |= 1 << FPSCR_FX;
+ if (fpscr_oe)
+ goto raise_oe;
+ break;
+ case FPSCR_UX:
+ env->fpscr |= 1 << FPSCR_FX;
+ if (fpscr_ue)
+ goto raise_ue;
+ break;
+ case FPSCR_ZX:
+ env->fpscr |= 1 << FPSCR_FX;
+ if (fpscr_ze)
+ goto raise_ze;
+ break;
+ case FPSCR_XX:
+ env->fpscr |= 1 << FPSCR_FX;
+ if (fpscr_xe)
+ goto raise_xe;
+ break;
+ case FPSCR_VXSNAN:
+ case FPSCR_VXISI:
+ case FPSCR_VXIDI:
+ case FPSCR_VXZDZ:
+ case FPSCR_VXIMZ:
+ case FPSCR_VXVC:
+ case FPSCR_VXSOFT:
+ case FPSCR_VXSQRT:
+ case FPSCR_VXCVI:
+ env->fpscr |= 1 << FPSCR_VX;
+ env->fpscr |= 1 << FPSCR_FX;
+ if (fpscr_ve != 0)
+ goto raise_ve;
+ break;
+ case FPSCR_VE:
+ if (fpscr_vx != 0) {
+ raise_ve:
+ env->error_code = POWERPC_EXCP_FP;
+ if (fpscr_vxsnan)
+ env->error_code |= POWERPC_EXCP_FP_VXSNAN;
+ if (fpscr_vxisi)
+ env->error_code |= POWERPC_EXCP_FP_VXISI;
+ if (fpscr_vxidi)
+ env->error_code |= POWERPC_EXCP_FP_VXIDI;
+ if (fpscr_vxzdz)
+ env->error_code |= POWERPC_EXCP_FP_VXZDZ;
+ if (fpscr_vximz)
+ env->error_code |= POWERPC_EXCP_FP_VXIMZ;
+ if (fpscr_vxvc)
+ env->error_code |= POWERPC_EXCP_FP_VXVC;
+ if (fpscr_vxsoft)
+ env->error_code |= POWERPC_EXCP_FP_VXSOFT;
+ if (fpscr_vxsqrt)
+ env->error_code |= POWERPC_EXCP_FP_VXSQRT;
+ if (fpscr_vxcvi)
+ env->error_code |= POWERPC_EXCP_FP_VXCVI;
+ goto raise_excp;
+ }
+ break;
+ case FPSCR_OE:
+ if (fpscr_ox != 0) {
+ raise_oe:
+ env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_OX;
+ goto raise_excp;
+ }
+ break;
+ case FPSCR_UE:
+ if (fpscr_ux != 0) {
+ raise_ue:
+ env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_UX;
+ goto raise_excp;
+ }
+ break;
+ case FPSCR_ZE:
+ if (fpscr_zx != 0) {
+ raise_ze:
+ env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_ZX;
+ goto raise_excp;
+ }
+ break;
+ case FPSCR_XE:
+ if (fpscr_xx != 0) {
+ raise_xe:
+ env->error_code = POWERPC_EXCP_FP | POWERPC_EXCP_FP_XX;
+ goto raise_excp;
+ }
+ break;
+ case FPSCR_RN1:
+ case FPSCR_RN:
+ fpscr_set_rounding_mode();
+ break;
+ default:
+ break;
+ raise_excp:
+ /* Update the floating-point enabled exception summary */
+ env->fpscr |= 1 << FPSCR_FEX;
+ /* We have to update Rc1 before raising the exception */
+ env->exception_index = POWERPC_EXCP_PROGRAM;
+ break;
}
- FT0 = p.d;
}
}
-void do_fres (void)
+void helper_store_fpscr (uint64_t arg, uint32_t mask)
{
- union {
- double d;
- uint64_t i;
- } p;
+ /*
+ * We use only the 32 LSB of the incoming fpr
+ */
+ uint32_t prev, new;
+ int i;
- if (likely(isnormal(FT0))) {
-#if USE_PRECISE_EMULATION
- FT0 = float64_div(1.0, FT0, &env->fp_status);
- FT0 = float64_to_float32(FT0, &env->fp_status);
-#else
- FT0 = float32_div(1.0, FT0, &env->fp_status);
-#endif
- } else {
- p.d = FT0;
- if (p.i == 0x8000000000000000ULL) {
- p.i = 0xFFF0000000000000ULL;
- } else if (p.i == 0x0000000000000000ULL) {
- p.i = 0x7FF0000000000000ULL;
- } else if (isnan(FT0)) {
- p.i = 0x7FF8000000000000ULL;
- } else if (FT0 < 0.0) {
- p.i = 0x8000000000000000ULL;
- } else {
- p.i = 0x0000000000000000ULL;
+ prev = env->fpscr;
+ new = (uint32_t)arg;
+ new &= ~0x60000000;
+ new |= prev & 0x60000000;
+ for (i = 0; i < 8; i++) {
+ if (mask & (1 << i)) {
+ env->fpscr &= ~(0xF << (4 * i));
+ env->fpscr |= new & (0xF << (4 * i));
}
- FT0 = p.d;
}
+ /* Update VX and FEX */
+ if (fpscr_ix != 0)
+ env->fpscr |= 1 << FPSCR_VX;
+ else
+ env->fpscr &= ~(1 << FPSCR_VX);
+ if ((fpscr_ex & fpscr_eex) != 0) {
+ env->fpscr |= 1 << FPSCR_FEX;
+ env->exception_index = POWERPC_EXCP_PROGRAM;
+ /* XXX: we should compute it properly */
+ env->error_code = POWERPC_EXCP_FP;
+ }
+ else
+ env->fpscr &= ~(1 << FPSCR_FEX);
+ fpscr_set_rounding_mode();
}
-void do_frsqrte (void)
+void helper_float_check_status (void)
{
- union {
- double d;
- uint64_t i;
- } p;
-
- if (likely(isnormal(FT0) && FT0 > 0.0)) {
- FT0 = float64_sqrt(FT0, &env->fp_status);
- FT0 = float32_div(1.0, FT0, &env->fp_status);
+#ifdef CONFIG_SOFTFLOAT
+ if (env->exception_index == POWERPC_EXCP_PROGRAM &&
+ (env->error_code & POWERPC_EXCP_FP)) {
+ /* Differred floating-point exception after target FPR update */
+ if (msr_fe0 != 0 || msr_fe1 != 0)
+ helper_raise_exception_err(env->exception_index, env->error_code);
} else {
- p.d = FT0;
- if (p.i == 0x8000000000000000ULL) {
- p.i = 0xFFF0000000000000ULL;
- } else if (p.i == 0x0000000000000000ULL) {
- p.i = 0x7FF0000000000000ULL;
- } else if (isnan(FT0)) {
- if (!(p.i & 0x0008000000000000ULL))
- p.i |= 0x000FFFFFFFFFFFFFULL;
- } else if (FT0 < 0) {
- p.i = 0x7FF8000000000000ULL;
- } else {
- p.i = 0x0000000000000000ULL;
+ int status = get_float_exception_flags(&env->fp_status);
+ if (status & float_flag_divbyzero) {
+ float_zero_divide_excp();
+ } else if (status & float_flag_overflow) {
+ float_overflow_excp();
+ } else if (status & float_flag_underflow) {
+ float_underflow_excp();
+ } else if (status & float_flag_inexact) {
+ float_inexact_excp();
}
- FT0 = p.d;
}
+#else
+ if (env->exception_index == POWERPC_EXCP_PROGRAM &&
+ (env->error_code & POWERPC_EXCP_FP)) {
+ /* Differred floating-point exception after target FPR update */
+ if (msr_fe0 != 0 || msr_fe1 != 0)
+ helper_raise_exception_err(env->exception_index, env->error_code);
+ }
+#endif
}
-void do_fsel (void)
+#ifdef CONFIG_SOFTFLOAT
+void helper_reset_fpstatus (void)
{
- if (FT0 >= 0)
- FT0 = FT1;
- else
- FT0 = FT2;
+ set_float_exception_flags(0, &env->fp_status);
}
+#endif
-void do_fcmpu (void)
+/* fadd - fadd. */
+uint64_t helper_fadd (uint64_t arg1, uint64_t arg2)
{
- if (likely(!isnan(FT0) && !isnan(FT1))) {
- if (float64_lt(FT0, FT1, &env->fp_status)) {
- T0 = 0x08UL;
- } else if (!float64_le(FT0, FT1, &env->fp_status)) {
- T0 = 0x04UL;
- } else {
- T0 = 0x02UL;
- }
+ CPU_DoubleU farg1, farg2;
+
+ farg1.ll = arg1;
+ farg2.ll = arg2;
+#if USE_PRECISE_EMULATION
+ if (unlikely(float64_is_signaling_nan(farg1.d) ||
+ float64_is_signaling_nan(farg2.d))) {
+ /* sNaN addition */
+ farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
+ } else if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2.d) &&
+ float64_is_neg(farg1.d) != float64_is_neg(farg2.d))) {
+ /* Magnitude subtraction of infinities */
+ farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
} else {
- T0 = 0x01UL;
- env->fpscr[4] |= 0x1;
- env->fpscr[6] |= 0x1;
+ farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
}
- env->fpscr[3] = T0;
+#else
+ farg1.d = float64_add(farg1.d, farg2.d, &env->fp_status);
+#endif
+ return farg1.ll;
}
-void do_fcmpo (void)
+/* fsub - fsub. */
+uint64_t helper_fsub (uint64_t arg1, uint64_t arg2)
{
- env->fpscr[4] &= ~0x1;
- if (likely(!isnan(FT0) && !isnan(FT1))) {
- if (float64_lt(FT0, FT1, &env->fp_status)) {
- T0 = 0x08UL;
- } else if (!float64_le(FT0, FT1, &env->fp_status)) {
- T0 = 0x04UL;
- } else {
- T0 = 0x02UL;
- }
- } else {
- T0 = 0x01UL;
- env->fpscr[4] |= 0x1;
- if (!float64_is_signaling_nan(FT0) || !float64_is_signaling_nan(FT1)) {
- /* Quiet NaN case */
- env->fpscr[6] |= 0x1;
- if (!(env->fpscr[1] & 0x8))
- env->fpscr[4] |= 0x8;
- } else {
- env->fpscr[4] |= 0x8;
- }
- }
- env->fpscr[3] = T0;
-}
+ CPU_DoubleU farg1, farg2;
-#if !defined (CONFIG_USER_ONLY)
-void cpu_dump_rfi (target_ulong RA, target_ulong msr);
-void do_rfi (void)
+ farg1.ll = arg1;
+ farg2.ll = arg2;
+#if USE_PRECISE_EMULATION
{
-#if defined(TARGET_PPC64)
- if (env->spr[SPR_SRR1] & (1ULL << MSR_SF)) {
- env->nip = (uint64_t)(env->spr[SPR_SRR0] & ~0x00000003);
- do_store_msr(env, (uint64_t)(env->spr[SPR_SRR1] & ~0xFFFF0000UL));
+ if (unlikely(float64_is_signaling_nan(farg1.d) ||
+ float64_is_signaling_nan(farg2.d))) {
+ /* sNaN subtraction */
+ farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
+ } else if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2.d) &&
+ float64_is_neg(farg1.d) == float64_is_neg(farg2.d))) {
+ /* Magnitude subtraction of infinities */
+ farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
} else {
- env->nip = (uint32_t)(env->spr[SPR_SRR0] & ~0x00000003);
- ppc_store_msr_32(env, (uint32_t)(env->spr[SPR_SRR1] & ~0xFFFF0000UL));
+ farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
}
+}
#else
- env->nip = (uint32_t)(env->spr[SPR_SRR0] & ~0x00000003);
- do_store_msr(env, (uint32_t)(env->spr[SPR_SRR1] & ~0xFFFF0000UL));
+ farg1.d = float64_sub(farg1.d, farg2.d, &env->fp_status);
#endif
-#if defined (DEBUG_OP)
- cpu_dump_rfi(env->nip, do_load_msr(env));
-#endif
- env->interrupt_request |= CPU_INTERRUPT_EXITTB;
+ return farg1.ll;
}
-#if defined(TARGET_PPC64)
-void do_rfid (void)
+/* fmul - fmul. */
+uint64_t helper_fmul (uint64_t arg1, uint64_t arg2)
{
- if (env->spr[SPR_SRR1] & (1ULL << MSR_SF)) {
- env->nip = (uint64_t)(env->spr[SPR_SRR0] & ~0x00000003);
- do_store_msr(env, (uint64_t)(env->spr[SPR_SRR1] & ~0xFFFF0000UL));
+ CPU_DoubleU farg1, farg2;
+
+ farg1.ll = arg1;
+ farg2.ll = arg2;
+#if USE_PRECISE_EMULATION
+ if (unlikely(float64_is_signaling_nan(farg1.d) ||
+ float64_is_signaling_nan(farg2.d))) {
+ /* sNaN multiplication */
+ farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
+ } else if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
+ (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
+ /* Multiplication of zero by infinity */
+ farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
} else {
- env->nip = (uint32_t)(env->spr[SPR_SRR0] & ~0x00000003);
- do_store_msr(env, (uint32_t)(env->spr[SPR_SRR1] & ~0xFFFF0000UL));
+ farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
}
-#if defined (DEBUG_OP)
- cpu_dump_rfi(env->nip, do_load_msr(env));
+#else
+ farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
#endif
- env->interrupt_request |= CPU_INTERRUPT_EXITTB;
+ return farg1.ll;
}
-#endif
-#if defined(TARGET_PPC64H)
-void do_hrfid (void)
+
+/* fdiv - fdiv. */
+uint64_t helper_fdiv (uint64_t arg1, uint64_t arg2)
{
- if (env->spr[SPR_HSRR1] & (1ULL << MSR_SF)) {
- env->nip = (uint64_t)(env->spr[SPR_HSRR0] & ~0x00000003);
- do_store_msr(env, (uint64_t)(env->spr[SPR_HSRR1] & ~0xFFFF0000UL));
+ CPU_DoubleU farg1, farg2;
+
+ farg1.ll = arg1;
+ farg2.ll = arg2;
+#if USE_PRECISE_EMULATION
+ if (unlikely(float64_is_signaling_nan(farg1.d) ||
+ float64_is_signaling_nan(farg2.d))) {
+ /* sNaN division */
+ farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
+ } else if (unlikely(float64_is_infinity(farg1.d) && float64_is_infinity(farg2.d))) {
+ /* Division of infinity by infinity */
+ farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIDI);
+ } else if (unlikely(float64_is_zero(farg1.d) && float64_is_zero(farg2.d))) {
+ /* Division of zero by zero */
+ farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXZDZ);
} else {
- env->nip = (uint32_t)(env->spr[SPR_HSRR0] & ~0x00000003);
- do_store_msr(env, (uint32_t)(env->spr[SPR_HSRR1] & ~0xFFFF0000UL));
+ farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
}
-#if defined (DEBUG_OP)
- cpu_dump_rfi(env->nip, do_load_msr(env));
+#else
+ farg1.d = float64_div(farg1.d, farg2.d, &env->fp_status);
#endif
- env->interrupt_request |= CPU_INTERRUPT_EXITTB;
+ return farg1.ll;
}
-#endif
-#endif
-void do_tw (int flags)
+/* fabs */
+uint64_t helper_fabs (uint64_t arg)
{
- if (!likely(!(((int32_t)T0 < (int32_t)T1 && (flags & 0x10)) ||
- ((int32_t)T0 > (int32_t)T1 && (flags & 0x08)) ||
- ((int32_t)T0 == (int32_t)T1 && (flags & 0x04)) ||
- ((uint32_t)T0 < (uint32_t)T1 && (flags & 0x02)) ||
- ((uint32_t)T0 > (uint32_t)T1 && (flags & 0x01))))) {
- do_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
- }
+ CPU_DoubleU farg;
+
+ farg.ll = arg;
+ farg.d = float64_abs(farg.d);
+ return farg.ll;
}
-#if defined(TARGET_PPC64)
-void do_td (int flags)
+/* fnabs */
+uint64_t helper_fnabs (uint64_t arg)
{
- if (!likely(!(((int64_t)T0 < (int64_t)T1 && (flags & 0x10)) ||
- ((int64_t)T0 > (int64_t)T1 && (flags & 0x08)) ||
- ((int64_t)T0 == (int64_t)T1 && (flags & 0x04)) ||
- ((uint64_t)T0 < (uint64_t)T1 && (flags & 0x02)) ||
- ((uint64_t)T0 > (uint64_t)T1 && (flags & 0x01)))))
- do_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
+ CPU_DoubleU farg;
+
+ farg.ll = arg;
+ farg.d = float64_abs(farg.d);
+ farg.d = float64_chs(farg.d);
+ return farg.ll;
}
-#endif
-/*****************************************************************************/
-/* PowerPC 601 specific instructions (POWER bridge) */
-void do_POWER_abso (void)
+/* fneg */
+uint64_t helper_fneg (uint64_t arg)
{
- if ((uint32_t)T0 == INT32_MIN) {
- T0 = INT32_MAX;
- xer_ov = 1;
- xer_so = 1;
- } else {
- T0 = -T0;
- xer_ov = 0;
- }
+ CPU_DoubleU farg;
+
+ farg.ll = arg;
+ farg.d = float64_chs(farg.d);
+ return farg.ll;
}
-void do_POWER_clcs (void)
+/* fctiw - fctiw. */
+uint64_t helper_fctiw (uint64_t arg)
{
- switch (T0) {
- case 0x0CUL:
- /* Instruction cache line size */
- T0 = env->icache_line_size;
- break;
- case 0x0DUL:
- /* Data cache line size */
- T0 = env->dcache_line_size;
- break;
- case 0x0EUL:
- /* Minimum cache line size */
- T0 = env->icache_line_size < env->dcache_line_size ?
- env->icache_line_size : env->dcache_line_size;
- break;
- case 0x0FUL:
- /* Maximum cache line size */
- T0 = env->icache_line_size > env->dcache_line_size ?
- env->icache_line_size : env->dcache_line_size;
- break;
- default:
- /* Undefined */
- break;
+ CPU_DoubleU farg;
+ farg.ll = arg;
+
+ if (unlikely(float64_is_signaling_nan(farg.d))) {
+ /* sNaN conversion */
+ farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
+ } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) {
+ /* qNan / infinity conversion */
+ farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
+ } else {
+ farg.ll = float64_to_int32(farg.d, &env->fp_status);
+#if USE_PRECISE_EMULATION
+ /* XXX: higher bits are not supposed to be significant.
+ * to make tests easier, return the same as a real PowerPC 750
+ */
+ farg.ll |= 0xFFF80000ULL << 32;
+#endif
}
+ return farg.ll;
}
-void do_POWER_div (void)
+/* fctiwz - fctiwz. */
+uint64_t helper_fctiwz (uint64_t arg)
{
- uint64_t tmp;
+ CPU_DoubleU farg;
+ farg.ll = arg;
- if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) {
- T0 = (long)((-1) * (T0 >> 31));
- env->spr[SPR_MQ] = 0;
+ if (unlikely(float64_is_signaling_nan(farg.d))) {
+ /* sNaN conversion */
+ farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
+ } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) {
+ /* qNan / infinity conversion */
+ farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
} else {
- tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
- env->spr[SPR_MQ] = tmp % T1;
- T0 = tmp / (int32_t)T1;
+ farg.ll = float64_to_int32_round_to_zero(farg.d, &env->fp_status);
+#if USE_PRECISE_EMULATION
+ /* XXX: higher bits are not supposed to be significant.
+ * to make tests easier, return the same as a real PowerPC 750
+ */
+ farg.ll |= 0xFFF80000ULL << 32;
+#endif
}
+ return farg.ll;
+}
+
+#if defined(TARGET_PPC64)
+/* fcfid - fcfid. */
+uint64_t helper_fcfid (uint64_t arg)
+{
+ CPU_DoubleU farg;
+ farg.d = int64_to_float64(arg, &env->fp_status);
+ return farg.ll;
}
-void do_POWER_divo (void)
+/* fctid - fctid. */
+uint64_t helper_fctid (uint64_t arg)
{
- int64_t tmp;
+ CPU_DoubleU farg;
+ farg.ll = arg;
- if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) {
- T0 = (long)((-1) * (T0 >> 31));
- env->spr[SPR_MQ] = 0;
- xer_ov = 1;
- xer_so = 1;
+ if (unlikely(float64_is_signaling_nan(farg.d))) {
+ /* sNaN conversion */
+ farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
+ } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) {
+ /* qNan / infinity conversion */
+ farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
} else {
- tmp = ((uint64_t)T0 << 32) | env->spr[SPR_MQ];
- env->spr[SPR_MQ] = tmp % T1;
- tmp /= (int32_t)T1;
- if (tmp > (int64_t)INT32_MAX || tmp < (int64_t)INT32_MIN) {
- xer_ov = 1;
- xer_so = 1;
- } else {
- xer_ov = 0;
- }
- T0 = tmp;
+ farg.ll = float64_to_int64(farg.d, &env->fp_status);
}
+ return farg.ll;
}
-void do_POWER_divs (void)
+/* fctidz - fctidz. */
+uint64_t helper_fctidz (uint64_t arg)
{
- if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) {
- T0 = (long)((-1) * (T0 >> 31));
- env->spr[SPR_MQ] = 0;
+ CPU_DoubleU farg;
+ farg.ll = arg;
+
+ if (unlikely(float64_is_signaling_nan(farg.d))) {
+ /* sNaN conversion */
+ farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
+ } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) {
+ /* qNan / infinity conversion */
+ farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
} else {
- env->spr[SPR_MQ] = T0 % T1;
- T0 = (int32_t)T0 / (int32_t)T1;
+ farg.ll = float64_to_int64_round_to_zero(farg.d, &env->fp_status);
}
+ return farg.ll;
}
-void do_POWER_divso (void)
+#endif
+
+static always_inline uint64_t do_fri (uint64_t arg, int rounding_mode)
{
- if (((int32_t)T0 == INT32_MIN && (int32_t)T1 == -1) || (int32_t)T1 == 0) {
- T0 = (long)((-1) * (T0 >> 31));
- env->spr[SPR_MQ] = 0;
- xer_ov = 1;
- xer_so = 1;
+ CPU_DoubleU farg;
+ farg.ll = arg;
+
+ if (unlikely(float64_is_signaling_nan(farg.d))) {
+ /* sNaN round */
+ farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN | POWERPC_EXCP_FP_VXCVI);
+ } else if (unlikely(float64_is_nan(farg.d) || float64_is_infinity(farg.d))) {
+ /* qNan / infinity round */
+ farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXCVI);
} else {
- T0 = (int32_t)T0 / (int32_t)T1;
- env->spr[SPR_MQ] = (int32_t)T0 % (int32_t)T1;
- xer_ov = 0;
+ set_float_rounding_mode(rounding_mode, &env->fp_status);
+ farg.ll = float64_round_to_int(farg.d, &env->fp_status);
+ /* Restore rounding mode from FPSCR */
+ fpscr_set_rounding_mode();
}
+ return farg.ll;
+}
+
+uint64_t helper_frin (uint64_t arg)
+{
+ return do_fri(arg, float_round_nearest_even);
+}
+
+uint64_t helper_friz (uint64_t arg)
+{
+ return do_fri(arg, float_round_to_zero);
+}
+
+uint64_t helper_frip (uint64_t arg)
+{
+ return do_fri(arg, float_round_up);
+}
+
+uint64_t helper_frim (uint64_t arg)
+{
+ return do_fri(arg, float_round_down);
}
-void do_POWER_dozo (void)
+/* fmadd - fmadd. */
+uint64_t helper_fmadd (uint64_t arg1, uint64_t arg2, uint64_t arg3)
{
- if ((int32_t)T1 > (int32_t)T0) {
- T2 = T0;
- T0 = T1 - T0;
- if (((uint32_t)(~T2) ^ (uint32_t)T1 ^ UINT32_MAX) &
- ((uint32_t)(~T2) ^ (uint32_t)T0) & (1UL << 31)) {
- xer_ov = 1;
- xer_so = 1;
+ CPU_DoubleU farg1, farg2, farg3;
+
+ farg1.ll = arg1;
+ farg2.ll = arg2;
+ farg3.ll = arg3;
+#if USE_PRECISE_EMULATION
+ if (unlikely(float64_is_signaling_nan(farg1.d) ||
+ float64_is_signaling_nan(farg2.d) ||
+ float64_is_signaling_nan(farg3.d))) {
+ /* sNaN operation */
+ farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
+ } else if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
+ (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
+ /* Multiplication of zero by infinity */
+ farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
+ } else {
+#ifdef FLOAT128
+ /* This is the way the PowerPC specification defines it */
+ float128 ft0_128, ft1_128;
+
+ ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
+ ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
+ ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
+ if (unlikely(float128_is_infinity(ft0_128) && float64_is_infinity(farg3.d) &&
+ float128_is_neg(ft0_128) != float64_is_neg(farg3.d))) {
+ /* Magnitude subtraction of infinities */
+ farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
} else {
- xer_ov = 0;
+ ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
+ ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
+ farg1.d = float128_to_float64(ft0_128, &env->fp_status);
}
- } else {
- T0 = 0;
- xer_ov = 0;
+#else
+ /* This is OK on x86 hosts */
+ farg1.d = (farg1.d * farg2.d) + farg3.d;
+#endif
}
+#else
+ farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
+ farg1.d = float64_add(farg1.d, farg3.d, &env->fp_status);
+#endif
+ return farg1.ll;
}
-void do_POWER_maskg (void)
+/* fmsub - fmsub. */
+uint64_t helper_fmsub (uint64_t arg1, uint64_t arg2, uint64_t arg3)
{
- uint32_t ret;
+ CPU_DoubleU farg1, farg2, farg3;
- if ((uint32_t)T0 == (uint32_t)(T1 + 1)) {
- ret = -1;
+ farg1.ll = arg1;
+ farg2.ll = arg2;
+ farg3.ll = arg3;
+#if USE_PRECISE_EMULATION
+ if (unlikely(float64_is_signaling_nan(farg1.d) ||
+ float64_is_signaling_nan(farg2.d) ||
+ float64_is_signaling_nan(farg3.d))) {
+ /* sNaN operation */
+ farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
+ } else if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
+ (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
+ /* Multiplication of zero by infinity */
+ farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
} else {
- ret = (((uint32_t)(-1)) >> ((uint32_t)T0)) ^
- (((uint32_t)(-1) >> ((uint32_t)T1)) >> 1);
- if ((uint32_t)T0 > (uint32_t)T1)
- ret = ~ret;
+#ifdef FLOAT128
+ /* This is the way the PowerPC specification defines it */
+ float128 ft0_128, ft1_128;
+
+ ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
+ ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
+ ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
+ if (unlikely(float128_is_infinity(ft0_128) && float64_is_infinity(farg3.d) &&
+ float128_is_neg(ft0_128) == float64_is_neg(farg3.d))) {
+ /* Magnitude subtraction of infinities */
+ farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
+ } else {
+ ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
+ ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
+ farg1.d = float128_to_float64(ft0_128, &env->fp_status);
+ }
+#else
+ /* This is OK on x86 hosts */
+ farg1.d = (farg1.d * farg2.d) - farg3.d;
+#endif
}
- T0 = ret;
+#else
+ farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
+ farg1.d = float64_sub(farg1.d, farg3.d, &env->fp_status);
+#endif
+ return farg1.ll;
}
-void do_POWER_mulo (void)
+/* fnmadd - fnmadd. */
+uint64_t helper_fnmadd (uint64_t arg1, uint64_t arg2, uint64_t arg3)
{
- uint64_t tmp;
+ CPU_DoubleU farg1, farg2, farg3;
+
+ farg1.ll = arg1;
+ farg2.ll = arg2;
+ farg3.ll = arg3;
- tmp = (uint64_t)T0 * (uint64_t)T1;
- env->spr[SPR_MQ] = tmp >> 32;
- T0 = tmp;
- if (tmp >> 32 != ((uint64_t)T0 >> 16) * ((uint64_t)T1 >> 16)) {
- xer_ov = 1;
- xer_so = 1;
+ if (unlikely(float64_is_signaling_nan(farg1.d) ||
+ float64_is_signaling_nan(farg2.d) ||
+ float64_is_signaling_nan(farg3.d))) {
+ /* sNaN operation */
+ farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
+ } else if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
+ (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
+ /* Multiplication of zero by infinity */
+ farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
} else {
- xer_ov = 0;
+#if USE_PRECISE_EMULATION
+#ifdef FLOAT128
+ /* This is the way the PowerPC specification defines it */
+ float128 ft0_128, ft1_128;
+
+ ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
+ ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
+ ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
+ if (unlikely(float128_is_infinity(ft0_128) && float64_is_infinity(farg3.d) &&
+ float128_is_neg(ft0_128) != float64_is_neg(farg3.d))) {
+ /* Magnitude subtraction of infinities */
+ farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
+ } else {
+ ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
+ ft0_128 = float128_add(ft0_128, ft1_128, &env->fp_status);
+ farg1.d = float128_to_float64(ft0_128, &env->fp_status);
+ }
+#else
+ /* This is OK on x86 hosts */
+ farg1.d = (farg1.d * farg2.d) + farg3.d;
+#endif
+#else
+ farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
+ farg1.d = float64_add(farg1.d, farg3.d, &env->fp_status);
+#endif
+ if (likely(!float64_is_nan(farg1.d)))
+ farg1.d = float64_chs(farg1.d);
}
+ return farg1.ll;
}
-#if !defined (CONFIG_USER_ONLY)
-void do_POWER_rac (void)
+/* fnmsub - fnmsub. */
+uint64_t helper_fnmsub (uint64_t arg1, uint64_t arg2, uint64_t arg3)
{
-#if 0
- mmu_ctx_t ctx;
+ CPU_DoubleU farg1, farg2, farg3;
- /* We don't have to generate many instances of this instruction,
- * as rac is supervisor only.
- */
- if (get_physical_address(env, &ctx, T0, 0, ACCESS_INT, 1) == 0)
- T0 = ctx.raddr;
+ farg1.ll = arg1;
+ farg2.ll = arg2;
+ farg3.ll = arg3;
+
+ if (unlikely(float64_is_signaling_nan(farg1.d) ||
+ float64_is_signaling_nan(farg2.d) ||
+ float64_is_signaling_nan(farg3.d))) {
+ /* sNaN operation */
+ farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
+ } else if (unlikely((float64_is_infinity(farg1.d) && float64_is_zero(farg2.d)) ||
+ (float64_is_zero(farg1.d) && float64_is_infinity(farg2.d)))) {
+ /* Multiplication of zero by infinity */
+ farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXIMZ);
+ } else {
+#if USE_PRECISE_EMULATION
+#ifdef FLOAT128
+ /* This is the way the PowerPC specification defines it */
+ float128 ft0_128, ft1_128;
+
+ ft0_128 = float64_to_float128(farg1.d, &env->fp_status);
+ ft1_128 = float64_to_float128(farg2.d, &env->fp_status);
+ ft0_128 = float128_mul(ft0_128, ft1_128, &env->fp_status);
+ if (unlikely(float128_is_infinity(ft0_128) && float64_is_infinity(farg3.d) &&
+ float128_is_neg(ft0_128) == float64_is_neg(farg3.d))) {
+ /* Magnitude subtraction of infinities */
+ farg1.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXISI);
+ } else {
+ ft1_128 = float64_to_float128(farg3.d, &env->fp_status);
+ ft0_128 = float128_sub(ft0_128, ft1_128, &env->fp_status);
+ farg1.d = float128_to_float64(ft0_128, &env->fp_status);
+ }
+#else
+ /* This is OK on x86 hosts */
+ farg1.d = (farg1.d * farg2.d) - farg3.d;
#endif
+#else
+ farg1.d = float64_mul(farg1.d, farg2.d, &env->fp_status);
+ farg1.d = float64_sub(farg1.d, farg3.d, &env->fp_status);
+#endif
+ if (likely(!float64_is_nan(farg1.d)))
+ farg1.d = float64_chs(farg1.d);
+ }
+ return farg1.ll;
}
-void do_POWER_rfsvc (void)
+/* frsp - frsp. */
+uint64_t helper_frsp (uint64_t arg)
{
- env->nip = env->lr & ~0x00000003UL;
- T0 = env->ctr & 0x0000FFFFUL;
- do_store_msr(env, T0);
-#if defined (DEBUG_OP)
- cpu_dump_rfi(env->nip, do_load_msr(env));
+ CPU_DoubleU farg;
+ float32 f32;
+ farg.ll = arg;
+
+#if USE_PRECISE_EMULATION
+ if (unlikely(float64_is_signaling_nan(farg.d))) {
+ /* sNaN square root */
+ farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
+ } else {
+ f32 = float64_to_float32(farg.d, &env->fp_status);
+ farg.d = float32_to_float64(f32, &env->fp_status);
+ }
+#else
+ f32 = float64_to_float32(farg.d, &env->fp_status);
+ farg.d = float32_to_float64(f32, &env->fp_status);
#endif
- env->interrupt_request |= CPU_INTERRUPT_EXITTB;
+ return farg.ll;
}
-/* PowerPC 601 BAT management helper */
-void do_store_601_batu (int nr)
+/* fsqrt - fsqrt. */
+uint64_t helper_fsqrt (uint64_t arg)
{
- do_store_ibatu(env, nr, (uint32_t)T0);
- env->DBAT[0][nr] = env->IBAT[0][nr];
- env->DBAT[1][nr] = env->IBAT[1][nr];
-}
-#endif
+ CPU_DoubleU farg;
+ farg.ll = arg;
-/*****************************************************************************/
-/* 602 specific instructions */
-/* mfrom is the most crazy instruction ever seen, imho ! */
-/* Real implementation uses a ROM table. Do the same */
-#define USE_MFROM_ROM_TABLE
-void do_op_602_mfrom (void)
-{
- if (likely(T0 < 602)) {
-#if defined(USE_MFROM_ROM_TABLE)
-#include "mfrom_table.c"
- T0 = mfrom_ROM_table[T0];
-#else
- double d;
- /* Extremly decomposed:
- * -T0 / 256
- * T0 = 256 * log10(10 + 1.0) + 0.5
- */
- d = T0;
- d = float64_div(d, 256, &env->fp_status);
- d = float64_chs(d);
- d = exp10(d); // XXX: use float emulation function
- d = float64_add(d, 1.0, &env->fp_status);
- d = log10(d); // XXX: use float emulation function
- d = float64_mul(d, 256, &env->fp_status);
- d = float64_add(d, 0.5, &env->fp_status);
- T0 = float64_round_to_int(d, &env->fp_status);
-#endif
+ if (unlikely(float64_is_signaling_nan(farg.d))) {
+ /* sNaN square root */
+ farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
+ } else if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) {
+ /* Square root of a negative nonzero number */
+ farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
} else {
- T0 = 0;
+ farg.d = float64_sqrt(farg.d, &env->fp_status);
}
+ return farg.ll;
}
-/*****************************************************************************/
-/* Embedded PowerPC specific helpers */
-void do_405_check_ov (void)
+/* fre - fre. */
+uint64_t helper_fre (uint64_t arg)
{
- if (likely((((uint32_t)T1 ^ (uint32_t)T2) >> 31) ||
- !(((uint32_t)T0 ^ (uint32_t)T2) >> 31))) {
- xer_ov = 0;
+ CPU_DoubleU fone, farg;
+ fone.ll = 0x3FF0000000000000ULL; /* 1.0 */
+ farg.ll = arg;
+
+ if (unlikely(float64_is_signaling_nan(farg.d))) {
+ /* sNaN reciprocal */
+ farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
} else {
- xer_ov = 1;
- xer_so = 1;
+ farg.d = float64_div(fone.d, farg.d, &env->fp_status);
}
+ return farg.d;
}
-void do_405_check_sat (void)
+/* fres - fres. */
+uint64_t helper_fres (uint64_t arg)
{
- if (!likely((((uint32_t)T1 ^ (uint32_t)T2) >> 31) ||
- !(((uint32_t)T0 ^ (uint32_t)T2) >> 31))) {
- /* Saturate result */
- if (T2 >> 31) {
- T0 = INT32_MIN;
- } else {
- T0 = INT32_MAX;
- }
+ CPU_DoubleU fone, farg;
+ float32 f32;
+ fone.ll = 0x3FF0000000000000ULL; /* 1.0 */
+ farg.ll = arg;
+
+ if (unlikely(float64_is_signaling_nan(farg.d))) {
+ /* sNaN reciprocal */
+ farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
+ } else {
+ farg.d = float64_div(fone.d, farg.d, &env->fp_status);
+ f32 = float64_to_float32(farg.d, &env->fp_status);
+ farg.d = float32_to_float64(f32, &env->fp_status);
}
+ return farg.ll;
}
-/* XXX: to be improved to check access rights when in user-mode */
-void do_load_dcr (void)
+/* frsqrte - frsqrte. */
+uint64_t helper_frsqrte (uint64_t arg)
{
- target_ulong val;
+ CPU_DoubleU fone, farg;
+ float32 f32;
+ fone.ll = 0x3FF0000000000000ULL; /* 1.0 */
+ farg.ll = arg;
- if (unlikely(env->dcr_env == NULL)) {
- if (loglevel != 0) {
- fprintf(logfile, "No DCR environment\n");
- }
- do_raise_exception_err(POWERPC_EXCP_PROGRAM,
- POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
- } else if (unlikely(ppc_dcr_read(env->dcr_env, T0, &val) != 0)) {
- if (loglevel != 0) {
- fprintf(logfile, "DCR read error %d %03x\n", (int)T0, (int)T0);
- }
- do_raise_exception_err(POWERPC_EXCP_PROGRAM,
- POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
+ if (unlikely(float64_is_signaling_nan(farg.d))) {
+ /* sNaN reciprocal square root */
+ farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
+ } else if (unlikely(float64_is_neg(farg.d) && !float64_is_zero(farg.d))) {
+ /* Reciprocal square root of a negative nonzero number */
+ farg.ll = fload_invalid_op_excp(POWERPC_EXCP_FP_VXSQRT);
} else {
- T0 = val;
+ farg.d = float64_sqrt(farg.d, &env->fp_status);
+ farg.d = float64_div(fone.d, farg.d, &env->fp_status);
+ f32 = float64_to_float32(farg.d, &env->fp_status);
+ farg.d = float32_to_float64(f32, &env->fp_status);
}
+ return farg.ll;
}
-void do_store_dcr (void)
+/* fsel - fsel. */
+uint64_t helper_fsel (uint64_t arg1, uint64_t arg2, uint64_t arg3)
{
- if (unlikely(env->dcr_env == NULL)) {
- if (loglevel != 0) {
- fprintf(logfile, "No DCR environment\n");
- }
- do_raise_exception_err(POWERPC_EXCP_PROGRAM,
- POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
- } else if (unlikely(ppc_dcr_write(env->dcr_env, T0, T1) != 0)) {
- if (loglevel != 0) {
- fprintf(logfile, "DCR write error %d %03x\n", (int)T0, (int)T0);
- }
- do_raise_exception_err(POWERPC_EXCP_PROGRAM,
- POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
- }
+ CPU_DoubleU farg1;
+
+ farg1.ll = arg1;
+
+ if ((!float64_is_neg(farg1.d) || float64_is_zero(farg1.d)) && !float64_is_nan(farg1.d))
+ return arg2;
+ else
+ return arg3;
}
-#if !defined(CONFIG_USER_ONLY)
-void do_40x_rfci (void)
+void helper_fcmpu (uint64_t arg1, uint64_t arg2, uint32_t crfD)
{
- env->nip = env->spr[SPR_40x_SRR2];
- do_store_msr(env, env->spr[SPR_40x_SRR3] & ~0xFFFF0000);
-#if defined (DEBUG_OP)
- cpu_dump_rfi(env->nip, do_load_msr(env));
-#endif
- env->interrupt_request = CPU_INTERRUPT_EXITTB;
+ CPU_DoubleU farg1, farg2;
+ uint32_t ret = 0;
+ farg1.ll = arg1;
+ farg2.ll = arg2;
+
+ if (unlikely(float64_is_nan(farg1.d) ||
+ float64_is_nan(farg2.d))) {
+ ret = 0x01UL;
+ } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
+ ret = 0x08UL;
+ } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
+ ret = 0x04UL;
+ } else {
+ ret = 0x02UL;
+ }
+
+ env->fpscr &= ~(0x0F << FPSCR_FPRF);
+ env->fpscr |= ret << FPSCR_FPRF;
+ env->crf[crfD] = ret;
+ if (unlikely(ret == 0x01UL
+ && (float64_is_signaling_nan(farg1.d) ||
+ float64_is_signaling_nan(farg2.d)))) {
+ /* sNaN comparison */
+ fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN);
+ }
}
-void do_rfci (void)
+void helper_fcmpo (uint64_t arg1, uint64_t arg2, uint32_t crfD)
{
-#if defined(TARGET_PPC64)
- if (env->spr[SPR_BOOKE_CSRR1] & (1 << MSR_CM)) {
- env->nip = (uint64_t)env->spr[SPR_BOOKE_CSRR0];
- } else
-#endif
- {
- env->nip = (uint32_t)env->spr[SPR_BOOKE_CSRR0];
+ CPU_DoubleU farg1, farg2;
+ uint32_t ret = 0;
+ farg1.ll = arg1;
+ farg2.ll = arg2;
+
+ if (unlikely(float64_is_nan(farg1.d) ||
+ float64_is_nan(farg2.d))) {
+ ret = 0x01UL;
+ } else if (float64_lt(farg1.d, farg2.d, &env->fp_status)) {
+ ret = 0x08UL;
+ } else if (!float64_le(farg1.d, farg2.d, &env->fp_status)) {
+ ret = 0x04UL;
+ } else {
+ ret = 0x02UL;
+ }
+
+ env->fpscr &= ~(0x0F << FPSCR_FPRF);
+ env->fpscr |= ret << FPSCR_FPRF;
+ env->crf[crfD] = ret;
+ if (unlikely (ret == 0x01UL)) {
+ if (float64_is_signaling_nan(farg1.d) ||
+ float64_is_signaling_nan(farg2.d)) {
+ /* sNaN comparison */
+ fload_invalid_op_excp(POWERPC_EXCP_FP_VXSNAN |
+ POWERPC_EXCP_FP_VXVC);
+ } else {
+ /* qNaN comparison */
+ fload_invalid_op_excp(POWERPC_EXCP_FP_VXVC);
+ }
}
- do_store_msr(env, (uint32_t)env->spr[SPR_BOOKE_CSRR1] & ~0x3FFF0000);
-#if defined (DEBUG_OP)
- cpu_dump_rfi(env->nip, do_load_msr(env));
-#endif
- env->interrupt_request = CPU_INTERRUPT_EXITTB;
}
-void do_rfdi (void)
+#if !defined (CONFIG_USER_ONLY)
+void helper_store_msr (target_ulong val)
{
-#if defined(TARGET_PPC64)
- if (env->spr[SPR_BOOKE_DSRR1] & (1 << MSR_CM)) {
- env->nip = (uint64_t)env->spr[SPR_BOOKE_DSRR0];
- } else
-#endif
- {
- env->nip = (uint32_t)env->spr[SPR_BOOKE_DSRR0];
+ val = hreg_store_msr(env, val, 0);
+ if (val != 0) {
+ env->interrupt_request |= CPU_INTERRUPT_EXITTB;
+ helper_raise_exception(val);
}
- do_store_msr(env, (uint32_t)env->spr[SPR_BOOKE_DSRR1] & ~0x3FFF0000);
-#if defined (DEBUG_OP)
- cpu_dump_rfi(env->nip, do_load_msr(env));
-#endif
- env->interrupt_request = CPU_INTERRUPT_EXITTB;
}
-void do_rfmci (void)
+static always_inline void do_rfi (target_ulong nip, target_ulong msr,
+ target_ulong msrm, int keep_msrh)
{
#if defined(TARGET_PPC64)
- if (env->spr[SPR_BOOKE_MCSRR1] & (1 << MSR_CM)) {
- env->nip = (uint64_t)env->spr[SPR_BOOKE_MCSRR0];
- } else
-#endif
- {
- env->nip = (uint32_t)env->spr[SPR_BOOKE_MCSRR0];
+ if (msr & (1ULL << MSR_SF)) {
+ nip = (uint64_t)nip;
+ msr &= (uint64_t)msrm;
+ } else {
+ nip = (uint32_t)nip;
+ msr = (uint32_t)(msr & msrm);
+ if (keep_msrh)
+ msr |= env->msr & ~((uint64_t)0xFFFFFFFF);
}
- do_store_msr(env, (uint32_t)env->spr[SPR_BOOKE_MCSRR1] & ~0x3FFF0000);
+#else
+ nip = (uint32_t)nip;
+ msr &= (uint32_t)msrm;
+#endif
+ /* XXX: beware: this is false if VLE is supported */
+ env->nip = nip & ~((target_ulong)0x00000003);
+ hreg_store_msr(env, msr, 1);
#if defined (DEBUG_OP)
- cpu_dump_rfi(env->nip, do_load_msr(env));
+ cpu_dump_rfi(env->nip, env->msr);
#endif
- env->interrupt_request = CPU_INTERRUPT_EXITTB;
+ /* No need to raise an exception here,
+ * as rfi is always the last insn of a TB
+ */
+ env->interrupt_request |= CPU_INTERRUPT_EXITTB;
}
-void do_load_403_pb (int num)
+void helper_rfi (void)
{
- T0 = env->pb[num];
+ do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
+ ~((target_ulong)0xFFFF0000), 1);
}
-void do_store_403_pb (int num)
+#if defined(TARGET_PPC64)
+void helper_rfid (void)
{
- if (likely(env->pb[num] != T0)) {
- env->pb[num] = T0;
- /* Should be optimized */
- tlb_flush(env, 1);
- }
+ do_rfi(env->spr[SPR_SRR0], env->spr[SPR_SRR1],
+ ~((target_ulong)0xFFFF0000), 0);
}
-#endif
-/* 440 specific */
-void do_440_dlmzb (void)
+void helper_hrfid (void)
{
- target_ulong mask;
- int i;
+ do_rfi(env->spr[SPR_HSRR0], env->spr[SPR_HSRR1],
+ ~((target_ulong)0xFFFF0000), 0);
+}
+#endif
+#endif
- i = 1;
- for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
- if ((T0 & mask) == 0)
- goto done;
- i++;
- }
- for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
- if ((T1 & mask) == 0)
- break;
- i++;
+void helper_tw (target_ulong arg1, target_ulong arg2, uint32_t flags)
+{
+ if (!likely(!(((int32_t)arg1 < (int32_t)arg2 && (flags & 0x10)) ||
+ ((int32_t)arg1 > (int32_t)arg2 && (flags & 0x08)) ||
+ ((int32_t)arg1 == (int32_t)arg2 && (flags & 0x04)) ||
+ ((uint32_t)arg1 < (uint32_t)arg2 && (flags & 0x02)) ||
+ ((uint32_t)arg1 > (uint32_t)arg2 && (flags & 0x01))))) {
+ helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
}
- done:
- T0 = i;
}
-#if defined(TARGET_PPCEMB)
-/* SPE extension helpers */
-/* Use a table to make this quicker */
-static uint8_t hbrev[16] = {
- 0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE,
- 0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF,
-};
-
-static always_inline uint8_t byte_reverse (uint8_t val)
+#if defined(TARGET_PPC64)
+void helper_td (target_ulong arg1, target_ulong arg2, uint32_t flags)
{
- return hbrev[val >> 4] | (hbrev[val & 0xF] << 4);
+ if (!likely(!(((int64_t)arg1 < (int64_t)arg2 && (flags & 0x10)) ||
+ ((int64_t)arg1 > (int64_t)arg2 && (flags & 0x08)) ||
+ ((int64_t)arg1 == (int64_t)arg2 && (flags & 0x04)) ||
+ ((uint64_t)arg1 < (uint64_t)arg2 && (flags & 0x02)) ||
+ ((uint64_t)arg1 > (uint64_t)arg2 && (flags & 0x01)))))
+ helper_raise_exception_err(POWERPC_EXCP_PROGRAM, POWERPC_EXCP_TRAP);
}
+#endif
-static always_inline uint32_t word_reverse (uint32_t val)
+/*****************************************************************************/
+/* PowerPC 601 specific instructions (POWER bridge) */
+
+target_ulong helper_clcs (uint32_t arg)
{
- return byte_reverse(val >> 24) | (byte_reverse(val >> 16) << 8) |
- (byte_reverse(val >> 8) << 16) | (byte_reverse(val) << 24);
+ switch (arg) {
+ case 0x0CUL:
+ /* Instruction cache line size */
+ return env->icache_line_size;
+ break;
+ case 0x0DUL:
+ /* Data cache line size */
+ return env->dcache_line_size;
+ break;
+ case 0x0EUL:
+ /* Minimum cache line size */
+ return (env->icache_line_size < env->dcache_line_size) ?
+ env->icache_line_size : env->dcache_line_size;
+ break;
+ case 0x0FUL:
+ /* Maximum cache line size */
+ return (env->icache_line_size > env->dcache_line_size) ?
+ env->icache_line_size : env->dcache_line_size;
+ break;
+ default:
+ /* Undefined */
+ return 0;
+ break;
+ }
}
-#define MASKBITS 16 // Random value - to be fixed
-void do_brinc (void)
+target_ulong helper_div (target_ulong arg1, target_ulong arg2)
{
- uint32_t a, b, d, mask;
+ uint64_t tmp = (uint64_t)arg1 << 32 | env->spr[SPR_MQ];
- mask = (uint32_t)(-1UL) >> MASKBITS;
- b = T1_64 & mask;
- a = T0_64 & mask;
- d = word_reverse(1 + word_reverse(a | ~mask));
- T0_64 = (T0_64 & ~mask) | (d & mask);
+ if (((int32_t)tmp == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
+ (int32_t)arg2 == 0) {
+ env->spr[SPR_MQ] = 0;
+ return INT32_MIN;
+ } else {
+ env->spr[SPR_MQ] = tmp % arg2;
+ return tmp / (int32_t)arg2;
+ }
}
-#define DO_SPE_OP2(name) \
-void do_ev##name (void) \
-{ \
- T0_64 = ((uint64_t)_do_e##name(T0_64 >> 32, T1_64 >> 32) << 32) | \
- (uint64_t)_do_e##name(T0_64, T1_64); \
-}
+target_ulong helper_divo (target_ulong arg1, target_ulong arg2)
+{
+ uint64_t tmp = (uint64_t)arg1 << 32 | env->spr[SPR_MQ];
-#define DO_SPE_OP1(name) \
-void do_ev##name (void) \
-{ \
- T0_64 = ((uint64_t)_do_e##name(T0_64 >> 32) << 32) | \
- (uint64_t)_do_e##name(T0_64); \
+ if (((int32_t)tmp == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
+ (int32_t)arg2 == 0) {
+ env->xer |= (1 << XER_OV) | (1 << XER_SO);
+ env->spr[SPR_MQ] = 0;
+ return INT32_MIN;
+ } else {
+ env->spr[SPR_MQ] = tmp % arg2;
+ tmp /= (int32_t)arg2;
+ if ((int32_t)tmp != tmp) {
+ env->xer |= (1 << XER_OV) | (1 << XER_SO);
+ } else {
+ env->xer &= ~(1 << XER_OV);
+ }
+ return tmp;
+ }
}
-/* Fixed-point vector arithmetic */
-static always_inline uint32_t _do_eabs (uint32_t val)
+target_ulong helper_divs (target_ulong arg1, target_ulong arg2)
{
- if (val != 0x80000000)
- val &= ~0x80000000;
+ if (((int32_t)arg1 == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
+ (int32_t)arg2 == 0) {
+ env->spr[SPR_MQ] = 0;
+ return INT32_MIN;
+ } else {
+ env->spr[SPR_MQ] = (int32_t)arg1 % (int32_t)arg2;
+ return (int32_t)arg1 / (int32_t)arg2;
+ }
+}
- return val;
+target_ulong helper_divso (target_ulong arg1, target_ulong arg2)
+{
+ if (((int32_t)arg1 == INT32_MIN && (int32_t)arg2 == (int32_t)-1) ||
+ (int32_t)arg2 == 0) {
+ env->xer |= (1 << XER_OV) | (1 << XER_SO);
+ env->spr[SPR_MQ] = 0;
+ return INT32_MIN;
+ } else {
+ env->xer &= ~(1 << XER_OV);
+ env->spr[SPR_MQ] = (int32_t)arg1 % (int32_t)arg2;
+ return (int32_t)arg1 / (int32_t)arg2;
+ }
}
-static always_inline uint32_t _do_eaddw (uint32_t op1, uint32_t op2)
+#if !defined (CONFIG_USER_ONLY)
+target_ulong helper_rac (target_ulong addr)
{
- return op1 + op2;
+ mmu_ctx_t ctx;
+ int nb_BATs;
+ target_ulong ret = 0;
+
+ /* We don't have to generate many instances of this instruction,
+ * as rac is supervisor only.
+ */
+ /* XXX: FIX THIS: Pretend we have no BAT */
+ nb_BATs = env->nb_BATs;
+ env->nb_BATs = 0;
+ if (get_physical_address(env, &ctx, addr, 0, ACCESS_INT) == 0)
+ ret = ctx.raddr;
+ env->nb_BATs = nb_BATs;
+ return ret;
}
-static always_inline int _do_ecntlsw (uint32_t val)
+void helper_rfsvc (void)
{
- if (val & 0x80000000)
- return _do_cntlzw(~val);
- else
- return _do_cntlzw(val);
+ do_rfi(env->lr, env->ctr, 0x0000FFFF, 0);
}
+#endif
-static always_inline int _do_ecntlzw (uint32_t val)
+/*****************************************************************************/
+/* 602 specific instructions */
+/* mfrom is the most crazy instruction ever seen, imho ! */
+/* Real implementation uses a ROM table. Do the same */
+/* Extremly decomposed:
+ * -arg / 256
+ * return 256 * log10(10 + 1.0) + 0.5
+ */
+#if !defined (CONFIG_USER_ONLY)
+target_ulong helper_602_mfrom (target_ulong arg)
{
- return _do_cntlzw(val);
+ if (likely(arg < 602)) {
+#include "mfrom_table.c"
+ return mfrom_ROM_table[arg];
+ } else {
+ return 0;
+ }
}
+#endif
+
+/*****************************************************************************/
+/* Embedded PowerPC specific helpers */
-static always_inline uint32_t _do_eneg (uint32_t val)
+/* XXX: to be improved to check access rights when in user-mode */
+target_ulong helper_load_dcr (target_ulong dcrn)
{
- if (val != 0x80000000)
- val ^= 0x80000000;
+ target_ulong val = 0;
+ if (unlikely(env->dcr_env == NULL)) {
+ if (loglevel != 0) {
+ fprintf(logfile, "No DCR environment\n");
+ }
+ helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
+ POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
+ } else if (unlikely(ppc_dcr_read(env->dcr_env, dcrn, &val) != 0)) {
+ if (loglevel != 0) {
+ fprintf(logfile, "DCR read error %d %03x\n", (int)dcrn, (int)dcrn);
+ }
+ helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
+ POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
+ }
return val;
}
-static always_inline uint32_t _do_erlw (uint32_t op1, uint32_t op2)
+void helper_store_dcr (target_ulong dcrn, target_ulong val)
{
- return rotl32(op1, op2);
-}
-
-static always_inline uint32_t _do_erndw (uint32_t val)
-{
- return (val + 0x000080000000) & 0xFFFF0000;
+ if (unlikely(env->dcr_env == NULL)) {
+ if (loglevel != 0) {
+ fprintf(logfile, "No DCR environment\n");
+ }
+ helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
+ POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL);
+ } else if (unlikely(ppc_dcr_write(env->dcr_env, dcrn, val) != 0)) {
+ if (loglevel != 0) {
+ fprintf(logfile, "DCR write error %d %03x\n", (int)dcrn, (int)dcrn);
+ }
+ helper_raise_exception_err(POWERPC_EXCP_PROGRAM,
+ POWERPC_EXCP_INVAL | POWERPC_EXCP_PRIV_REG);
+ }
}
-static always_inline uint32_t _do_eslw (uint32_t op1, uint32_t op2)
+#if !defined(CONFIG_USER_ONLY)
+void helper_40x_rfci (void)
{
- /* No error here: 6 bits are used */
- return op1 << (op2 & 0x3F);
+ do_rfi(env->spr[SPR_40x_SRR2], env->spr[SPR_40x_SRR3],
+ ~((target_ulong)0xFFFF0000), 0);
}
-static always_inline int32_t _do_esrws (int32_t op1, uint32_t op2)
+void helper_rfci (void)
{
- /* No error here: 6 bits are used */
- return op1 >> (op2 & 0x3F);
+ do_rfi(env->spr[SPR_BOOKE_CSRR0], SPR_BOOKE_CSRR1,
+ ~((target_ulong)0x3FFF0000), 0);
}
-static always_inline uint32_t _do_esrwu (uint32_t op1, uint32_t op2)
+void helper_rfdi (void)
{
- /* No error here: 6 bits are used */
- return op1 >> (op2 & 0x3F);
+ do_rfi(env->spr[SPR_BOOKE_DSRR0], SPR_BOOKE_DSRR1,
+ ~((target_ulong)0x3FFF0000), 0);
}
-static always_inline uint32_t _do_esubfw (uint32_t op1, uint32_t op2)
+void helper_rfmci (void)
{
- return op2 - op1;
+ do_rfi(env->spr[SPR_BOOKE_MCSRR0], SPR_BOOKE_MCSRR1,
+ ~((target_ulong)0x3FFF0000), 0);
}
+#endif
-/* evabs */
-DO_SPE_OP1(abs);
-/* evaddw */
-DO_SPE_OP2(addw);
-/* evcntlsw */
-DO_SPE_OP1(cntlsw);
-/* evcntlzw */
-DO_SPE_OP1(cntlzw);
-/* evneg */
-DO_SPE_OP1(neg);
-/* evrlw */
-DO_SPE_OP2(rlw);
-/* evrnd */
-DO_SPE_OP1(rndw);
-/* evslw */
-DO_SPE_OP2(slw);
-/* evsrws */
-DO_SPE_OP2(srws);
-/* evsrwu */
-DO_SPE_OP2(srwu);
-/* evsubfw */
-DO_SPE_OP2(subfw);
-
-/* evsel is a little bit more complicated... */
-static always_inline uint32_t _do_esel (uint32_t op1, uint32_t op2, int n)
+/* 440 specific */
+target_ulong helper_dlmzb (target_ulong high, target_ulong low, uint32_t update_Rc)
{
- if (n)
- return op1;
- else
- return op2;
-}
+ target_ulong mask;
+ int i;
-void do_evsel (void)
-{
- T0_64 = ((uint64_t)_do_esel(T0_64 >> 32, T1_64 >> 32, T0 >> 3) << 32) |
- (uint64_t)_do_esel(T0_64, T1_64, (T0 >> 2) & 1);
+ i = 1;
+ for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
+ if ((high & mask) == 0) {
+ if (update_Rc) {
+ env->crf[0] = 0x4;
+ }
+ goto done;
+ }
+ i++;
+ }
+ for (mask = 0xFF000000; mask != 0; mask = mask >> 8) {
+ if ((low & mask) == 0) {
+ if (update_Rc) {
+ env->crf[0] = 0x8;
+ }
+ goto done;
+ }
+ i++;
+ }
+ if (update_Rc) {
+ env->crf[0] = 0x2;
+ }
+ done:
+ env->xer = (env->xer & ~0x7F) | i;
+ if (update_Rc) {
+ env->crf[0] |= xer_so;
+ }
+ return i;
}
-/* Fixed-point vector comparisons */
-#define DO_SPE_CMP(name) \
-void do_ev##name (void) \
-{ \
- T0 = _do_evcmp_merge((uint64_t)_do_e##name(T0_64 >> 32, \
- T1_64 >> 32) << 32, \
- _do_e##name(T0_64, T1_64)); \
-}
+/*****************************************************************************/
+/* SPE extension helpers */
+/* Use a table to make this quicker */
+static uint8_t hbrev[16] = {
+ 0x0, 0x8, 0x4, 0xC, 0x2, 0xA, 0x6, 0xE,
+ 0x1, 0x9, 0x5, 0xD, 0x3, 0xB, 0x7, 0xF,
+};
-static always_inline uint32_t _do_evcmp_merge (int t0, int t1)
-{
- return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
-}
-static always_inline int _do_ecmpeq (uint32_t op1, uint32_t op2)
+static always_inline uint8_t byte_reverse (uint8_t val)
{
- return op1 == op2 ? 1 : 0;
+ return hbrev[val >> 4] | (hbrev[val & 0xF] << 4);
}
-static always_inline int _do_ecmpgts (int32_t op1, int32_t op2)
+static always_inline uint32_t word_reverse (uint32_t val)
{
- return op1 > op2 ? 1 : 0;
+ return byte_reverse(val >> 24) | (byte_reverse(val >> 16) << 8) |
+ (byte_reverse(val >> 8) << 16) | (byte_reverse(val) << 24);
}
-static always_inline int _do_ecmpgtu (uint32_t op1, uint32_t op2)
+#define MASKBITS 16 // Random value - to be fixed (implementation dependant)
+target_ulong helper_brinc (target_ulong arg1, target_ulong arg2)
{
- return op1 > op2 ? 1 : 0;
+ uint32_t a, b, d, mask;
+
+ mask = UINT32_MAX >> (32 - MASKBITS);
+ a = arg1 & mask;
+ b = arg2 & mask;
+ d = word_reverse(1 + word_reverse(a | ~b));
+ return (arg1 & ~mask) | (d & b);
}
-static always_inline int _do_ecmplts (int32_t op1, int32_t op2)
+uint32_t helper_cntlsw32 (uint32_t val)
{
- return op1 < op2 ? 1 : 0;
+ if (val & 0x80000000)
+ return clz32(~val);
+ else
+ return clz32(val);
}
-static always_inline int _do_ecmpltu (uint32_t op1, uint32_t op2)
+uint32_t helper_cntlzw32 (uint32_t val)
{
- return op1 < op2 ? 1 : 0;
+ return clz32(val);
}
-/* evcmpeq */
-DO_SPE_CMP(cmpeq);
-/* evcmpgts */
-DO_SPE_CMP(cmpgts);
-/* evcmpgtu */
-DO_SPE_CMP(cmpgtu);
-/* evcmplts */
-DO_SPE_CMP(cmplts);
-/* evcmpltu */
-DO_SPE_CMP(cmpltu);
-
-/* Single precision floating-point conversions from/to integer */
-static always_inline uint32_t _do_efscfsi (int32_t val)
+/* Single-precision floating-point conversions */
+static always_inline uint32_t efscfsi (uint32_t val)
{
- union {
- uint32_t u;
- float32 f;
- } u;
+ CPU_FloatU u;
u.f = int32_to_float32(val, &env->spe_status);
- return u.u;
+ return u.l;
}
-static always_inline uint32_t _do_efscfui (uint32_t val)
+static always_inline uint32_t efscfui (uint32_t val)
{
- union {
- uint32_t u;
- float32 f;
- } u;
+ CPU_FloatU u;
u.f = uint32_to_float32(val, &env->spe_status);
- return u.u;
+ return u.l;
}
-static always_inline int32_t _do_efsctsi (uint32_t val)
+static always_inline int32_t efsctsi (uint32_t val)
{
- union {
- int32_t u;
- float32 f;
- } u;
+ CPU_FloatU u;
- u.u = val;
+ u.l = val;
/* NaN are not treated the same way IEEE 754 does */
- if (unlikely(isnan(u.f)))
+ if (unlikely(float32_is_nan(u.f)))
return 0;
return float32_to_int32(u.f, &env->spe_status);
}
-static always_inline uint32_t _do_efsctui (uint32_t val)
+static always_inline uint32_t efsctui (uint32_t val)
{
- union {
- int32_t u;
- float32 f;
- } u;
+ CPU_FloatU u;
- u.u = val;
+ u.l = val;
/* NaN are not treated the same way IEEE 754 does */
- if (unlikely(isnan(u.f)))
+ if (unlikely(float32_is_nan(u.f)))
return 0;
return float32_to_uint32(u.f, &env->spe_status);
}
-static always_inline int32_t _do_efsctsiz (uint32_t val)
+static always_inline uint32_t efsctsiz (uint32_t val)
{
- union {
- int32_t u;
- float32 f;
- } u;
+ CPU_FloatU u;
- u.u = val;
+ u.l = val;
/* NaN are not treated the same way IEEE 754 does */
- if (unlikely(isnan(u.f)))
+ if (unlikely(float32_is_nan(u.f)))
return 0;
return float32_to_int32_round_to_zero(u.f, &env->spe_status);
}
-static always_inline uint32_t _do_efsctuiz (uint32_t val)
+static always_inline uint32_t efsctuiz (uint32_t val)
{
- union {
- int32_t u;
- float32 f;
- } u;
+ CPU_FloatU u;
- u.u = val;
+ u.l = val;
/* NaN are not treated the same way IEEE 754 does */
- if (unlikely(isnan(u.f)))
+ if (unlikely(float32_is_nan(u.f)))
return 0;
return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
}
-void do_efscfsi (void)
-{
- T0_64 = _do_efscfsi(T0_64);
-}
-
-void do_efscfui (void)
-{
- T0_64 = _do_efscfui(T0_64);
-}
-
-void do_efsctsi (void)
+static always_inline uint32_t efscfsf (uint32_t val)
{
- T0_64 = _do_efsctsi(T0_64);
-}
-
-void do_efsctui (void)
-{
- T0_64 = _do_efsctui(T0_64);
-}
-
-void do_efsctsiz (void)
-{
- T0_64 = _do_efsctsiz(T0_64);
-}
-
-void do_efsctuiz (void)
-{
- T0_64 = _do_efsctuiz(T0_64);
-}
-
-/* Single precision floating-point conversion to/from fractional */
-static always_inline uint32_t _do_efscfsf (uint32_t val)
-{
- union {
- uint32_t u;
- float32 f;
- } u;
+ CPU_FloatU u;
float32 tmp;
u.f = int32_to_float32(val, &env->spe_status);
tmp = int64_to_float32(1ULL << 32, &env->spe_status);
u.f = float32_div(u.f, tmp, &env->spe_status);
- return u.u;
+ return u.l;
}
-static always_inline uint32_t _do_efscfuf (uint32_t val)
+static always_inline uint32_t efscfuf (uint32_t val)
{
- union {
- uint32_t u;
- float32 f;
- } u;
+ CPU_FloatU u;
float32 tmp;
u.f = uint32_to_float32(val, &env->spe_status);
tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
u.f = float32_div(u.f, tmp, &env->spe_status);
- return u.u;
+ return u.l;
}
-static always_inline int32_t _do_efsctsf (uint32_t val)
+static always_inline uint32_t efsctsf (uint32_t val)
{
- union {
- int32_t u;
- float32 f;
- } u;
+ CPU_FloatU u;
float32 tmp;
- u.u = val;
+ u.l = val;
/* NaN are not treated the same way IEEE 754 does */
- if (unlikely(isnan(u.f)))
+ if (unlikely(float32_is_nan(u.f)))
return 0;
tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
u.f = float32_mul(u.f, tmp, &env->spe_status);
return float32_to_int32(u.f, &env->spe_status);
}
-static always_inline uint32_t _do_efsctuf (uint32_t val)
+static always_inline uint32_t efsctuf (uint32_t val)
{
- union {
- int32_t u;
- float32 f;
- } u;
+ CPU_FloatU u;
float32 tmp;
- u.u = val;
+ u.l = val;
/* NaN are not treated the same way IEEE 754 does */
- if (unlikely(isnan(u.f)))
+ if (unlikely(float32_is_nan(u.f)))
return 0;
tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
u.f = float32_mul(u.f, tmp, &env->spe_status);
return float32_to_uint32(u.f, &env->spe_status);
}
-static always_inline int32_t _do_efsctsfz (uint32_t val)
-{
- union {
- int32_t u;
- float32 f;
- } u;
- float32 tmp;
-
- u.u = val;
- /* NaN are not treated the same way IEEE 754 does */
- if (unlikely(isnan(u.f)))
- return 0;
- tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
- u.f = float32_mul(u.f, tmp, &env->spe_status);
-
- return float32_to_int32_round_to_zero(u.f, &env->spe_status);
+#define HELPER_SPE_SINGLE_CONV(name) \
+uint32_t helper_e##name (uint32_t val) \
+{ \
+ return e##name(val); \
+}
+/* efscfsi */
+HELPER_SPE_SINGLE_CONV(fscfsi);
+/* efscfui */
+HELPER_SPE_SINGLE_CONV(fscfui);
+/* efscfuf */
+HELPER_SPE_SINGLE_CONV(fscfuf);
+/* efscfsf */
+HELPER_SPE_SINGLE_CONV(fscfsf);
+/* efsctsi */
+HELPER_SPE_SINGLE_CONV(fsctsi);
+/* efsctui */
+HELPER_SPE_SINGLE_CONV(fsctui);
+/* efsctsiz */
+HELPER_SPE_SINGLE_CONV(fsctsiz);
+/* efsctuiz */
+HELPER_SPE_SINGLE_CONV(fsctuiz);
+/* efsctsf */
+HELPER_SPE_SINGLE_CONV(fsctsf);
+/* efsctuf */
+HELPER_SPE_SINGLE_CONV(fsctuf);
+
+#define HELPER_SPE_VECTOR_CONV(name) \
+uint64_t helper_ev##name (uint64_t val) \
+{ \
+ return ((uint64_t)e##name(val >> 32) << 32) | \
+ (uint64_t)e##name(val); \
}
+/* evfscfsi */
+HELPER_SPE_VECTOR_CONV(fscfsi);
+/* evfscfui */
+HELPER_SPE_VECTOR_CONV(fscfui);
+/* evfscfuf */
+HELPER_SPE_VECTOR_CONV(fscfuf);
+/* evfscfsf */
+HELPER_SPE_VECTOR_CONV(fscfsf);
+/* evfsctsi */
+HELPER_SPE_VECTOR_CONV(fsctsi);
+/* evfsctui */
+HELPER_SPE_VECTOR_CONV(fsctui);
+/* evfsctsiz */
+HELPER_SPE_VECTOR_CONV(fsctsiz);
+/* evfsctuiz */
+HELPER_SPE_VECTOR_CONV(fsctuiz);
+/* evfsctsf */
+HELPER_SPE_VECTOR_CONV(fsctsf);
+/* evfsctuf */
+HELPER_SPE_VECTOR_CONV(fsctuf);
-static always_inline uint32_t _do_efsctufz (uint32_t val)
+/* Single-precision floating-point arithmetic */
+static always_inline uint32_t efsadd (uint32_t op1, uint32_t op2)
{
- union {
- int32_t u;
- float32 f;
- } u;
- float32 tmp;
-
- u.u = val;
- /* NaN are not treated the same way IEEE 754 does */
- if (unlikely(isnan(u.f)))
- return 0;
- tmp = uint64_to_float32(1ULL << 32, &env->spe_status);
- u.f = float32_mul(u.f, tmp, &env->spe_status);
-
- return float32_to_uint32_round_to_zero(u.f, &env->spe_status);
+ CPU_FloatU u1, u2;
+ u1.l = op1;
+ u2.l = op2;
+ u1.f = float32_add(u1.f, u2.f, &env->spe_status);
+ return u1.l;
}
-void do_efscfsf (void)
+static always_inline uint32_t efssub (uint32_t op1, uint32_t op2)
{
- T0_64 = _do_efscfsf(T0_64);
+ CPU_FloatU u1, u2;
+ u1.l = op1;
+ u2.l = op2;
+ u1.f = float32_sub(u1.f, u2.f, &env->spe_status);
+ return u1.l;
}
-void do_efscfuf (void)
+static always_inline uint32_t efsmul (uint32_t op1, uint32_t op2)
{
- T0_64 = _do_efscfuf(T0_64);
+ CPU_FloatU u1, u2;
+ u1.l = op1;
+ u2.l = op2;
+ u1.f = float32_mul(u1.f, u2.f, &env->spe_status);
+ return u1.l;
}
-void do_efsctsf (void)
+static always_inline uint32_t efsdiv (uint32_t op1, uint32_t op2)
{
- T0_64 = _do_efsctsf(T0_64);
+ CPU_FloatU u1, u2;
+ u1.l = op1;
+ u2.l = op2;
+ u1.f = float32_div(u1.f, u2.f, &env->spe_status);
+ return u1.l;
+}
+
+#define HELPER_SPE_SINGLE_ARITH(name) \
+uint32_t helper_e##name (uint32_t op1, uint32_t op2) \
+{ \
+ return e##name(op1, op2); \
+}
+/* efsadd */
+HELPER_SPE_SINGLE_ARITH(fsadd);
+/* efssub */
+HELPER_SPE_SINGLE_ARITH(fssub);
+/* efsmul */
+HELPER_SPE_SINGLE_ARITH(fsmul);
+/* efsdiv */
+HELPER_SPE_SINGLE_ARITH(fsdiv);
+
+#define HELPER_SPE_VECTOR_ARITH(name) \
+uint64_t helper_ev##name (uint64_t op1, uint64_t op2) \
+{ \
+ return ((uint64_t)e##name(op1 >> 32, op2 >> 32) << 32) | \
+ (uint64_t)e##name(op1, op2); \
}
+/* evfsadd */
+HELPER_SPE_VECTOR_ARITH(fsadd);
+/* evfssub */
+HELPER_SPE_VECTOR_ARITH(fssub);
+/* evfsmul */
+HELPER_SPE_VECTOR_ARITH(fsmul);
+/* evfsdiv */
+HELPER_SPE_VECTOR_ARITH(fsdiv);
-void do_efsctuf (void)
+/* Single-precision floating-point comparisons */
+static always_inline uint32_t efststlt (uint32_t op1, uint32_t op2)
{
- T0_64 = _do_efsctuf(T0_64);
+ CPU_FloatU u1, u2;
+ u1.l = op1;
+ u2.l = op2;
+ return float32_lt(u1.f, u2.f, &env->spe_status) ? 4 : 0;
}
-void do_efsctsfz (void)
+static always_inline uint32_t efststgt (uint32_t op1, uint32_t op2)
{
- T0_64 = _do_efsctsfz(T0_64);
+ CPU_FloatU u1, u2;
+ u1.l = op1;
+ u2.l = op2;
+ return float32_le(u1.f, u2.f, &env->spe_status) ? 0 : 4;
}
-void do_efsctufz (void)
+static always_inline uint32_t efststeq (uint32_t op1, uint32_t op2)
{
- T0_64 = _do_efsctufz(T0_64);
+ CPU_FloatU u1, u2;
+ u1.l = op1;
+ u2.l = op2;
+ return float32_eq(u1.f, u2.f, &env->spe_status) ? 4 : 0;
}
-/* Double precision floating point helpers */
-static always_inline int _do_efdcmplt (uint64_t op1, uint64_t op2)
+static always_inline uint32_t efscmplt (uint32_t op1, uint32_t op2)
{
/* XXX: TODO: test special values (NaN, infinites, ...) */
- return _do_efdtstlt(op1, op2);
+ return efststlt(op1, op2);
}
-static always_inline int _do_efdcmpgt (uint64_t op1, uint64_t op2)
+static always_inline uint32_t efscmpgt (uint32_t op1, uint32_t op2)
{
/* XXX: TODO: test special values (NaN, infinites, ...) */
- return _do_efdtstgt(op1, op2);
+ return efststgt(op1, op2);
}
-static always_inline int _do_efdcmpeq (uint64_t op1, uint64_t op2)
+static always_inline uint32_t efscmpeq (uint32_t op1, uint32_t op2)
{
/* XXX: TODO: test special values (NaN, infinites, ...) */
- return _do_efdtsteq(op1, op2);
+ return efststeq(op1, op2);
}
-void do_efdcmplt (void)
+#define HELPER_SINGLE_SPE_CMP(name) \
+uint32_t helper_e##name (uint32_t op1, uint32_t op2) \
+{ \
+ return e##name(op1, op2) << 2; \
+}
+/* efststlt */
+HELPER_SINGLE_SPE_CMP(fststlt);
+/* efststgt */
+HELPER_SINGLE_SPE_CMP(fststgt);
+/* efststeq */
+HELPER_SINGLE_SPE_CMP(fststeq);
+/* efscmplt */
+HELPER_SINGLE_SPE_CMP(fscmplt);
+/* efscmpgt */
+HELPER_SINGLE_SPE_CMP(fscmpgt);
+/* efscmpeq */
+HELPER_SINGLE_SPE_CMP(fscmpeq);
+
+static always_inline uint32_t evcmp_merge (int t0, int t1)
{
- T0 = _do_efdcmplt(T0_64, T1_64);
+ return (t0 << 3) | (t1 << 2) | ((t0 | t1) << 1) | (t0 & t1);
}
-void do_efdcmpgt (void)
-{
- T0 = _do_efdcmpgt(T0_64, T1_64);
+#define HELPER_VECTOR_SPE_CMP(name) \
+uint32_t helper_ev##name (uint64_t op1, uint64_t op2) \
+{ \
+ return evcmp_merge(e##name(op1 >> 32, op2 >> 32), e##name(op1, op2)); \
}
+/* evfststlt */
+HELPER_VECTOR_SPE_CMP(fststlt);
+/* evfststgt */
+HELPER_VECTOR_SPE_CMP(fststgt);
+/* evfststeq */
+HELPER_VECTOR_SPE_CMP(fststeq);
+/* evfscmplt */
+HELPER_VECTOR_SPE_CMP(fscmplt);
+/* evfscmpgt */
+HELPER_VECTOR_SPE_CMP(fscmpgt);
+/* evfscmpeq */
+HELPER_VECTOR_SPE_CMP(fscmpeq);
-void do_efdcmpeq (void)
+/* Double-precision floating-point conversion */
+uint64_t helper_efdcfsi (uint32_t val)
{
- T0 = _do_efdcmpeq(T0_64, T1_64);
+ CPU_DoubleU u;
+
+ u.d = int32_to_float64(val, &env->spe_status);
+
+ return u.ll;
}
-/* Double precision floating-point conversion to/from integer */
-static always_inline uint64_t _do_efdcfsi (int64_t val)
+uint64_t helper_efdcfsid (uint64_t val)
{
- union {
- uint64_t u;
- float64 f;
- } u;
+ CPU_DoubleU u;
- u.f = int64_to_float64(val, &env->spe_status);
+ u.d = int64_to_float64(val, &env->spe_status);
- return u.u;
+ return u.ll;
}
-static always_inline uint64_t _do_efdcfui (uint64_t val)
+uint64_t helper_efdcfui (uint32_t val)
{
- union {
- uint64_t u;
- float64 f;
- } u;
+ CPU_DoubleU u;
- u.f = uint64_to_float64(val, &env->spe_status);
+ u.d = uint32_to_float64(val, &env->spe_status);
- return u.u;
+ return u.ll;
}
-static always_inline int64_t _do_efdctsi (uint64_t val)
+uint64_t helper_efdcfuid (uint64_t val)
{
- union {
- int64_t u;
- float64 f;
- } u;
+ CPU_DoubleU u;
- u.u = val;
- /* NaN are not treated the same way IEEE 754 does */
- if (unlikely(isnan(u.f)))
- return 0;
+ u.d = uint64_to_float64(val, &env->spe_status);
- return float64_to_int64(u.f, &env->spe_status);
+ return u.ll;
}
-static always_inline uint64_t _do_efdctui (uint64_t val)
+uint32_t helper_efdctsi (uint64_t val)
{
- union {
- int64_t u;
- float64 f;
- } u;
+ CPU_DoubleU u;
- u.u = val;
+ u.ll = val;
/* NaN are not treated the same way IEEE 754 does */
- if (unlikely(isnan(u.f)))
+ if (unlikely(float64_is_nan(u.d)))
return 0;
- return float64_to_uint64(u.f, &env->spe_status);
+ return float64_to_int32(u.d, &env->spe_status);
}
-static always_inline int64_t _do_efdctsiz (uint64_t val)
+uint32_t helper_efdctui (uint64_t val)
{
- union {
- int64_t u;
- float64 f;
- } u;
+ CPU_DoubleU u;
- u.u = val;
+ u.ll = val;
/* NaN are not treated the same way IEEE 754 does */
- if (unlikely(isnan(u.f)))
+ if (unlikely(float64_is_nan(u.d)))
return 0;
- return float64_to_int64_round_to_zero(u.f, &env->spe_status);
+ return float64_to_uint32(u.d, &env->spe_status);
}
-static always_inline uint64_t _do_efdctuiz (uint64_t val)
+uint32_t helper_efdctsiz (uint64_t val)
{
- union {
- int64_t u;
- float64 f;
- } u;
+ CPU_DoubleU u;
- u.u = val;
+ u.ll = val;
/* NaN are not treated the same way IEEE 754 does */
- if (unlikely(isnan(u.f)))
+ if (unlikely(float64_is_nan(u.d)))
return 0;
- return float64_to_uint64_round_to_zero(u.f, &env->spe_status);
+ return float64_to_int32_round_to_zero(u.d, &env->spe_status);
}
-void do_efdcfsi (void)
+uint64_t helper_efdctsidz (uint64_t val)
{
- T0_64 = _do_efdcfsi(T0_64);
-}
+ CPU_DoubleU u;
-void do_efdcfui (void)
-{
- T0_64 = _do_efdcfui(T0_64);
-}
+ u.ll = val;
+ /* NaN are not treated the same way IEEE 754 does */
+ if (unlikely(float64_is_nan(u.d)))
+ return 0;
-void do_efdctsi (void)
-{
- T0_64 = _do_efdctsi(T0_64);
+ return float64_to_int64_round_to_zero(u.d, &env->spe_status);
}
-void do_efdctui (void)
+uint32_t helper_efdctuiz (uint64_t val)
{
- T0_64 = _do_efdctui(T0_64);
-}
+ CPU_DoubleU u;
-void do_efdctsiz (void)
-{
- T0_64 = _do_efdctsiz(T0_64);
-}
+ u.ll = val;
+ /* NaN are not treated the same way IEEE 754 does */
+ if (unlikely(float64_is_nan(u.d)))
+ return 0;
-void do_efdctuiz (void)
-{
- T0_64 = _do_efdctuiz(T0_64);
+ return float64_to_uint32_round_to_zero(u.d, &env->spe_status);
}
-/* Double precision floating-point conversion to/from fractional */
-static always_inline uint64_t _do_efdcfsf (int64_t val)
+uint64_t helper_efdctuidz (uint64_t val)
{
- union {
- uint64_t u;
- float64 f;
- } u;
- float64 tmp;
+ CPU_DoubleU u;
- u.f = int32_to_float64(val, &env->spe_status);
- tmp = int64_to_float64(1ULL << 32, &env->spe_status);
- u.f = float64_div(u.f, tmp, &env->spe_status);
+ u.ll = val;
+ /* NaN are not treated the same way IEEE 754 does */
+ if (unlikely(float64_is_nan(u.d)))
+ return 0;
- return u.u;
+ return float64_to_uint64_round_to_zero(u.d, &env->spe_status);
}
-static always_inline uint64_t _do_efdcfuf (uint64_t val)
+uint64_t helper_efdcfsf (uint32_t val)
{
- union {
- uint64_t u;
- float64 f;
- } u;
+ CPU_DoubleU u;
float64 tmp;
- u.f = uint32_to_float64(val, &env->spe_status);
+ u.d = int32_to_float64(val, &env->spe_status);
tmp = int64_to_float64(1ULL << 32, &env->spe_status);
- u.f = float64_div(u.f, tmp, &env->spe_status);
+ u.d = float64_div(u.d, tmp, &env->spe_status);
- return u.u;
+ return u.ll;
}
-static always_inline int64_t _do_efdctsf (uint64_t val)
+uint64_t helper_efdcfuf (uint32_t val)
{
- union {
- int64_t u;
- float64 f;
- } u;
+ CPU_DoubleU u;
float64 tmp;
- u.u = val;
- /* NaN are not treated the same way IEEE 754 does */
- if (unlikely(isnan(u.f)))
- return 0;
- tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
- u.f = float64_mul(u.f, tmp, &env->spe_status);
+ u.d = uint32_to_float64(val, &env->spe_status);
+ tmp = int64_to_float64(1ULL << 32, &env->spe_status);
+ u.d = float64_div(u.d, tmp, &env->spe_status);
- return float64_to_int32(u.f, &env->spe_status);
+ return u.ll;
}
-static always_inline uint64_t _do_efdctuf (uint64_t val)
+uint32_t helper_efdctsf (uint64_t val)
{
- union {
- int64_t u;
- float64 f;
- } u;
+ CPU_DoubleU u;
float64 tmp;
- u.u = val;
+ u.ll = val;
/* NaN are not treated the same way IEEE 754 does */
- if (unlikely(isnan(u.f)))
+ if (unlikely(float64_is_nan(u.d)))
return 0;
tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
- u.f = float64_mul(u.f, tmp, &env->spe_status);
+ u.d = float64_mul(u.d, tmp, &env->spe_status);
- return float64_to_uint32(u.f, &env->spe_status);
+ return float64_to_int32(u.d, &env->spe_status);
}
-static always_inline int64_t _do_efdctsfz (uint64_t val)
+uint32_t helper_efdctuf (uint64_t val)
{
- union {
- int64_t u;
- float64 f;
- } u;
+ CPU_DoubleU u;
float64 tmp;
- u.u = val;
+ u.ll = val;
/* NaN are not treated the same way IEEE 754 does */
- if (unlikely(isnan(u.f)))
+ if (unlikely(float64_is_nan(u.d)))
return 0;
tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
- u.f = float64_mul(u.f, tmp, &env->spe_status);
+ u.d = float64_mul(u.d, tmp, &env->spe_status);
- return float64_to_int32_round_to_zero(u.f, &env->spe_status);
+ return float64_to_uint32(u.d, &env->spe_status);
}
-static always_inline uint64_t _do_efdctufz (uint64_t val)
+uint32_t helper_efscfd (uint64_t val)
{
- union {
- int64_t u;
- float64 f;
- } u;
- float64 tmp;
+ CPU_DoubleU u1;
+ CPU_FloatU u2;
- u.u = val;
- /* NaN are not treated the same way IEEE 754 does */
- if (unlikely(isnan(u.f)))
- return 0;
- tmp = uint64_to_float64(1ULL << 32, &env->spe_status);
- u.f = float64_mul(u.f, tmp, &env->spe_status);
+ u1.ll = val;
+ u2.f = float64_to_float32(u1.d, &env->spe_status);
- return float64_to_uint32_round_to_zero(u.f, &env->spe_status);
+ return u2.l;
}
-void do_efdcfsf (void)
+uint64_t helper_efdcfs (uint32_t val)
{
- T0_64 = _do_efdcfsf(T0_64);
-}
+ CPU_DoubleU u2;
+ CPU_FloatU u1;
-void do_efdcfuf (void)
-{
- T0_64 = _do_efdcfuf(T0_64);
-}
+ u1.l = val;
+ u2.d = float32_to_float64(u1.f, &env->spe_status);
-void do_efdctsf (void)
-{
- T0_64 = _do_efdctsf(T0_64);
+ return u2.ll;
}
-void do_efdctuf (void)
+/* Double precision fixed-point arithmetic */
+uint64_t helper_efdadd (uint64_t op1, uint64_t op2)
{
- T0_64 = _do_efdctuf(T0_64);
+ CPU_DoubleU u1, u2;
+ u1.ll = op1;
+ u2.ll = op2;
+ u1.d = float64_add(u1.d, u2.d, &env->spe_status);
+ return u1.ll;
}
-void do_efdctsfz (void)
+uint64_t helper_efdsub (uint64_t op1, uint64_t op2)
{
- T0_64 = _do_efdctsfz(T0_64);
+ CPU_DoubleU u1, u2;
+ u1.ll = op1;
+ u2.ll = op2;
+ u1.d = float64_sub(u1.d, u2.d, &env->spe_status);
+ return u1.ll;
}
-void do_efdctufz (void)
+uint64_t helper_efdmul (uint64_t op1, uint64_t op2)
{
- T0_64 = _do_efdctufz(T0_64);
+ CPU_DoubleU u1, u2;
+ u1.ll = op1;
+ u2.ll = op2;
+ u1.d = float64_mul(u1.d, u2.d, &env->spe_status);
+ return u1.ll;
}
-/* Floating point conversion between single and double precision */
-static always_inline uint32_t _do_efscfd (uint64_t val)
+uint64_t helper_efddiv (uint64_t op1, uint64_t op2)
{
- union {
- uint64_t u;
- float64 f;
- } u1;
- union {
- uint32_t u;
- float32 f;
- } u2;
-
- u1.u = val;
- u2.f = float64_to_float32(u1.f, &env->spe_status);
-
- return u2.u;
+ CPU_DoubleU u1, u2;
+ u1.ll = op1;
+ u2.ll = op2;
+ u1.d = float64_div(u1.d, u2.d, &env->spe_status);
+ return u1.ll;
}
-static always_inline uint64_t _do_efdcfs (uint32_t val)
+/* Double precision floating point helpers */
+uint32_t helper_efdtstlt (uint64_t op1, uint64_t op2)
{
- union {
- uint64_t u;
- float64 f;
- } u2;
- union {
- uint32_t u;
- float32 f;
- } u1;
-
- u1.u = val;
- u2.f = float32_to_float64(u1.f, &env->spe_status);
-
- return u2.u;
+ CPU_DoubleU u1, u2;
+ u1.ll = op1;
+ u2.ll = op2;
+ return float64_lt(u1.d, u2.d, &env->spe_status) ? 4 : 0;
}
-void do_efscfd (void)
+uint32_t helper_efdtstgt (uint64_t op1, uint64_t op2)
{
- T0_64 = _do_efscfd(T0_64);
+ CPU_DoubleU u1, u2;
+ u1.ll = op1;
+ u2.ll = op2;
+ return float64_le(u1.d, u2.d, &env->spe_status) ? 0 : 4;
}
-void do_efdcfs (void)
+uint32_t helper_efdtsteq (uint64_t op1, uint64_t op2)
{
- T0_64 = _do_efdcfs(T0_64);
+ CPU_DoubleU u1, u2;
+ u1.ll = op1;
+ u2.ll = op2;
+ return float64_eq(u1.d, u2.d, &env->spe_status) ? 4 : 0;
}
-/* Single precision fixed-point vector arithmetic */
-/* evfsabs */
-DO_SPE_OP1(fsabs);
-/* evfsnabs */
-DO_SPE_OP1(fsnabs);
-/* evfsneg */
-DO_SPE_OP1(fsneg);
-/* evfsadd */
-DO_SPE_OP2(fsadd);
-/* evfssub */
-DO_SPE_OP2(fssub);
-/* evfsmul */
-DO_SPE_OP2(fsmul);
-/* evfsdiv */
-DO_SPE_OP2(fsdiv);
-
-/* Single-precision floating-point comparisons */
-static always_inline int _do_efscmplt (uint32_t op1, uint32_t op2)
+uint32_t helper_efdcmplt (uint64_t op1, uint64_t op2)
{
/* XXX: TODO: test special values (NaN, infinites, ...) */
- return _do_efststlt(op1, op2);
+ return helper_efdtstlt(op1, op2);
}
-static always_inline int _do_efscmpgt (uint32_t op1, uint32_t op2)
+uint32_t helper_efdcmpgt (uint64_t op1, uint64_t op2)
{
/* XXX: TODO: test special values (NaN, infinites, ...) */
- return _do_efststgt(op1, op2);
+ return helper_efdtstgt(op1, op2);
}
-static always_inline int _do_efscmpeq (uint32_t op1, uint32_t op2)
+uint32_t helper_efdcmpeq (uint64_t op1, uint64_t op2)
{
/* XXX: TODO: test special values (NaN, infinites, ...) */
- return _do_efststeq(op1, op2);
-}
-
-void do_efscmplt (void)
-{
- T0 = _do_efscmplt(T0_64, T1_64);
-}
-
-void do_efscmpgt (void)
-{
- T0 = _do_efscmpgt(T0_64, T1_64);
-}
-
-void do_efscmpeq (void)
-{
- T0 = _do_efscmpeq(T0_64, T1_64);
+ return helper_efdtsteq(op1, op2);
}
-/* Single-precision floating-point vector comparisons */
-/* evfscmplt */
-DO_SPE_CMP(fscmplt);
-/* evfscmpgt */
-DO_SPE_CMP(fscmpgt);
-/* evfscmpeq */
-DO_SPE_CMP(fscmpeq);
-/* evfststlt */
-DO_SPE_CMP(fststlt);
-/* evfststgt */
-DO_SPE_CMP(fststgt);
-/* evfststeq */
-DO_SPE_CMP(fststeq);
-
-/* Single-precision floating-point vector conversions */
-/* evfscfsi */
-DO_SPE_OP1(fscfsi);
-/* evfscfui */
-DO_SPE_OP1(fscfui);
-/* evfscfuf */
-DO_SPE_OP1(fscfuf);
-/* evfscfsf */
-DO_SPE_OP1(fscfsf);
-/* evfsctsi */
-DO_SPE_OP1(fsctsi);
-/* evfsctui */
-DO_SPE_OP1(fsctui);
-/* evfsctsiz */
-DO_SPE_OP1(fsctsiz);
-/* evfsctuiz */
-DO_SPE_OP1(fsctuiz);
-/* evfsctsf */
-DO_SPE_OP1(fsctsf);
-/* evfsctuf */
-DO_SPE_OP1(fsctuf);
-#endif /* defined(TARGET_PPCEMB) */
-
/*****************************************************************************/
/* Softmmu support */
#if !defined (CONFIG_USER_ONLY)
#define MMUSUFFIX _mmu
-#define GETPC() (__builtin_return_address(0))
#define SHIFT 0
#include "softmmu_template.h"
{
TranslationBlock *tb;
CPUState *saved_env;
- target_phys_addr_t pc;
+ unsigned long pc;
int ret;
/* XXX: hack to restore env in all cases, even if not called from
if (unlikely(ret != 0)) {
if (likely(retaddr)) {
/* now we have a real cpu fault */
- pc = (target_phys_addr_t)(unsigned long)retaddr;
+ pc = (unsigned long)retaddr;
tb = tb_find_pc(pc);
if (likely(tb)) {
/* the PC is inside the translated code. It means that we have
cpu_restore_state(tb, env, pc, NULL);
}
}
- do_raise_exception_err(env->exception_index, env->error_code);
+ helper_raise_exception_err(env->exception_index, env->error_code);
}
env = saved_env;
}
+/* Segment registers load and store */
+target_ulong helper_load_sr (target_ulong sr_num)
+{
+ return env->sr[sr_num];
+}
+
+void helper_store_sr (target_ulong sr_num, target_ulong val)
+{
+ ppc_store_sr(env, sr_num, val);
+}
+
+/* SLB management */
+#if defined(TARGET_PPC64)
+target_ulong helper_load_slb (target_ulong slb_nr)
+{
+ return ppc_load_slb(env, slb_nr);
+}
+
+void helper_store_slb (target_ulong slb_nr, target_ulong rs)
+{
+ ppc_store_slb(env, slb_nr, rs);
+}
+
+void helper_slbia (void)
+{
+ ppc_slb_invalidate_all(env);
+}
+
+void helper_slbie (target_ulong addr)
+{
+ ppc_slb_invalidate_one(env, addr);
+}
+
+#endif /* defined(TARGET_PPC64) */
+
+/* TLB management */
+void helper_tlbia (void)
+{
+ ppc_tlb_invalidate_all(env);
+}
+
+void helper_tlbie (target_ulong addr)
+{
+ ppc_tlb_invalidate_one(env, addr);
+}
+
/* Software driven TLBs management */
/* PowerPC 602/603 software TLB load instructions helpers */
-void do_load_6xx_tlb (int is_code)
+static void do_6xx_tlb (target_ulong new_EPN, int is_code)
{
target_ulong RPN, CMP, EPN;
int way;
way = (env->spr[SPR_SRR1] >> 17) & 1;
#if defined (DEBUG_SOFTWARE_TLB)
if (loglevel != 0) {
- fprintf(logfile, "%s: EPN %08lx %08lx PTE0 %08lx PTE1 %08lx way %d\n",
- __func__, (unsigned long)T0, (unsigned long)EPN,
- (unsigned long)CMP, (unsigned long)RPN, way);
+ fprintf(logfile, "%s: EPN " ADDRX " " ADDRX " PTE0 " ADDRX
+ " PTE1 " ADDRX " way %d\n",
+ __func__, new_EPN, EPN, CMP, RPN, way);
}
#endif
/* Store this TLB */
- ppc6xx_tlb_store(env, (uint32_t)(T0 & TARGET_PAGE_MASK),
+ ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
way, is_code, CMP, RPN);
}
-void do_load_74xx_tlb (int is_code)
+void helper_6xx_tlbd (target_ulong EPN)
+{
+ do_6xx_tlb(EPN, 0);
+}
+
+void helper_6xx_tlbi (target_ulong EPN)
+{
+ do_6xx_tlb(EPN, 1);
+}
+
+/* PowerPC 74xx software TLB load instructions helpers */
+static void do_74xx_tlb (target_ulong new_EPN, int is_code)
{
target_ulong RPN, CMP, EPN;
int way;
way = env->spr[SPR_TLBMISS] & 0x3;
#if defined (DEBUG_SOFTWARE_TLB)
if (loglevel != 0) {
- fprintf(logfile, "%s: EPN %08lx %08lx PTE0 %08lx PTE1 %08lx way %d\n",
- __func__, (unsigned long)T0, (unsigned long)EPN,
- (unsigned long)CMP, (unsigned long)RPN, way);
+ fprintf(logfile, "%s: EPN " ADDRX " " ADDRX " PTE0 " ADDRX
+ " PTE1 " ADDRX " way %d\n",
+ __func__, new_EPN, EPN, CMP, RPN, way);
}
#endif
/* Store this TLB */
- ppc6xx_tlb_store(env, (uint32_t)(T0 & TARGET_PAGE_MASK),
+ ppc6xx_tlb_store(env, (uint32_t)(new_EPN & TARGET_PAGE_MASK),
way, is_code, CMP, RPN);
}
-static target_ulong booke_tlb_to_page_size (int size)
+void helper_74xx_tlbd (target_ulong EPN)
+{
+ do_74xx_tlb(EPN, 0);
+}
+
+void helper_74xx_tlbi (target_ulong EPN)
+{
+ do_74xx_tlb(EPN, 1);
+}
+
+static always_inline target_ulong booke_tlb_to_page_size (int size)
{
return 1024 << (2 * size);
}
-static int booke_page_size_to_tlb (target_ulong page_size)
+static always_inline int booke_page_size_to_tlb (target_ulong page_size)
{
int size;
}
/* Helpers for 4xx TLB management */
-void do_4xx_tlbre_lo (void)
+target_ulong helper_4xx_tlbre_lo (target_ulong entry)
{
ppcemb_tlb_t *tlb;
+ target_ulong ret;
int size;
- T0 &= 0x3F;
- tlb = &env->tlb[T0].tlbe;
- T0 = tlb->EPN;
+ entry &= 0x3F;
+ tlb = &env->tlb[entry].tlbe;
+ ret = tlb->EPN;
if (tlb->prot & PAGE_VALID)
- T0 |= 0x400;
+ ret |= 0x400;
size = booke_page_size_to_tlb(tlb->size);
if (size < 0 || size > 0x7)
size = 1;
- T0 |= size << 7;
+ ret |= size << 7;
env->spr[SPR_40x_PID] = tlb->PID;
+ return ret;
}
-void do_4xx_tlbre_hi (void)
+target_ulong helper_4xx_tlbre_hi (target_ulong entry)
{
ppcemb_tlb_t *tlb;
+ target_ulong ret;
- T0 &= 0x3F;
- tlb = &env->tlb[T0].tlbe;
- T0 = tlb->RPN;
+ entry &= 0x3F;
+ tlb = &env->tlb[entry].tlbe;
+ ret = tlb->RPN;
if (tlb->prot & PAGE_EXEC)
- T0 |= 0x200;
+ ret |= 0x200;
if (tlb->prot & PAGE_WRITE)
- T0 |= 0x100;
+ ret |= 0x100;
+ return ret;
}
-void do_4xx_tlbwe_hi (void)
+void helper_4xx_tlbwe_hi (target_ulong entry, target_ulong val)
{
ppcemb_tlb_t *tlb;
target_ulong page, end;
#if defined (DEBUG_SOFTWARE_TLB)
if (loglevel != 0) {
- fprintf(logfile, "%s T0 " REGX " T1 " REGX "\n", __func__, T0, T1);
+ fprintf(logfile, "%s entry %d val " ADDRX "\n", __func__, (int)entry, val);
}
#endif
- T0 &= 0x3F;
- tlb = &env->tlb[T0].tlbe;
+ entry &= 0x3F;
+ tlb = &env->tlb[entry].tlbe;
/* Invalidate previous TLB (if it's valid) */
if (tlb->prot & PAGE_VALID) {
end = tlb->EPN + tlb->size;
#if defined (DEBUG_SOFTWARE_TLB)
if (loglevel != 0) {
fprintf(logfile, "%s: invalidate old TLB %d start " ADDRX
- " end " ADDRX "\n", __func__, (int)T0, tlb->EPN, end);
+ " end " ADDRX "\n", __func__, (int)entry, tlb->EPN, end);
}
#endif
for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
tlb_flush_page(env, page);
}
- tlb->size = booke_tlb_to_page_size((T1 >> 7) & 0x7);
+ tlb->size = booke_tlb_to_page_size((val >> 7) & 0x7);
/* We cannot handle TLB size < TARGET_PAGE_SIZE.
* If this ever occurs, one should use the ppcemb target instead
* of the ppc or ppc64 one
*/
- if ((T1 & 0x40) && tlb->size < TARGET_PAGE_SIZE) {
+ if ((val & 0x40) && tlb->size < TARGET_PAGE_SIZE) {
cpu_abort(env, "TLB size " TARGET_FMT_lu " < %u "
"are not supported (%d)\n",
- tlb->size, TARGET_PAGE_SIZE, (int)((T1 >> 7) & 0x7));
+ tlb->size, TARGET_PAGE_SIZE, (int)((val >> 7) & 0x7));
}
- tlb->EPN = T1 & ~(tlb->size - 1);
- if (T1 & 0x40)
+ tlb->EPN = val & ~(tlb->size - 1);
+ if (val & 0x40)
tlb->prot |= PAGE_VALID;
else
tlb->prot &= ~PAGE_VALID;
- if (T1 & 0x20) {
+ if (val & 0x20) {
/* XXX: TO BE FIXED */
cpu_abort(env, "Little-endian TLB entries are not supported by now\n");
}
tlb->PID = env->spr[SPR_40x_PID]; /* PID */
- tlb->attr = T1 & 0xFF;
+ tlb->attr = val & 0xFF;
#if defined (DEBUG_SOFTWARE_TLB)
if (loglevel != 0) {
fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
" size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
- (int)T0, tlb->RPN, tlb->EPN, tlb->size,
+ (int)entry, tlb->RPN, tlb->EPN, tlb->size,
tlb->prot & PAGE_READ ? 'r' : '-',
tlb->prot & PAGE_WRITE ? 'w' : '-',
tlb->prot & PAGE_EXEC ? 'x' : '-',
#if defined (DEBUG_SOFTWARE_TLB)
if (loglevel != 0) {
fprintf(logfile, "%s: invalidate TLB %d start " ADDRX
- " end " ADDRX "\n", __func__, (int)T0, tlb->EPN, end);
+ " end " ADDRX "\n", __func__, (int)entry, tlb->EPN, end);
}
#endif
for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)
}
}
-void do_4xx_tlbwe_lo (void)
+void helper_4xx_tlbwe_lo (target_ulong entry, target_ulong val)
{
ppcemb_tlb_t *tlb;
#if defined (DEBUG_SOFTWARE_TLB)
if (loglevel != 0) {
- fprintf(logfile, "%s T0 " REGX " T1 " REGX "\n", __func__, T0, T1);
+ fprintf(logfile, "%s entry %i val " ADDRX "\n", __func__, (int)entry, val);
}
#endif
- T0 &= 0x3F;
- tlb = &env->tlb[T0].tlbe;
- tlb->RPN = T1 & 0xFFFFFC00;
+ entry &= 0x3F;
+ tlb = &env->tlb[entry].tlbe;
+ tlb->RPN = val & 0xFFFFFC00;
tlb->prot = PAGE_READ;
- if (T1 & 0x200)
+ if (val & 0x200)
tlb->prot |= PAGE_EXEC;
- if (T1 & 0x100)
+ if (val & 0x100)
tlb->prot |= PAGE_WRITE;
#if defined (DEBUG_SOFTWARE_TLB)
if (loglevel != 0) {
fprintf(logfile, "%s: set up TLB %d RPN " PADDRX " EPN " ADDRX
" size " ADDRX " prot %c%c%c%c PID %d\n", __func__,
- (int)T0, tlb->RPN, tlb->EPN, tlb->size,
+ (int)entry, tlb->RPN, tlb->EPN, tlb->size,
tlb->prot & PAGE_READ ? 'r' : '-',
tlb->prot & PAGE_WRITE ? 'w' : '-',
tlb->prot & PAGE_EXEC ? 'x' : '-',
#endif
}
+target_ulong helper_4xx_tlbsx (target_ulong address)
+{
+ return ppcemb_tlb_search(env, address, env->spr[SPR_40x_PID]);
+}
+
/* PowerPC 440 TLB management */
-void do_440_tlbwe (int word)
+void helper_440_tlbwe (uint32_t word, target_ulong entry, target_ulong value)
{
ppcemb_tlb_t *tlb;
target_ulong EPN, RPN, size;
#if defined (DEBUG_SOFTWARE_TLB)
if (loglevel != 0) {
- fprintf(logfile, "%s word %d T0 " REGX " T1 " REGX "\n",
- __func__, word, T0, T1);
+ fprintf(logfile, "%s word %d entry %d value " ADDRX "\n",
+ __func__, word, (int)entry, value);
}
#endif
do_flush_tlbs = 0;
- T0 &= 0x3F;
- tlb = &env->tlb[T0].tlbe;
+ entry &= 0x3F;
+ tlb = &env->tlb[entry].tlbe;
switch (word) {
default:
/* Just here to please gcc */
case 0:
- EPN = T1 & 0xFFFFFC00;
+ EPN = value & 0xFFFFFC00;
if ((tlb->prot & PAGE_VALID) && EPN != tlb->EPN)
do_flush_tlbs = 1;
tlb->EPN = EPN;
- size = booke_tlb_to_page_size((T1 >> 4) & 0xF);
+ size = booke_tlb_to_page_size((value >> 4) & 0xF);
if ((tlb->prot & PAGE_VALID) && tlb->size < size)
do_flush_tlbs = 1;
tlb->size = size;
tlb->attr &= ~0x1;
- tlb->attr |= (T1 >> 8) & 1;
- if (T1 & 0x200) {
+ tlb->attr |= (value >> 8) & 1;
+ if (value & 0x200) {
tlb->prot |= PAGE_VALID;
} else {
if (tlb->prot & PAGE_VALID) {
tlb_flush(env, 1);
break;
case 1:
- RPN = T1 & 0xFFFFFC0F;
+ RPN = value & 0xFFFFFC0F;
if ((tlb->prot & PAGE_VALID) && tlb->RPN != RPN)
tlb_flush(env, 1);
tlb->RPN = RPN;
break;
case 2:
- tlb->attr = (tlb->attr & 0x1) | (T1 & 0x0000FF00);
+ tlb->attr = (tlb->attr & 0x1) | (value & 0x0000FF00);
tlb->prot = tlb->prot & PAGE_VALID;
- if (T1 & 0x1)
+ if (value & 0x1)
tlb->prot |= PAGE_READ << 4;
- if (T1 & 0x2)
+ if (value & 0x2)
tlb->prot |= PAGE_WRITE << 4;
- if (T1 & 0x4)
+ if (value & 0x4)
tlb->prot |= PAGE_EXEC << 4;
- if (T1 & 0x8)
+ if (value & 0x8)
tlb->prot |= PAGE_READ;
- if (T1 & 0x10)
+ if (value & 0x10)
tlb->prot |= PAGE_WRITE;
- if (T1 & 0x20)
+ if (value & 0x20)
tlb->prot |= PAGE_EXEC;
break;
}
}
-void do_440_tlbre (int word)
+target_ulong helper_440_tlbre (uint32_t word, target_ulong entry)
{
ppcemb_tlb_t *tlb;
+ target_ulong ret;
int size;
- T0 &= 0x3F;
- tlb = &env->tlb[T0].tlbe;
+ entry &= 0x3F;
+ tlb = &env->tlb[entry].tlbe;
switch (word) {
default:
/* Just here to please gcc */
case 0:
- T0 = tlb->EPN;
+ ret = tlb->EPN;
size = booke_page_size_to_tlb(tlb->size);
if (size < 0 || size > 0xF)
size = 1;
- T0 |= size << 4;
+ ret |= size << 4;
if (tlb->attr & 0x1)
- T0 |= 0x100;
+ ret |= 0x100;
if (tlb->prot & PAGE_VALID)
- T0 |= 0x200;
+ ret |= 0x200;
env->spr[SPR_440_MMUCR] &= ~0x000000FF;
env->spr[SPR_440_MMUCR] |= tlb->PID;
break;
case 1:
- T0 = tlb->RPN;
+ ret = tlb->RPN;
break;
case 2:
- T0 = tlb->attr & ~0x1;
+ ret = tlb->attr & ~0x1;
if (tlb->prot & (PAGE_READ << 4))
- T0 |= 0x1;
+ ret |= 0x1;
if (tlb->prot & (PAGE_WRITE << 4))
- T0 |= 0x2;
+ ret |= 0x2;
if (tlb->prot & (PAGE_EXEC << 4))
- T0 |= 0x4;
+ ret |= 0x4;
if (tlb->prot & PAGE_READ)
- T0 |= 0x8;
+ ret |= 0x8;
if (tlb->prot & PAGE_WRITE)
- T0 |= 0x10;
+ ret |= 0x10;
if (tlb->prot & PAGE_EXEC)
- T0 |= 0x20;
+ ret |= 0x20;
break;
}
+ return ret;
}
+
+target_ulong helper_440_tlbsx (target_ulong address)
+{
+ return ppcemb_tlb_search(env, address, env->spr[SPR_440_MMUCR] & 0xFF);
+}
+
#endif /* !CONFIG_USER_ONLY */
projects / qemu / blobdiff