* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
+//#define DEBUG_OP
+
#include "config.h"
#include "exec.h"
#define Ts2 (int32_t)T2
#define FT0 (env->ft0)
+#define FT1 (env->ft1)
+#define FT2 (env->ft2)
+
+#define FTS0 ((float)env->ft0)
+#define FTS1 ((float)env->ft1)
+#define FTS2 ((float)env->ft2)
-#define PPC_OP(name) void op_##name(void)
+#define PPC_OP(name) void glue(op_, name)(void)
#define REG 0
#include "op_template.h"
} else {
tmp = 0x02;
}
- set_CRn(0, tmp);
+ env->crf[0] = tmp;
RETURN();
}
tmp = 0x02;
}
tmp |= xer_ov;
- set_CRn(0, tmp);
+ env->crf[0] = tmp;
RETURN();
}
/* reset_Rc0 */
PPC_OP(reset_Rc0)
{
- set_CRn(0, 0x02 | xer_ov);
+ env->crf[0] = 0x02 | xer_ov;
RETURN();
}
/* set_Rc0_1 */
PPC_OP(set_Rc0_1)
{
- set_CRn(0, 0x04 | xer_ov);
+ env->crf[0] = 0x04 | xer_ov;
RETURN();
}
+/* Set Rc1 (for floating point arithmetic) */
+PPC_OP(set_Rc1)
+{
+ env->crf[1] = regs->fpscr[7];
+ RETURN();
+}
+
+/* Constants load */
PPC_OP(set_T0)
{
T0 = PARAM(1);
RETURN();
}
-/* Update time base */
-PPC_OP(update_tb)
+/* Generate exceptions */
+PPC_OP(raise_exception_err)
{
- T0 = regs->spr[SPR_ENCODE(268)];
- T1 = T0;
- T0 += PARAM(1);
- if (T0 < T1) {
- T1 = regs->spr[SPR_ENCODE(269)] + 1;
- regs->spr[SPR_ENCODE(269)] = T1;
- }
- regs->spr[SPR_ENCODE(268)] = T0;
- RETURN();
+ do_raise_exception_err(PARAM(1), PARAM(2));
}
PPC_OP(raise_exception)
{
- raise_exception(PARAM(1));
+ do_raise_exception(PARAM(1));
+}
+
+PPC_OP(update_nip)
+{
+ env->nip = PARAM(1);
+}
+
+PPC_OP(debug)
+{
+ env->nip = PARAM(1);
+#if defined (DEBUG_OP)
+ dump_state();
+#endif
+ do_raise_exception(EXCP_DEBUG);
+ RETURN();
+}
+
+/* Segment registers load and store with immediate index */
+PPC_OP(load_srin)
+{
+ T0 = regs->sr[T1 >> 28];
+ RETURN();
+}
+
+PPC_OP(store_srin)
+{
+ do_store_sr(T1 >> 28);
+ RETURN();
+}
+
+PPC_OP(load_sdr1)
+{
+ T0 = regs->sdr1;
+ RETURN();
+}
+
+PPC_OP(store_sdr1)
+{
+ regs->sdr1 = T0;
RETURN();
}
EXIT_TB();
}
+/* Load/store special registers */
PPC_OP(load_cr)
{
- T0 = do_load_cr();
+ do_load_cr();
RETURN();
}
PPC_OP(store_cr)
{
- do_store_cr(PARAM(1), T0);
+ do_store_cr(PARAM(1));
RETURN();
}
PPC_OP(load_xer_bc)
{
- T0 = xer_bc;
+ T1 = xer_bc;
RETURN();
}
PPC_OP(load_xer)
{
- T0 = do_load_xer();
+ do_load_xer();
RETURN();
}
PPC_OP(store_xer)
{
- do_store_xer(T0);
+ do_store_xer();
RETURN();
}
PPC_OP(load_msr)
{
- T0 = do_load_msr();
+ do_load_msr();
RETURN();
}
PPC_OP(store_msr)
{
- do_store_msr(T0);
+ do_store_msr();
+ RETURN();
+}
+
+/* SPR */
+PPC_OP(load_spr)
+{
+ T0 = regs->spr[PARAM(1)];
+ RETURN();
+}
+
+PPC_OP(store_spr)
+{
+ regs->spr[PARAM(1)] = T0;
RETURN();
}
PPC_OP(load_lr)
{
- regs->LR = PARAM(1);
+ T0 = regs->lr;
RETURN();
}
-/* Set reservation */
-PPC_OP(set_reservation)
+PPC_OP(store_lr)
{
- regs->reserve = T1 & ~0x03;
+ regs->lr = T0;
RETURN();
}
-/* Reset reservation */
-PPC_OP(reset_reservation)
+PPC_OP(load_ctr)
{
- regs->reserve = 0;
+ T0 = regs->ctr;
+ RETURN();
+}
+
+PPC_OP(store_ctr)
+{
+ regs->ctr = T0;
+ RETURN();
+}
+
+PPC_OP(load_tbl)
+{
+ T0 = cpu_ppc_load_tbl(regs);
+ RETURN();
+}
+
+PPC_OP(load_tbu)
+{
+ T0 = cpu_ppc_load_tbu(regs);
+ RETURN();
+}
+
+PPC_OP(store_tbl)
+{
+ cpu_ppc_store_tbl(regs, T0);
+ RETURN();
+}
+
+PPC_OP(store_tbu)
+{
+ cpu_ppc_store_tbu(regs, T0);
+ RETURN();
+}
+
+PPC_OP(load_decr)
+{
+ T0 = cpu_ppc_load_decr(regs);
+ }
+
+PPC_OP(store_decr)
+{
+ cpu_ppc_store_decr(regs, T0);
+ RETURN();
+}
+
+PPC_OP(load_ibat)
+{
+ T0 = regs->IBAT[PARAM(1)][PARAM(2)];
+}
+
+PPC_OP(store_ibat)
+{
+ do_store_ibat(PARAM(1), PARAM(2));
+}
+
+PPC_OP(load_dbat)
+{
+ T0 = regs->DBAT[PARAM(1)][PARAM(2)];
+}
+
+PPC_OP(store_dbat)
+{
+ do_store_dbat(PARAM(1), PARAM(2));
+}
+
+/* FPSCR */
+PPC_OP(load_fpscr)
+{
+ do_load_fpscr();
+ RETURN();
+}
+
+PPC_OP(store_fpscr)
+{
+ do_store_fpscr(PARAM(1));
+ RETURN();
+}
+
+PPC_OP(reset_scrfx)
+{
+ regs->fpscr[7] &= ~0x8;
RETURN();
}
}
/* Branch */
-#define __PPC_OP_B(name, target) \
-PPC_OP(name) \
-{ \
- regs->nip = (target); \
- RETURN(); \
-}
-
-#define __PPC_OP_BL(name, target) \
-PPC_OP(name) \
-{ \
- regs->LR = PARAM(1); \
- regs->nip = (target); \
- RETURN(); \
-}
-
-#define PPC_OP_B(name, target) \
-__PPC_OP_B(name, target); \
-__PPC_OP_BL(name##l, target)
-
-#define __PPC_OP_BC(name, cond, target) \
-PPC_OP(name) \
-{ \
- if (cond) { \
- T0 = (target); \
- } else { \
- T0 = PARAM(1); \
- } \
- regs->nip = T0; \
- RETURN(); \
-}
-
-#define __PPC_OP_BCL(name, cond, target) \
-PPC_OP(name) \
-{ \
- if (cond) { \
- T0 = (target); \
- regs->LR = PARAM(1); \
- } else { \
- T0 = PARAM(1); \
- } \
- regs->nip = T0; \
- RETURN(); \
-}
-
-#define _PPC_OP_BC(name, namel, cond, target) \
-__PPC_OP_BC(name, cond, target); \
-__PPC_OP_BCL(namel, cond, target)
-
-/* Branch to target */
-#define PPC_OP_BC(name, cond) \
-_PPC_OP_BC(b_##name, bl_##name, cond, PARAM(2))
-
-PPC_OP_B(b, PARAM(1));
-PPC_OP_BC(ctr, (regs->CTR != 0));
-PPC_OP_BC(ctr_true, (regs->CTR != 0 && (T0 & PARAM(3)) != 0));
-PPC_OP_BC(ctr_false, (regs->CTR != 0 && (T0 & PARAM(3)) == 0));
-PPC_OP_BC(ctrz, (regs->CTR == 0));
-PPC_OP_BC(ctrz_true, (regs->CTR == 0 && (T0 & PARAM(3)) != 0));
-PPC_OP_BC(ctrz_false, (regs->CTR == 0 && (T0 & PARAM(3)) == 0));
-PPC_OP_BC(true, ((T0 & PARAM(3)) != 0));
-PPC_OP_BC(false, ((T0 & PARAM(3)) == 0));
-
-/* Branch to CTR */
-#define PPC_OP_BCCTR(name, cond) \
-_PPC_OP_BC(bctr_##name, bctrl_##name, cond, regs->CTR & ~0x03)
-
-PPC_OP_B(bctr, regs->CTR & ~0x03);
-PPC_OP_BCCTR(ctr, (regs->CTR != 0));
-PPC_OP_BCCTR(ctr_true, (regs->CTR != 0 && (T0 & PARAM(2)) != 0));
-PPC_OP_BCCTR(ctr_false, (regs->CTR != 0 && (T0 & PARAM(2)) == 0));
-PPC_OP_BCCTR(ctrz, (regs->CTR == 0));
-PPC_OP_BCCTR(ctrz_true, (regs->CTR == 0 && (T0 & PARAM(2)) != 0));
-PPC_OP_BCCTR(ctrz_false, (regs->CTR == 0 && (T0 & PARAM(2)) == 0));
-PPC_OP_BCCTR(true, ((T0 & PARAM(2)) != 0));
-PPC_OP_BCCTR(false, ((T0 & PARAM(2)) == 0));
-
-/* Branch to LR */
-#define PPC_OP_BCLR(name, cond) \
-_PPC_OP_BC(blr_##name, blrl_##name, cond, regs->LR & ~0x03)
-
-PPC_OP_B(blr, regs->LR & ~0x03);
-PPC_OP_BCLR(ctr, (regs->CTR != 0));
-PPC_OP_BCLR(ctr_true, (regs->CTR != 0 && (T0 & PARAM(2)) != 0));
-PPC_OP_BCLR(ctr_false, (regs->CTR != 0 && (T0 & PARAM(2)) == 0));
-PPC_OP_BCLR(ctrz, (regs->CTR == 0));
-PPC_OP_BCLR(ctrz_true, (regs->CTR == 0 && (T0 & PARAM(2)) != 0));
-PPC_OP_BCLR(ctrz_false, (regs->CTR == 0 && (T0 & PARAM(2)) == 0));
-PPC_OP_BCLR(true, ((T0 & PARAM(2)) != 0));
-PPC_OP_BCLR(false, ((T0 & PARAM(2)) == 0));
+#define EIP regs->nip
+
+PPC_OP(setlr)
+{
+ regs->lr = PARAM1;
+}
+
+PPC_OP(b)
+{
+ JUMP_TB(b1, PARAM1, 0, PARAM2);
+}
+
+PPC_OP(b_T1)
+{
+ regs->nip = T1;
+}
+
+PPC_OP(btest)
+{
+ if (T0) {
+ JUMP_TB(btest, PARAM1, 0, PARAM2);
+ } else {
+ JUMP_TB(btest, PARAM1, 1, PARAM3);
+ }
+ RETURN();
+}
+
+PPC_OP(btest_T1)
+{
+ if (T0) {
+ regs->nip = T1 & ~3;
+ } else {
+ regs->nip = PARAM1;
+ }
+ RETURN();
+}
+
+PPC_OP(movl_T1_ctr)
+{
+ T1 = regs->ctr;
+}
+
+PPC_OP(movl_T1_lr)
+{
+ T1 = regs->lr;
+}
+
+/* tests with result in T0 */
+
+PPC_OP(test_ctr)
+{
+ T0 = regs->ctr;
+}
+
+PPC_OP(test_ctr_true)
+{
+ T0 = (regs->ctr != 0 && (T0 & PARAM(1)) != 0);
+}
+
+PPC_OP(test_ctr_false)
+{
+ T0 = (regs->ctr != 0 && (T0 & PARAM(1)) == 0);
+}
+
+PPC_OP(test_ctrz)
+{
+ T0 = (regs->ctr == 0);
+}
+
+PPC_OP(test_ctrz_true)
+{
+ T0 = (regs->ctr == 0 && (T0 & PARAM(1)) != 0);
+}
+
+PPC_OP(test_ctrz_false)
+{
+ T0 = (regs->ctr == 0 && (T0 & PARAM(1)) == 0);
+}
+
+PPC_OP(test_true)
+{
+ T0 = (T0 & PARAM(1));
+}
+
+PPC_OP(test_false)
+{
+ T0 = ((T0 & PARAM(1)) == 0);
+}
/* CTR maintenance */
PPC_OP(dec_ctr)
{
- regs->CTR--;
+ regs->ctr--;
RETURN();
}
/* rotate left word immediate then mask insert */
PPC_OP(rlwimi)
{
- T0 = rotl(T0, PARAM(1) & PARAM(2)) | (T0 & PARAM(3));
+ T0 = (rotl(T0, PARAM(1)) & PARAM(2)) | (T1 & PARAM(3));
RETURN();
}
/* shift right algebraic word */
PPC_OP(sraw)
{
- Ts0 = do_sraw(Ts0, T1);
+ do_sraw();
RETURN();
}
}
/*** Floating-Point arithmetic ***/
-
-/*** Floating-Point multiply-and-add ***/
-
-/*** Floating-Point round & convert ***/
-
-/*** Floating-Point compare ***/
-
-/*** Floating-Point status & ctrl register ***/
-
-/*** Integer load ***/
-#define ld16x(x) s_ext16(ld16(x))
-#define PPC_ILD_OPX(name, op) \
-PPC_OP(l##name##x_z) \
-{ \
- T1 = op(T0); \
- RETURN(); \
-} \
-PPC_OP(l##name##x) \
-{ \
- T0 += T1; \
- T1 = op(T0); \
- RETURN(); \
+/* fadd - fadd. */
+PPC_OP(fadd)
+{
+ FT0 += FT1;
+ RETURN();
}
-#define PPC_ILD_OP(name, op) \
-PPC_OP(l##name##_z) \
-{ \
- T1 = op(SPARAM(1)); \
- RETURN(); \
-} \
-PPC_OP(l##name) \
-{ \
- T0 += SPARAM(1); \
- T1 = op(T0); \
- RETURN(); \
-} \
-PPC_ILD_OPX(name, op)
-
-PPC_ILD_OP(bz, ld8);
-PPC_ILD_OP(ha, ld16x);
-PPC_ILD_OP(hz, ld16);
-PPC_ILD_OP(wz, ld32);
-
-/*** Integer store ***/
-#define PPC_IST_OPX(name, op) \
-PPC_OP(st##name##x_z) \
-{ \
- op(T0, T1); \
- RETURN(); \
-} \
-PPC_OP(st##name##x) \
-{ \
- T0 += T1; \
- op(T0, T2); \
- RETURN(); \
+/* fadds - fadds. */
+PPC_OP(fadds)
+{
+ FTS0 += FTS1;
+ RETURN();
}
-#define PPC_IST_OP(name, op) \
-PPC_OP(st##name##_z) \
-{ \
- op(SPARAM(1), T0); \
- RETURN(); \
-} \
-PPC_OP(st##name) \
-{ \
- T0 += SPARAM(1); \
- op(T0, T1); \
- RETURN(); \
-} \
-PPC_IST_OPX(name, op);
+/* fsub - fsub. */
+PPC_OP(fsub)
+{
+ FT0 -= FT1;
+ RETURN();
+}
-PPC_IST_OP(b, st8);
-PPC_IST_OP(h, st16);
-PPC_IST_OP(w, st32);
+/* fsubs - fsubs. */
+PPC_OP(fsubs)
+{
+ FTS0 -= FTS1;
+ RETURN();
+}
-/*** Integer load and store with byte reverse ***/
-PPC_ILD_OPX(hbr, ld16r);
-PPC_ILD_OPX(wbr, ld32r);
-PPC_IST_OPX(hbr, st16r);
-PPC_IST_OPX(wbr, st32r);
+/* fmul - fmul. */
+PPC_OP(fmul)
+{
+ FT0 *= FT1;
+ RETURN();
+}
-/*** Integer load and store multiple ***/
-PPC_OP(lmw)
+/* fmuls - fmuls. */
+PPC_OP(fmuls)
{
- do_lmw(PARAM(1), SPARAM(2) + T0);
+ FTS0 *= FTS1;
RETURN();
}
-PPC_OP(stmw)
+/* fdiv - fdiv. */
+PPC_OP(fdiv)
{
- do_stmw(PARAM(1), SPARAM(2) + T0);
+ FT0 /= FT1;
RETURN();
}
-/*** Integer load and store strings ***/
-PPC_OP(lswi)
+/* fdivs - fdivs. */
+PPC_OP(fdivs)
{
- do_lsw(PARAM(1), PARAM(2), T0);
+ FTS0 /= FTS1;
RETURN();
}
-PPC_OP(lswx)
+/* fsqrt - fsqrt. */
+PPC_OP(fsqrt)
{
- do_lsw(PARAM(1), T0, T1 + T2);
+ do_fsqrt();
RETURN();
}
-PPC_OP(stswi_z)
+/* fsqrts - fsqrts. */
+PPC_OP(fsqrts)
{
- do_stsw(PARAM(1), PARAM(2), 0);
+ do_fsqrts();
RETURN();
}
-PPC_OP(stswi)
+/* fres - fres. */
+PPC_OP(fres)
{
- do_stsw(PARAM(1), PARAM(2), T0);
+ do_fres();
RETURN();
}
-PPC_OP(stswx_z)
+/* frsqrte - frsqrte. */
+PPC_OP(frsqrte)
{
- do_stsw(PARAM(1), T0, T1);
+ do_fsqrte();
RETURN();
}
-PPC_OP(stswx)
+/* fsel - fsel. */
+PPC_OP(fsel)
{
- do_stsw(PARAM(1), T0, T1 + T2);
+ do_fsel();
RETURN();
}
-/* SPR */
-PPC_OP(load_spr)
+/*** Floating-Point multiply-and-add ***/
+/* fmadd - fmadd. */
+PPC_OP(fmadd)
{
- T0 = regs->spr[PARAM(1)];
+ FT0 = (FT0 * FT1) + FT2;
+ RETURN();
}
-PPC_OP(store_spr)
+/* fmadds - fmadds. */
+PPC_OP(fmadds)
{
- regs->spr[PARAM(1)] = T0;
+ FTS0 = (FTS0 * FTS1) + FTS2;
+ RETURN();
}
-/* FPSCR */
-PPC_OP(load_fpscr)
+/* fmsub - fmsub. */
+PPC_OP(fmsub)
{
- T0 = do_load_fpscr();
+ FT0 = (FT0 * FT1) - FT2;
+ RETURN();
}
-PPC_OP(store_fpscr)
+/* fmsubs - fmsubs. */
+PPC_OP(fmsubs)
{
- do_store_fpscr(PARAM(1), T0);
+ FTS0 = (FTS0 * FTS1) - FTS2;
+ RETURN();
}
-/*** Floating-point store ***/
+/* fnmadd - fnmadd. - fnmadds - fnmadds. */
+PPC_OP(fnmadd)
+{
+ do_fnmadd();
+ RETURN();
+}
-static inline uint32_t dtos(uint64_t f)
+/* fnmadds - fnmadds. */
+PPC_OP(fnmadds)
{
- unsigned int e, m, s;
- e = (((f >> 52) & 0x7ff) - 1022) + 126;
- s = (f >> 63);
- m = (f >> 29);
- return (s << 31) | (e << 23) | m;
+ do_fnmadds();
+ RETURN();
}
-static inline uint64_t stod(uint32_t f)
+/* fnmsub - fnmsub. */
+PPC_OP(fnmsub)
{
- unsigned int e, m, s;
- e = ((f >> 23) & 0xff) - 126 + 1022;
- s = f >> 31;
- m = f & ((1 << 23) - 1);
- return ((uint64_t)s << 63) | ((uint64_t)e << 52) | ((uint64_t)m << 29);
+ do_fnmsub();
+ RETURN();
}
-PPC_OP(stfd_z_FT0)
+/* fnmsubs - fnmsubs. */
+PPC_OP(fnmsubs)
{
- st64(SPARAM(1), FT0);
+ do_fnmsubs();
+ RETURN();
}
-PPC_OP(stfd_FT0)
+/*** Floating-Point round & convert ***/
+/* frsp - frsp. */
+PPC_OP(frsp)
{
- T0 += SPARAM(1);
- st64(T0, FT0);
+ FT0 = FTS0;
+ RETURN();
}
-PPC_OP(stfdx_z_FT0)
+/* fctiw - fctiw. */
+PPC_OP(fctiw)
{
- st64(T0, FT0);
+ do_fctiw();
+ RETURN();
}
-PPC_OP(stfdx_FT0)
+/* fctiwz - fctiwz. */
+PPC_OP(fctiwz)
{
- T0 += T1;
- st64(T0, FT0);
+ do_fctiwz();
+ RETURN();
}
-PPC_OP(stfs_z_FT0)
+/*** Floating-Point compare ***/
+/* fcmpu */
+PPC_OP(fcmpu)
{
- st32(SPARAM(1), dtos(FT0));
+ do_fcmpu();
+ RETURN();
}
-PPC_OP(stfs_FT0)
+/* fcmpo */
+PPC_OP(fcmpo)
{
- T0 += SPARAM(1);
- st32(T0, dtos(FT0));
+ do_fcmpo();
+ RETURN();
}
-PPC_OP(stfsx_z_FT0)
+/*** Floating-point move ***/
+/* fabs */
+PPC_OP(fabs)
{
- st32(T0, dtos(FT0));
+ do_fabs();
+ RETURN();
}
-PPC_OP(stfsx_FT0)
+/* fnabs */
+PPC_OP(fnabs)
{
- T0 += T1;
- st32(T0, dtos(FT0));
+ do_fnabs();
+ RETURN();
}
-/*** Floating-point load ***/
-PPC_OP(lfd_z_FT0)
+/* fneg */
+PPC_OP(fneg)
{
- FT0 = ld64(SPARAM(1));
+ FT0 = -FT0;
+ RETURN();
}
-PPC_OP(lfd_FT0)
+/* Load and store */
+#define MEMSUFFIX _raw
+#include "op_mem.h"
+#if !defined(CONFIG_USER_ONLY)
+#define MEMSUFFIX _user
+#include "op_mem.h"
+
+#define MEMSUFFIX _kernel
+#include "op_mem.h"
+#endif
+
+/* Special op to check and maybe clear reservation */
+PPC_OP(check_reservation)
{
- T0 += SPARAM(1);
- FT0 = ld64(T0);
+ do_check_reservation();
+ RETURN();
}
-PPC_OP(lfdx_z_FT0)
+/* Return from interrupt */
+PPC_OP(rfi)
{
- FT0 = ld64(T0);
+ regs->nip = regs->spr[SRR0] & ~0x00000003;
+#if 1 // TRY
+ T0 = regs->spr[SRR1] & ~0xFFF00000;
+#else
+ T0 = regs->spr[SRR1] & ~0xFFFF0000;
+#endif
+ do_store_msr();
+#if defined (DEBUG_OP)
+ dump_rfi();
+#endif
+ // do_tlbia();
+ do_raise_exception(EXCP_RFI);
+ RETURN();
}
-PPC_OP(lfdx_FT0)
+/* Trap word */
+PPC_OP(tw)
{
- T0 += T1;
- FT0 = ld64(T0);
+ if ((Ts0 < Ts1 && (PARAM(1) & 0x10)) ||
+ (Ts0 > Ts1 && (PARAM(1) & 0x08)) ||
+ (Ts0 == Ts1 && (PARAM(1) & 0x04)) ||
+ (T0 < T1 && (PARAM(1) & 0x02)) ||
+ (T0 > T1 && (PARAM(1) & 0x01)))
+ do_raise_exception_err(EXCP_PROGRAM, EXCP_TRAP);
+ RETURN();
}
-PPC_OP(lfs_z_FT0)
+PPC_OP(twi)
{
- FT0 = stod(ld32(SPARAM(1)));
+ if ((Ts0 < SPARAM(1) && (PARAM(2) & 0x10)) ||
+ (Ts0 > SPARAM(1) && (PARAM(2) & 0x08)) ||
+ (Ts0 == SPARAM(1) && (PARAM(2) & 0x04)) ||
+ (T0 < (uint32_t)SPARAM(1) && (PARAM(2) & 0x02)) ||
+ (T0 > (uint32_t)SPARAM(1) && (PARAM(2) & 0x01)))
+ do_raise_exception_err(EXCP_PROGRAM, EXCP_TRAP);
+ RETURN();
}
-PPC_OP(lfs_FT0)
+/* Instruction cache block invalidate */
+PPC_OP(icbi)
{
- T0 += SPARAM(1);
- FT0 = stod(ld32(T0));
+ do_icbi();
+ RETURN();
}
-PPC_OP(lfsx_z_FT0)
+/* tlbia */
+PPC_OP(tlbia)
{
- FT0 = stod(ld32(T0));
+ do_tlbia();
+ RETURN();
}
-PPC_OP(lfsx_FT0)
+/* tlbie */
+PPC_OP(tlbie)
{
- T0 += T1;
- FT0 = stod(ld32(T0));
+ do_tlbie();
+ RETURN();
}
projects / qemu / blobdiff