halt state support for ppc

[qemu] / target-ppc / helper.c

diff --git a/target-ppc/helper.c b/target-ppc/helper.c
index c9693c8..ff1355c 100644 (file)
--- a/target-ppc/helper.c
+++ b/target-ppc/helper.c
@@ -36,6 +36,32 @@
 /*****************************************************************************/
 /* PowerPC MMU emulation */
 
+#if defined(CONFIG_USER_ONLY) 
+int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
+                              int is_user, int is_softmmu)
+{
+    int exception, error_code;
+    
+    if (rw == 2) {
+        exception = EXCP_ISI;
+        error_code = 0;
+    } else {
+        exception = EXCP_DSI;
+        error_code = 0;
+        if (rw)
+            error_code |= 0x02000000;
+        env->spr[SPR_DAR] = address;
+        env->spr[SPR_DSISR] = error_code;
+    }
+    env->exception_index = exception;
+    env->error_code = error_code;
+    return 1;
+}
+target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
+{
+    return addr;
+}
+#else
 /* Perform BAT hit & translation */
 static int get_bat (CPUState *env, uint32_t *real, int *prot,
                     uint32_t virtual, int rw, int type)
@@ -355,8 +381,8 @@ static int get_segment (CPUState *env, uint32_t *real, int *prot,
     return ret;
 }
 
-int get_physical_address (CPUState *env, uint32_t *physical, int *prot,
-                          uint32_t address, int rw, int access_type)
+static int get_physical_address (CPUState *env, uint32_t *physical, int *prot,
+                                 uint32_t address, int rw, int access_type)
 {
     int ret;
 #if 0
@@ -387,12 +413,6 @@ int get_physical_address (CPUState *env, uint32_t *physical, int *prot,
     return ret;
 }
 
-#if defined(CONFIG_USER_ONLY) 
-target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
-{
-    return addr;
-}
-#else
 target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
 {
     uint32_t phys_addr;
@@ -402,7 +422,6 @@ target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
         return -1;
     return phys_addr;
 }
-#endif
 
 /* Perform address translation */
 int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
@@ -523,6 +542,7 @@ int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
     }
     return ret;
 }
+#endif
 
 /*****************************************************************************/
 /* BATs management */
@@ -786,7 +806,7 @@ void do_compute_hflags (CPUPPCState *env)
 }
 
 void do_store_msr (CPUPPCState *env, target_ulong value)
-    {
+{
     value &= env->msr_mask;
     if (((value >> MSR_IR) & 1) != msr_ir ||
         ((value >> MSR_DR) & 1) != msr_dr) {
@@ -826,6 +846,11 @@ void do_store_msr (CPUPPCState *env, target_ulong value)
     msr_ri  = (value >> MSR_RI)  & 1;
     msr_le  = (value >> MSR_LE)  & 1;
     do_compute_hflags(env);
+    if (msr_pow) {
+        /* power save: exit cpu loop */
+        env->exception_index = EXCP_HLT;
+        cpu_loop_exit();
+    }
 }
 
 float64 do_load_fpscr (CPUPPCState *env)
@@ -1416,15 +1441,5 @@ void do_interrupt (CPUState *env)
     /* Jump to handler */
     env->nip = excp;
     env->exception_index = EXCP_NONE;
-#if 0
-    /* ensure that no TB jump will be modified as
-       the program flow was changed */
-#ifdef __sparc__
-    tmp_T0 = 0;
-#else
-    T0 = 0;
-#endif
-#endif
-    env->interrupt_request |= CPU_INTERRUPT_EXITTB;
 }
 #endif /* !CONFIG_USER_ONLY */