/*****************************************************************************/
/* PPC MMU emulation */
-int cpu_ppc_handle_mmu_fault (CPUState *env, uint32_t address, int rw,
- int is_user, int is_softmmu);
/* Perform BAT hit & translation */
static int get_bat (CPUState *env, uint32_t *real, int *prot,
int ret = -1; /* No entry found */
for (i = 0; i < 8; i++) {
- pte0 = ldl_raw(phys_ram_base + base + (i * 8));
- pte1 = ldl_raw(phys_ram_base + base + (i * 8) + 4);
+ pte0 = ldl_phys(base + (i * 8));
+ pte1 = ldl_phys(base + (i * 8) + 4);
#if defined (DEBUG_MMU)
if (loglevel > 0) {
fprintf(logfile, "Load pte from 0x%08x => 0x%08x 0x%08x "
}
}
if (store) {
- stl_raw(phys_ram_base + base + (good * 8) + 4, keep);
+ stl_phys_notdirty(base + (good * 8) + 4, keep);
}
}
NULL, it means that the function was called in C code (i.e. not
from generated code or from helper.c) */
/* XXX: fix it to restore all registers */
-void tlb_fill(unsigned long addr, int is_write, int is_user, void *retaddr)
+void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr)
{
TranslationBlock *tb;
CPUState *saved_env;
generated code */
saved_env = env;
env = cpu_single_env;
+#if 0
{
unsigned long tlb_addrr, tlb_addrw;
int index;
index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
tlb_addrr = env->tlb_read[is_user][index].address;
tlb_addrw = env->tlb_write[is_user][index].address;
-#if 0
if (loglevel) {
fprintf(logfile,
"%s 1 %p %p idx=%d addr=0x%08lx tbl_addr=0x%08lx 0x%08lx "
tlb_addrr, tlb_addrw, addr & TARGET_PAGE_MASK,
tlb_addrr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
}
-#endif
}
+#endif
ret = cpu_ppc_handle_mmu_fault(env, addr, is_write, is_user, 1);
if (ret) {
if (retaddr) {
}
do_raise_exception_err(env->exception_index, env->error_code);
}
+#if 0
{
unsigned long tlb_addrr, tlb_addrw;
int index;
index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
tlb_addrr = env->tlb_read[is_user][index].address;
tlb_addrw = env->tlb_write[is_user][index].address;
-#if 0
printf("%s 2 %p %p idx=%d addr=0x%08lx tbl_addr=0x%08lx 0x%08lx "
"(0x%08lx 0x%08lx)\n", __func__, env,
&env->tlb_read[is_user][index], index, addr,
tlb_addrr, tlb_addrw, addr & TARGET_PAGE_MASK,
tlb_addrr & (TARGET_PAGE_MASK | TLB_INVALID_MASK));
-#endif
}
+#endif
env = saved_env;
}
int access_type;
int ret = 0;
-// printf("%s 0\n", __func__);
- access_type = env->access_type;
+ if (rw == 2) {
+ /* code access */
+ rw = 0;
+ access_type = ACCESS_CODE;
+ } else {
+ /* data access */
+ /* XXX: put correct access by using cpu_restore_state()
+ correctly */
+ access_type = ACCESS_INT;
+ // access_type = env->access_type;
+ }
if (env->user_mode_only) {
/* user mode only emulation */
ret = -2;
goto do_fault;
}
- /* NASTY BUG workaround */
- if (access_type == ACCESS_CODE && rw) {
- printf("%s: ERROR WRITE CODE ACCESS\n", __func__);
- access_type = ACCESS_INT;
- }
ret = get_physical_address(env, &physical, &prot,
address, rw, access_type);
if (ret == 0) {
do_fault:
#if defined (DEBUG_MMU)
if (loglevel > 0)
- cpu_ppc_dump_state(env, logfile, 0);
+ cpu_dump_state(env, logfile, fprintf, 0);
#endif
if (access_type == ACCESS_CODE) {
exception = EXCP_ISI;
env->error_code = error_code;
ret = 1;
}
-
return ret;
}
msr_dr = (value >> MSR_DR) & 0x01;
msr_ri = (value >> MSR_RI) & 0x01;
msr_le = (value >> MSR_LE) & 0x01;
+ /* XXX: should enter PM state if msr_pow has been set */
}
+#if defined (CONFIG_USER_ONLY)
void do_interrupt (CPUState *env)
{
-#if defined (CONFIG_USER_ONLY)
- env->exception_index |= 0x100;
+ env->exception_index = -1;
+}
#else
+void do_interrupt (CPUState *env)
+{
uint32_t msr;
- int excp = env->exception_index;
+ int excp;
+ excp = env->exception_index;
msr = _load_msr(env);
#if defined (DEBUG_EXCEPTIONS)
if ((excp == EXCP_PROGRAM || excp == EXCP_DSI) && msr_pr == 1)
if (loglevel > 0) {
fprintf(logfile, "Raise exception at 0x%08x => 0x%08x (%02x)\n",
env->nip, excp << 8, env->error_code);
- }
+ }
if (loglevel > 0)
- cpu_ppc_dump_state(env, logfile, 0);
+ cpu_dump_state(env, logfile, fprintf, 0);
}
#endif
+ if (loglevel & CPU_LOG_INT) {
+ fprintf(logfile, "Raise exception at 0x%08x => 0x%08x (%02x)\n",
+ env->nip, excp << 8, env->error_code);
+ }
/* Generate informations in save/restore registers */
switch (excp) {
case EXCP_OFCALL:
/* Store exception cause */
/* Get rS/rD and rA from faulting opcode */
env->spr[DSISR] |=
- (ldl_code((void *)(env->nip - 4)) & 0x03FF0000) >> 16;
+ (ldl_code((env->nip - 4)) & 0x03FF0000) >> 16;
/* data location address has been stored
* when the fault has been detected
*/
}
goto store_next;
case EXCP_SYSCALL:
-#if defined (DEBUG_EXCEPTIONS)
- if (msr_pr) {
- if (loglevel) {
- fprintf(logfile, "syscall %d 0x%08x 0x%08x 0x%08x 0x%08x\n",
- env->gpr[0], env->gpr[3], env->gpr[4],
- env->gpr[5], env->gpr[6]);
- } else {
- printf("syscall %d from 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
- env->gpr[0], env->nip, env->gpr[3], env->gpr[4],
- env->gpr[5], env->gpr[6]);
- }
- }
-#endif
+ if (loglevel & CPU_LOG_INT) {
+ fprintf(logfile, "syscall %d 0x%08x 0x%08x 0x%08x 0x%08x\n",
+ env->gpr[0], env->gpr[3], env->gpr[4],
+ env->gpr[5], env->gpr[6]);
+ if (env->gpr[0] == 4 && env->gpr[3] == 1) {
+ int len, addr, i;
+ uint8_t c;
+
+ fprintf(logfile, "write: ");
+ addr = env->gpr[4];
+ len = env->gpr[5];
+ if (len > 64)
+ len = 64;
+ for(i = 0; i < len; i++) {
+ c = 0;
+ cpu_memory_rw_debug(env, addr + i, &c, 1, 0);
+ if (c < 32 || c > 126)
+ c = '.';
+ fprintf(logfile, "%c", c);
+ }
+ fprintf(logfile, "\n");
+ }
+ }
goto store_next;
case EXCP_TRACE:
goto store_next;
#else
T0 = 0;
#endif
-#endif
env->exception_index = -1;
}
+#endif /* !CONFIG_USER_ONLY */
projects / qemu / blobdiff