/*
- * PPC emulation definitions for qemu.
- *
- * Copyright (c) 2003 Jocelyn Mayer
+ * PowerPC emulation definitions for qemu.
+ *
+ * Copyright (c) 2003-2007 Jocelyn Mayer
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
#if !defined (__PPC_H__)
#define __PPC_H__
-#include "dyngen-exec.h"
-
-register struct CPUPPCState *env asm(AREG0);
-register uint32_t T0 asm(AREG1);
-register uint32_t T1 asm(AREG2);
-register uint32_t T2 asm(AREG3);
+#include "config.h"
-#define PARAM(n) ((uint32_t)PARAM##n)
-#define SPARAM(n) ((int32_t)PARAM##n)
-#define FT0 (env->ft0)
-#define FT1 (env->ft1)
-#define FT2 (env->ft2)
-#define FTS0 ((float)env->ft0)
-#define FTS1 ((float)env->ft1)
-#define FTS2 ((float)env->ft2)
-
-#define RETURN() __asm__ __volatile__("");
+#include "dyngen-exec.h"
#include "cpu.h"
#include "exec-all.h"
-static inline uint8_t ld8 (uint32_t EA)
-{
- return *((uint8_t *)EA);
-}
-
-static inline uint16_t ld16 (uint32_t EA)
-{
- return __be16_to_cpu(*((uint16_t *)EA));
-}
-
-static inline uint16_t ld16r (uint32_t EA)
-{
- return __le16_to_cpu(*((uint16_t *)EA));
-}
-
-static inline uint32_t ld32 (uint32_t EA)
-{
- return __be32_to_cpu(*((uint32_t *)EA));
-}
-
-static inline uint32_t ld32r (uint32_t EA)
-{
- return __le32_to_cpu(*((uint32_t *)EA));
-}
+/* For normal operations, precise emulation should not be needed */
+//#define USE_PRECISE_EMULATION 1
+#define USE_PRECISE_EMULATION 0
-static inline uint64_t ld64 (uint32_t EA)
-{
- return __be64_to_cpu(*((uint64_t *)EA));
-}
+register struct CPUPPCState *env asm(AREG0);
+#if TARGET_LONG_BITS > HOST_LONG_BITS
+/* no registers can be used */
+#define T0 (env->t0)
+#define T1 (env->t1)
+#define T2 (env->t2)
+#define TDX "%016" PRIx64
+#else
+register unsigned long T0 asm(AREG1);
+register unsigned long T1 asm(AREG2);
+register unsigned long T2 asm(AREG3);
+#define TDX "%016lx"
+#endif
+/* We may, sometime, need 64 bits registers on 32 bits targets */
+#if (HOST_LONG_BITS == 32)
+/* no registers can be used */
+#define T0_64 (env->t0)
+#define T1_64 (env->t1)
+#define T2_64 (env->t2)
+#else
+#define T0_64 T0
+#define T1_64 T1
+#define T2_64 T2
+#endif
+/* Provision for Altivec */
+#define AVR0 (env->avr0)
+#define AVR1 (env->avr1)
+#define AVR2 (env->avr2)
-static inline uint64_t ld64r (uint32_t EA)
-{
- return __le64_to_cpu(*((uint64_t *)EA));
-}
+#define FT0 (env->ft0)
+#define FT1 (env->ft1)
+#define FT2 (env->ft2)
-static inline void st8 (uint32_t EA, uint8_t data)
-{
- *((uint8_t *)EA) = data;
-}
+#if defined (DEBUG_OP)
+# define RETURN() __asm__ __volatile__("nop" : : : "memory");
+#else
+# define RETURN() __asm__ __volatile__("" : : : "memory");
+#endif
-static inline void st16 (uint32_t EA, uint16_t data)
+static always_inline target_ulong rotl8 (target_ulong i, int n)
{
- *((uint16_t *)EA) = __cpu_to_be16(data);
+ return (((uint8_t)i << n) | ((uint8_t)i >> (8 - n)));
}
-static inline void st16r (uint32_t EA, uint16_t data)
+static always_inline target_ulong rotl16 (target_ulong i, int n)
{
- *((uint16_t *)EA) = __cpu_to_le16(data);
+ return (((uint16_t)i << n) | ((uint16_t)i >> (16 - n)));
}
-static inline void st32 (uint32_t EA, uint32_t data)
+static always_inline target_ulong rotl32 (target_ulong i, int n)
{
- *((uint32_t *)EA) = __cpu_to_be32(data);
+ return (((uint32_t)i << n) | ((uint32_t)i >> (32 - n)));
}
-static inline void st32r (uint32_t EA, uint32_t data)
+#if defined(TARGET_PPC64)
+static always_inline target_ulong rotl64 (target_ulong i, int n)
{
- *((uint32_t *)EA) = __cpu_to_le32(data);
+ return (((uint64_t)i << n) | ((uint64_t)i >> (64 - n)));
}
+#endif
-static inline void st64 (uint32_t EA, uint64_t data)
-{
- *((uint64_t *)EA) = __cpu_to_be64(data);
-}
+#if !defined(CONFIG_USER_ONLY)
+#include "softmmu_exec.h"
+#endif /* !defined(CONFIG_USER_ONLY) */
-static inline void st64r (uint32_t EA, uint64_t data)
-{
- *((uint64_t *)EA) = __cpu_to_le64(data);
-}
+void do_raise_exception_err (uint32_t exception, int error_code);
+void do_raise_exception (uint32_t exception);
-static inline void set_CRn(int n, uint8_t value)
-{
- env->crf[n] = value;
-}
+int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong vaddr,
+ int rw, int access_type);
-static inline void set_carry (void)
-{
- xer_ca = 1;
-}
+void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code,
+ target_ulong pte0, target_ulong pte1);
-static inline void reset_carry (void)
+static always_inline void env_to_regs (void)
{
- xer_ca = 0;
}
-static inline void set_overflow (void)
+static always_inline void regs_to_env (void)
{
- xer_so = 1;
- xer_ov = 1;
}
-static inline void reset_overflow (void)
-{
- xer_ov = 0;
-}
+int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
+ int mmu_idx, int is_softmmu);
-static inline uint32_t rotl (uint32_t i, int n)
+static always_inline int cpu_halted (CPUState *env)
{
- return ((i << n) | (i >> (32 - n)));
+ if (!env->halted)
+ return 0;
+ if (msr_ee && (env->interrupt_request & CPU_INTERRUPT_HARD)) {
+ env->halted = 0;
+ return 0;
+ }
+ return EXCP_HALTED;
}
-void raise_exception (int exception_index);
-void raise_exception_err (int exception_index, int error_code);
-
-uint32_t do_load_cr (void);
-void do_store_cr (uint32_t crn, uint32_t value);
-uint32_t do_load_xer (void);
-void do_store_xer (uint32_t value);
-uint32_t do_load_msr (void);
-void do_store_msr (uint32_t msr_value);
-void do_load_fpscr (void);
-void do_store_fpscr (uint32_t mask);
-
-int32_t do_sraw(int32_t Ta, uint32_t Tb);
-void do_lmw (int reg, uint32_t src);
-void do_stmw (int reg, uint32_t dest);
-void do_lsw (uint32_t reg, int count, uint32_t src);
-void do_stsw (uint32_t reg, int count, uint32_t dest);
-
-void do_dcbz (void);
-void do_icbi (void);
-
#endif /* !defined (__PPC_H__) */
projects / qemu / blobdiff