/*
* PowerPC emulation definitions for qemu.
- *
+ *
* Copyright (c) 2003-2007 Jocelyn Mayer
*
* This library is free software; you can redistribute it and/or
#define T0 (env->t0)
#define T1 (env->t1)
#define T2 (env->t2)
+#define TDX "%016" PRIx64
#else
register unsigned long T0 asm(AREG1);
register unsigned long T1 asm(AREG2);
register unsigned long T2 asm(AREG3);
+#define TDX "%016lx"
#endif
-/* We may, sometime, need 64 bits registers on 32 bits target */
-#if defined(TARGET_PPC64) || defined(TARGET_PPCSPE) || (HOST_LONG_BITS == 64)
-#define T0_64 T0
-#define T1_64 T1
-#define T2_64 T2
-#else
+/* We may, sometime, need 64 bits registers on 32 bits targets */
+#if (HOST_LONG_BITS == 32)
/* no registers can be used */
#define T0_64 (env->t0)
#define T1_64 (env->t1)
#define T2_64 (env->t2)
+#else
+#define T0_64 T0
+#define T1_64 T1
+#define T2_64 T2
#endif
/* Provision for Altivec */
-#define T0_avr (env->t0_avr)
-#define T1_avr (env->t1_avr)
-#define T2_avr (env->t2_avr)
-
-/* XXX: to clean: remove this mess */
-#define PARAM(n) ((uint32_t)PARAM##n)
-#define SPARAM(n) ((int32_t)PARAM##n)
+#define AVR0 (env->avr0)
+#define AVR1 (env->avr1)
+#define AVR2 (env->avr2)
#define FT0 (env->ft0)
#define FT1 (env->ft1)
# define RETURN() __asm__ __volatile__("" : : : "memory");
#endif
-static inline target_ulong rotl8 (target_ulong i, int n)
+static always_inline target_ulong rotl8 (target_ulong i, int n)
{
return (((uint8_t)i << n) | ((uint8_t)i >> (8 - n)));
}
-static inline target_ulong rotl16 (target_ulong i, int n)
+static always_inline target_ulong rotl16 (target_ulong i, int n)
{
return (((uint16_t)i << n) | ((uint16_t)i >> (16 - n)));
}
-static inline target_ulong rotl32 (target_ulong i, int n)
+static always_inline target_ulong rotl32 (target_ulong i, int n)
{
return (((uint32_t)i << n) | ((uint32_t)i >> (32 - n)));
}
#if defined(TARGET_PPC64)
-static inline target_ulong rotl64 (target_ulong i, int n)
+static always_inline target_ulong rotl64 (target_ulong i, int n)
{
return (((uint64_t)i << n) | ((uint64_t)i >> (64 - n)));
}
void do_raise_exception (uint32_t exception);
int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong vaddr,
- int rw, int access_type, int check_BATs);
+ int rw, int access_type);
-void ppc6xx_tlb_invalidate_all (CPUState *env);
-void ppc6xx_tlb_invalidate_virt (CPUState *env, target_ulong eaddr,
- int is_code);
void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code,
target_ulong pte0, target_ulong pte1);
-static inline void env_to_regs(void)
+static always_inline void env_to_regs (void)
{
}
-static inline void regs_to_env(void)
+static always_inline void regs_to_env (void)
{
}
int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
- int is_user, int is_softmmu);
+ int mmu_idx, int is_softmmu);
+
+static always_inline int cpu_halted (CPUState *env)
+{
+ if (!env->halted)
+ return 0;
+ if (msr_ee && (env->interrupt_request & CPU_INTERRUPT_HARD)) {
+ env->halted = 0;
+ return 0;
+ }
+ return EXCP_HALTED;
+}
#endif /* !defined (__PPC_H__) */