qemu_put signedness fixes, by Andre Przywara.

[qemu] / target-ppc / exec.h

diff --git a/target-ppc/exec.h b/target-ppc/exec.h
index 5abcee0..76fdb0b 100644 (file)
--- a/target-ppc/exec.h
+++ b/target-ppc/exec.h
@@ -37,13 +37,15 @@ register struct CPUPPCState *env asm(AREG0);
 #define T0 (env->t0)
 #define T1 (env->t1)
 #define T2 (env->t2)
+#define TDX "%016" PRIx64
 #else
 register unsigned long T0 asm(AREG1);
 register unsigned long T1 asm(AREG2);
 register unsigned long T2 asm(AREG3);
+#define TDX "%016lx"
 #endif
-/* We may, sometime, need 64 bits registers on 32 bits target */
-#if TARGET_GPR_BITS > HOST_LONG_BITS
+/* We may, sometime, need 64 bits registers on 32 bits targets */
+#if (HOST_LONG_BITS == 32)
 /* no registers can be used */
 #define T0_64 (env->t0)
 #define T1_64 (env->t1)
@@ -98,7 +100,7 @@ void do_raise_exception_err (uint32_t exception, int error_code);
 void do_raise_exception (uint32_t exception);
 
 int get_physical_address (CPUState *env, mmu_ctx_t *ctx, target_ulong vaddr,
-                          int rw, int access_type, int check_BATs);
+                          int rw, int access_type);
 
 void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code,
                        target_ulong pte0, target_ulong pte1);