removed stdout reference (not portable)

[qemu] / target-ppc / cpu.h

diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index e6cb094..99ed1bd 100644 (file)
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -43,15 +43,6 @@ static inline int32_t s_ext16 (uint16_t value)
     return *tmp;
 }
 
-/* 24 to 32 bits */
-static inline int32_t s_ext24 (uint32_t value)
-{
-    uint16_t utmp = (value >> 8) & 0xFFFF;
-    int16_t *tmp = &utmp;
-
-    return (*tmp << 8) | (value & 0xFF);
-}
-
 #include "config.h"
 #include <setjmp.h>
 
@@ -74,10 +65,16 @@ enum {
 
 #define PPC_COMMON  (PPC_INTEGER | PPC_FLOAT | PPC_FLOW | PPC_MEM |           \
                      PPC_RES | PPC_CACHE | PPC_MISC | PPC_SEGMENT)
+/* PPC 604 */
+#define PPC_604 (PPC_INTEGER | PPC_FLOAT | PPC_FLOW | PPC_MEM |               \
+                 PPC_RES | PPC_CACHE | PPC_MISC | PPC_EXTERN | PPC_SEGMENT    \
+                 PPC_MEM_OPT)
 /* PPC 740/745/750/755 (aka G3) has external access instructions */
 #define PPC_750 (PPC_INTEGER | PPC_FLOAT | PPC_FLOW | PPC_MEM |               \
                  PPC_RES | PPC_CACHE | PPC_MISC | PPC_EXTERN | PPC_SEGMENT)
 
+typedef struct ppc_tb_t ppc_tb_t;
+
 /* Supervisor mode registers */
 /* Machine state register */
 #define MSR_POW 18
@@ -134,10 +131,6 @@ typedef struct CPUPPCState {
     /* special purpose registers */
     uint32_t lr;
     uint32_t ctr;
-    /* Time base */
-    uint32_t tb[2];
-    /* decrementer */
-    uint32_t decr;
     /* BATs */
     uint32_t DBAT[2][8];
     uint32_t IBAT[2][8];
@@ -154,13 +147,6 @@ typedef struct CPUPPCState {
     int error_code;
     int access_type; /* when a memory exception occurs, the access
                         type is stored here */
-#if 0 /* TODO */
-    uint32_t pending_exceptions; /* For external & decr exception,
-                                 * that can be delayed */
-#else
-    uint32_t exceptions; /* exception queue */
-    uint32_t errors[32];
-#endif
     int user_mode_only; /* user mode only simulation */
     struct TranslationBlock *current_tb; /* currently executing TB */
     /* soft mmu support */
@@ -178,8 +164,13 @@ typedef struct CPUPPCState {
     /* ice debug support */
     uint32_t breakpoints[MAX_BREAKPOINTS];
     int nb_breakpoints;
-    int brkstate;
-    int singlestep_enabled;
+    int singlestep_enabled; /* XXX: should use CPU single step mode instead */
+
+    /* Time base and decrementer */
+    ppc_tb_t *tb_env;
+
+    /* Power management */
+    int power_mode;
 
     /* user data */
     void *opaque;
@@ -206,10 +197,17 @@ void _store_xer (CPUPPCState *env, uint32_t value);
 uint32_t _load_msr (CPUPPCState *env);
 void _store_msr (CPUPPCState *env, uint32_t value);
 
-void PPC_init_hw (uint32_t mem_size,
-                  uint32_t kernel_addr, uint32_t kernel_size,
-                  uint32_t stack_addr, int boot_device,
-                 const unsigned char *initrd_file);
+int cpu_ppc_register (CPUPPCState *env, uint32_t pvr);
+
+/* Time-base and decrementer management */
+#ifndef NO_CPU_IO_DEFS
+uint32_t cpu_ppc_load_tbl (CPUPPCState *env);
+uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
+void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
+void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
+uint32_t cpu_ppc_load_decr (CPUPPCState *env);
+void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
+#endif
 
 #define TARGET_PAGE_BITS 12
 #include "cpu-all.h"
@@ -234,7 +232,10 @@ void PPC_init_hw (uint32_t mem_size,
 #define xer_ca env->xer[1]
 #define xer_bc env->xer[0]
 
+#define MQ     SPR_ENCODE(0)
 #define XER    SPR_ENCODE(1)
+#define RTCUR  SPR_ENCODE(4)
+#define RTCLR  SPR_ENCODE(5)
 #define LR     SPR_ENCODE(8)
 #define CTR    SPR_ENCODE(9)
 /* VEA mode SPR */
@@ -243,6 +244,8 @@ void PPC_init_hw (uint32_t mem_size,
 /* supervisor mode SPR */
 #define DSISR  SPR_ENCODE(18)
 #define DAR    SPR_ENCODE(19)
+#define RTCUW  SPR_ENCODE(20)
+#define RTCLW  SPR_ENCODE(21)
 #define DECR   SPR_ENCODE(22)
 #define SDR1   SPR_ENCODE(25)
 #define SRR0   SPR_ENCODE(26)
@@ -292,14 +295,50 @@ void PPC_init_hw (uint32_t mem_size,
 #define DBAT6L SPR_ENCODE(573)
 #define DBAT7U SPR_ENCODE(574)
 #define DBAT7L SPR_ENCODE(575)
+#define UMMCR0 SPR_ENCODE(936)
+#define UPMC1  SPR_ENCODE(937)
+#define UPMC2  SPR_ENCODE(938)
+#define USIA   SPR_ENCODE(939)
+#define UMMCR1 SPR_ENCODE(940)
+#define UPMC3  SPR_ENCODE(941)
+#define UPMC4  SPR_ENCODE(942)
+#define MMCR0  SPR_ENCODE(952)
+#define PMC1   SPR_ENCODE(953)
+#define PMC2   SPR_ENCODE(954)
+#define SIA    SPR_ENCODE(955)
+#define MMCR1  SPR_ENCODE(956)
+#define PMC3   SPR_ENCODE(957)
+#define PMC4   SPR_ENCODE(958)
+#define SDA    SPR_ENCODE(959)
+#define DMISS  SPR_ENCODE(976)
+#define DCMP   SPR_ENCODE(977)
+#define DHASH1 SPR_ENCODE(978)
+#define DHASH2 SPR_ENCODE(979)
+#define IMISS  SPR_ENCODE(980)
+#define ICMP   SPR_ENCODE(981)
+#define RPA    SPR_ENCODE(982)
+#define TCR    SPR_ENCODE(984)
+#define IBR    SPR_ENCODE(986)
+#define ESASRR SPR_ENCODE(987)
+#define SEBR   SPR_ENCODE(990)
+#define SER    SPR_ENCODE(991)
+#define HID0   SPR_ENCODE(1008)
+#define HID1   SPR_ENCODE(1009)
+#define IABR   SPR_ENCODE(1010)
+#define HID2   SPR_ENCODE(1011)
 #define DABR   SPR_ENCODE(1013)
+#define L2PM   SPR_ENCODE(1016)
+#define L2CR   SPR_ENCODE(1017)
+#define ICTC   SPR_ENCODE(1019)
+#define THRM1  SPR_ENCODE(1020)
+#define THRM2  SPR_ENCODE(1021)
+#define THRM3  SPR_ENCODE(1022)
+#define SP     SPR_ENCODE(1021)
+#define LP     SPR_ENCODE(1022)
 #define DABR_MASK 0xFFFFFFF8
 #define FPECR  SPR_ENCODE(1022)
 #define PIR    SPR_ENCODE(1023)
 
-#define TARGET_PAGE_BITS 12
-#include "cpu-all.h"
-
 /* Memory access type :
  * may be needed for precise access rights control and precise exceptions.
  */