#if !defined (__CPU_PPC_H__)
#define __CPU_PPC_H__
-#include <endian.h>
-#include <asm/byteorder.h>
+#define TARGET_LONG_BITS 32
#include "cpu-defs.h"
return *tmp;
}
-/* 24 to 32 bits */
-static inline int32_t s_ext24 (uint32_t value)
-{
- uint16_t utmp = (value >> 8) & 0xFFFF;
- int16_t *tmp = &utmp;
-
- return (*tmp << 8) | (value & 0xFF);
-}
-
#include "config.h"
#include <setjmp.h>
#define PPC_COMMON (PPC_INTEGER | PPC_FLOAT | PPC_FLOW | PPC_MEM | \
PPC_RES | PPC_CACHE | PPC_MISC | PPC_SEGMENT)
+/* PPC 604 */
+#define PPC_604 (PPC_INTEGER | PPC_FLOAT | PPC_FLOW | PPC_MEM | \
+ PPC_RES | PPC_CACHE | PPC_MISC | PPC_EXTERN | PPC_SEGMENT \
+ PPC_MEM_OPT)
/* PPC 740/745/750/755 (aka G3) has external access instructions */
#define PPC_750 (PPC_INTEGER | PPC_FLOAT | PPC_FLOW | PPC_MEM | \
PPC_RES | PPC_CACHE | PPC_MISC | PPC_EXTERN | PPC_SEGMENT)
+typedef struct ppc_tb_t ppc_tb_t;
+
/* Supervisor mode registers */
/* Machine state register */
#define MSR_POW 18
/* special purpose registers */
uint32_t lr;
uint32_t ctr;
- /* Time base */
- uint32_t tb[2];
- /* decrementer */
- uint32_t decr;
/* BATs */
uint32_t DBAT[2][8];
uint32_t IBAT[2][8];
jmp_buf jmp_env;
int exception_index;
int error_code;
- uint32_t exceptions; /* exception queue */
- uint32_t errors[16];
+ int access_type; /* when a memory exception occurs, the access
+ type is stored here */
int user_mode_only; /* user mode only simulation */
struct TranslationBlock *current_tb; /* currently executing TB */
/* soft mmu support */
- /* 0 = kernel, 1 = user */
+ /* in order to avoid passing too many arguments to the memory
+ write helpers, we store some rarely used information in the CPU
+ context) */
+ unsigned long mem_write_pc; /* host pc at which the memory was
+ written */
+ unsigned long mem_write_vaddr; /* target virtual addr at which the
+ memory was written */
+ /* 0 = kernel, 1 = user (may have 2 = kernel code, 3 = user code ?) */
CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
+
+ /* ice debug support */
+ uint32_t breakpoints[MAX_BREAKPOINTS];
+ int nb_breakpoints;
+ int singlestep_enabled; /* XXX: should use CPU single step mode instead */
+
+ /* Time base and decrementer */
+ ppc_tb_t *tb_env;
+
+ /* Power management */
+ int power_mode;
+
/* user data */
void *opaque;
} CPUPPCState;
int cpu_ppc_signal_handler(int host_signum, struct siginfo *info,
void *puc);
-void cpu_ppc_dump_state(CPUPPCState *env, FILE *f, int flags);
+void do_interrupt (CPUPPCState *env);
void cpu_loop_exit(void);
+
+void cpu_ppc_dump_state(CPUPPCState *env, FILE *f, int flags);
void dump_stack (CPUPPCState *env);
-uint32_t _load_xer (void);
-void _store_xer (uint32_t value);
-uint32_t _load_msr (void);
-void _store_msr (uint32_t value);
-void do_interrupt (CPUPPCState *env);
+
+uint32_t _load_xer (CPUPPCState *env);
+void _store_xer (CPUPPCState *env, uint32_t value);
+uint32_t _load_msr (CPUPPCState *env);
+void _store_msr (CPUPPCState *env, uint32_t value);
+
+int cpu_ppc_register (CPUPPCState *env, uint32_t pvr);
+
+/* Time-base and decrementer management */
+#ifndef NO_CPU_IO_DEFS
+uint32_t cpu_ppc_load_tbl (CPUPPCState *env);
+uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
+void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
+void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
+uint32_t cpu_ppc_load_decr (CPUPPCState *env);
+void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
+#endif
#define TARGET_PAGE_BITS 12
#include "cpu-all.h"
#define xer_ca env->xer[1]
#define xer_bc env->xer[0]
+#define MQ SPR_ENCODE(0)
#define XER SPR_ENCODE(1)
+#define RTCUR SPR_ENCODE(4)
+#define RTCLR SPR_ENCODE(5)
#define LR SPR_ENCODE(8)
#define CTR SPR_ENCODE(9)
/* VEA mode SPR */
/* supervisor mode SPR */
#define DSISR SPR_ENCODE(18)
#define DAR SPR_ENCODE(19)
+#define RTCUW SPR_ENCODE(20)
+#define RTCLW SPR_ENCODE(21)
#define DECR SPR_ENCODE(22)
#define SDR1 SPR_ENCODE(25)
#define SRR0 SPR_ENCODE(26)
#define DBAT6L SPR_ENCODE(573)
#define DBAT7U SPR_ENCODE(574)
#define DBAT7L SPR_ENCODE(575)
+#define UMMCR0 SPR_ENCODE(936)
+#define UPMC1 SPR_ENCODE(937)
+#define UPMC2 SPR_ENCODE(938)
+#define USIA SPR_ENCODE(939)
+#define UMMCR1 SPR_ENCODE(940)
+#define UPMC3 SPR_ENCODE(941)
+#define UPMC4 SPR_ENCODE(942)
+#define MMCR0 SPR_ENCODE(952)
+#define PMC1 SPR_ENCODE(953)
+#define PMC2 SPR_ENCODE(954)
+#define SIA SPR_ENCODE(955)
+#define MMCR1 SPR_ENCODE(956)
+#define PMC3 SPR_ENCODE(957)
+#define PMC4 SPR_ENCODE(958)
+#define SDA SPR_ENCODE(959)
+#define DMISS SPR_ENCODE(976)
+#define DCMP SPR_ENCODE(977)
+#define DHASH1 SPR_ENCODE(978)
+#define DHASH2 SPR_ENCODE(979)
+#define IMISS SPR_ENCODE(980)
+#define ICMP SPR_ENCODE(981)
+#define RPA SPR_ENCODE(982)
+#define TCR SPR_ENCODE(984)
+#define IBR SPR_ENCODE(986)
+#define ESASRR SPR_ENCODE(987)
+#define SEBR SPR_ENCODE(990)
+#define SER SPR_ENCODE(991)
+#define HID0 SPR_ENCODE(1008)
+#define HID1 SPR_ENCODE(1009)
+#define IABR SPR_ENCODE(1010)
+#define HID2 SPR_ENCODE(1011)
#define DABR SPR_ENCODE(1013)
+#define L2PM SPR_ENCODE(1016)
+#define L2CR SPR_ENCODE(1017)
+#define ICTC SPR_ENCODE(1019)
+#define THRM1 SPR_ENCODE(1020)
+#define THRM2 SPR_ENCODE(1021)
+#define THRM3 SPR_ENCODE(1022)
+#define SP SPR_ENCODE(1021)
+#define LP SPR_ENCODE(1022)
#define DABR_MASK 0xFFFFFFF8
#define FPECR SPR_ENCODE(1022)
#define PIR SPR_ENCODE(1023)
-#define TARGET_PAGE_BITS 12
-#include "cpu-all.h"
-
-CPUPPCState *cpu_ppc_init(void);
-int cpu_ppc_exec(CPUPPCState *s);
-void cpu_ppc_close(CPUPPCState *s);
-void cpu_ppc_dump_state(CPUPPCState *env, FILE *f, int flags);
-void PPC_init_hw (CPUPPCState *env, uint32_t mem_size,
- uint32_t kernel_addr, uint32_t kernel_size,
- uint32_t stack_addr, int boot_device);
-
/* Memory access type :
* may be needed for precise access rights control and precise exceptions.
*/
/* flags for EXCP_DSI */
EXCP_DSI_DIRECT = 0x10,
EXCP_DSI_STORE = 0x20,
- EXCP_ECXW = 0x40,
+ EXCP_DSI_ECXW = 0x40,
/* Exception subtypes for EXCP_ISI */
EXCP_ISI_TRANSLATE = 0x01, /* Code address can't be translated */
EXCP_ISI_NOEXEC = 0x02, /* Try to fetch from a data segment */
EXCP_ISI_GUARD = 0x03, /* Fetch from guarded memory */
EXCP_ISI_PROT = 0x04, /* Memory protection violation */
+ EXCP_ISI_DIRECT = 0x05, /* Trying to fetch from *
+ * a direct store segment */
/* Exception subtypes for EXCP_ALIGN */
EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
projects / qemu / blobdiff