More efficient target register / TC accesses.

[qemu] / target-mips / translate_init.c

diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index d84bee0..b7d68cc 100644 (file)
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -546,8 +546,6 @@ static int cpu_mips_register (CPUMIPSState *env, const mips_def_t *def)
     env->CP0_TCStatus_rw_bitmask = def->CP0_TCStatus_rw_bitmask;
     env->CP0_SRSCtl = def->CP0_SRSCtl;
     env->current_tc = 0;
-    env->current_tc_gprs = &env->gpr[env->current_tc][0];
-    env->current_tc_hi = &env->HI[env->current_tc][0];
     env->SEGBITS = def->SEGBITS;
     env->SEGMask = (target_ulong)((1ULL << def->SEGBITS) - 1);
 #if defined(TARGET_MIPS64)