#include "exec-all.h"
#include "disas.h"
-#define MIPS_DEBUG_DISAS
+//#define MIPS_DEBUG_DISAS
//#define MIPS_SINGLE_STEP
+#ifdef USE_DIRECT_JUMP
+#define TBPARAM(x)
+#else
+#define TBPARAM(x) (long)(x)
+#endif
+
enum {
#define DEF(s, n, copy_size) INDEX_op_ ## s,
#include "opc.h"
#include "gen-op.h"
+/* MIPS opcodes */
+#define EXT_SPECIAL 0x100
+#define EXT_SPECIAL2 0x200
+#define EXT_REGIMM 0x300
+#define EXT_CP0 0x400
+#define EXT_CP1 0x500
+#define EXT_CP2 0x600
+#define EXT_CP3 0x700
+
+enum {
+ /* indirect opcode tables */
+ OPC_SPECIAL = 0x00,
+ OPC_BREGIMM = 0x01,
+ OPC_CP0 = 0x10,
+ OPC_CP1 = 0x11,
+ OPC_CP2 = 0x12,
+ OPC_CP3 = 0x13,
+ OPC_SPECIAL2 = 0x1C,
+ /* arithmetic with immediate */
+ OPC_ADDI = 0x08,
+ OPC_ADDIU = 0x09,
+ OPC_SLTI = 0x0A,
+ OPC_SLTIU = 0x0B,
+ OPC_ANDI = 0x0C,
+ OPC_ORI = 0x0D,
+ OPC_XORI = 0x0E,
+ OPC_LUI = 0x0F,
+ /* Jump and branches */
+ OPC_J = 0x02,
+ OPC_JAL = 0x03,
+ OPC_BEQ = 0x04, /* Unconditional if rs = rt = 0 (B) */
+ OPC_BEQL = 0x14,
+ OPC_BNE = 0x05,
+ OPC_BNEL = 0x15,
+ OPC_BLEZ = 0x06,
+ OPC_BLEZL = 0x16,
+ OPC_BGTZ = 0x07,
+ OPC_BGTZL = 0x17,
+ OPC_JALX = 0x1D, /* MIPS 16 only */
+ /* Load and stores */
+ OPC_LB = 0x20,
+ OPC_LH = 0x21,
+ OPC_LWL = 0x22,
+ OPC_LW = 0x23,
+ OPC_LBU = 0x24,
+ OPC_LHU = 0x25,
+ OPC_LWR = 0x26,
+ OPC_SB = 0x28,
+ OPC_SH = 0x29,
+ OPC_SWL = 0x2A,
+ OPC_SW = 0x2B,
+ OPC_SWR = 0x2E,
+ OPC_LL = 0x30,
+ OPC_SC = 0x38,
+ /* Floating point load/store */
+ OPC_LWC1 = 0x31,
+ OPC_LWC2 = 0x32,
+ OPC_LDC1 = 0x35,
+ OPC_LDC2 = 0x36,
+ OPC_SWC1 = 0x39,
+ OPC_SWC2 = 0x3A,
+ OPC_SDC1 = 0x3D,
+ OPC_SDC2 = 0x3E,
+ /* Cache and prefetch */
+ OPC_CACHE = 0x2F,
+ OPC_PREF = 0x33,
+};
+
+/* MIPS special opcodes */
+enum {
+ /* Shifts */
+ OPC_SLL = 0x00 | EXT_SPECIAL,
+ /* NOP is SLL r0, r0, 0 */
+ /* SSNOP is SLL r0, r0, 1 */
+ OPC_SRL = 0x02 | EXT_SPECIAL,
+ OPC_SRA = 0x03 | EXT_SPECIAL,
+ OPC_SLLV = 0x04 | EXT_SPECIAL,
+ OPC_SRLV = 0x06 | EXT_SPECIAL,
+ OPC_SRAV = 0x07 | EXT_SPECIAL,
+ /* Multiplication / division */
+ OPC_MULT = 0x18 | EXT_SPECIAL,
+ OPC_MULTU = 0x19 | EXT_SPECIAL,
+ OPC_DIV = 0x1A | EXT_SPECIAL,
+ OPC_DIVU = 0x1B | EXT_SPECIAL,
+ /* 2 registers arithmetic / logic */
+ OPC_ADD = 0x20 | EXT_SPECIAL,
+ OPC_ADDU = 0x21 | EXT_SPECIAL,
+ OPC_SUB = 0x22 | EXT_SPECIAL,
+ OPC_SUBU = 0x23 | EXT_SPECIAL,
+ OPC_AND = 0x24 | EXT_SPECIAL,
+ OPC_OR = 0x25 | EXT_SPECIAL,
+ OPC_XOR = 0x26 | EXT_SPECIAL,
+ OPC_NOR = 0x27 | EXT_SPECIAL,
+ OPC_SLT = 0x2A | EXT_SPECIAL,
+ OPC_SLTU = 0x2B | EXT_SPECIAL,
+ /* Jumps */
+ OPC_JR = 0x08 | EXT_SPECIAL,
+ OPC_JALR = 0x09 | EXT_SPECIAL,
+ /* Traps */
+ OPC_TGE = 0x30 | EXT_SPECIAL,
+ OPC_TGEU = 0x31 | EXT_SPECIAL,
+ OPC_TLT = 0x32 | EXT_SPECIAL,
+ OPC_TLTU = 0x33 | EXT_SPECIAL,
+ OPC_TEQ = 0x34 | EXT_SPECIAL,
+ OPC_TNE = 0x36 | EXT_SPECIAL,
+ /* HI / LO registers load & stores */
+ OPC_MFHI = 0x10 | EXT_SPECIAL,
+ OPC_MTHI = 0x11 | EXT_SPECIAL,
+ OPC_MFLO = 0x12 | EXT_SPECIAL,
+ OPC_MTLO = 0x13 | EXT_SPECIAL,
+ /* Conditional moves */
+ OPC_MOVZ = 0x0A | EXT_SPECIAL,
+ OPC_MOVN = 0x0B | EXT_SPECIAL,
+
+ OPC_MOVCI = 0x01 | EXT_SPECIAL,
+
+ /* Special */
+ OPC_PMON = 0x05 | EXT_SPECIAL,
+ OPC_SYSCALL = 0x0C | EXT_SPECIAL,
+ OPC_BREAK = 0x0D | EXT_SPECIAL,
+ OPC_SYNC = 0x0F | EXT_SPECIAL,
+};
+
+enum {
+ /* Mutiply & xxx operations */
+ OPC_MADD = 0x00 | EXT_SPECIAL2,
+ OPC_MADDU = 0x01 | EXT_SPECIAL2,
+ OPC_MUL = 0x02 | EXT_SPECIAL2,
+ OPC_MSUB = 0x04 | EXT_SPECIAL2,
+ OPC_MSUBU = 0x05 | EXT_SPECIAL2,
+ /* Misc */
+ OPC_CLZ = 0x20 | EXT_SPECIAL2,
+ OPC_CLO = 0x21 | EXT_SPECIAL2,
+ /* Special */
+ OPC_SDBBP = 0x3F | EXT_SPECIAL2,
+};
+
+/* Branch REGIMM */
+enum {
+ OPC_BLTZ = 0x00 | EXT_REGIMM,
+ OPC_BLTZL = 0x02 | EXT_REGIMM,
+ OPC_BGEZ = 0x01 | EXT_REGIMM,
+ OPC_BGEZL = 0x03 | EXT_REGIMM,
+ OPC_BLTZAL = 0x10 | EXT_REGIMM,
+ OPC_BLTZALL = 0x12 | EXT_REGIMM,
+ OPC_BGEZAL = 0x11 | EXT_REGIMM,
+ OPC_BGEZALL = 0x13 | EXT_REGIMM,
+ OPC_TGEI = 0x08 | EXT_REGIMM,
+ OPC_TGEIU = 0x09 | EXT_REGIMM,
+ OPC_TLTI = 0x0A | EXT_REGIMM,
+ OPC_TLTIU = 0x0B | EXT_REGIMM,
+ OPC_TEQI = 0x0C | EXT_REGIMM,
+ OPC_TNEI = 0x0E | EXT_REGIMM,
+};
+
+enum {
+ /* Coprocessor 0 (MMU) */
+ OPC_MFC0 = 0x00 | EXT_CP0,
+ OPC_MTC0 = 0x04 | EXT_CP0,
+ OPC_TLBR = 0x01 | EXT_CP0,
+ OPC_TLBWI = 0x02 | EXT_CP0,
+ OPC_TLBWR = 0x06 | EXT_CP0,
+ OPC_TLBP = 0x08 | EXT_CP0,
+ OPC_ERET = 0x18 | EXT_CP0,
+ OPC_DERET = 0x1F | EXT_CP0,
+ OPC_WAIT = 0x20 | EXT_CP0,
+};
+
const unsigned char *regnames[] =
{ "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3",
"t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
}
}
-static inline void generate_exception (DisasContext *ctx, int excp)
+static inline void generate_exception_err (DisasContext *ctx, int excp, int err)
{
#if defined MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM)
fprintf(logfile, "%s: raise exception %d\n", __func__, excp);
#endif
save_cpu_state(ctx, 1);
- gen_op_raise_exception(excp);
+ if (err == 0)
+ gen_op_raise_exception(excp);
+ else
+ gen_op_raise_exception_err(excp, err);
ctx->bstate = BS_EXCP;
}
+static inline void generate_exception (DisasContext *ctx, int excp)
+{
+ generate_exception_err (ctx, excp, 0);
+}
+
#if defined(CONFIG_USER_ONLY)
#define op_ldst(name) gen_op_##name##_raw()
#define OP_LD_TABLE(width)
opn = "lbu";
break;
case OPC_LWL:
+ GEN_LOAD_REG_TN(T1, rt);
op_ldst(lwl);
GEN_STORE_TN_REG(rt, T0);
opn = "lwl";
opn = "swr";
break;
case OPC_LWR:
+ GEN_LOAD_REG_TN(T1, rt);
op_ldst(lwr);
GEN_STORE_TN_REG(rt, T0);
opn = "lwr";
ctx->bstate = BS_STOP;
}
+static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
+{
+ TranslationBlock *tb;
+ tb = ctx->tb;
+ if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
+ if (n == 0)
+ gen_op_goto_tb0(TBPARAM(tb));
+ else
+ gen_op_goto_tb1(TBPARAM(tb));
+ gen_op_save_pc(dest);
+ gen_op_set_T0((long)tb + n);
+ gen_op_exit_tb();
+ } else {
+ gen_op_save_pc(dest);
+ gen_op_set_T0(0);
+ gen_op_exit_tb();
+ }
+}
+
/* Branches (before delay slot) */
static void gen_compute_branch (DisasContext *ctx, uint16_t opc,
int rs, int rt, int32_t offset)
case OPC_BLEZ: /* 0 <= 0 */
case OPC_BLEZL: /* 0 <= 0 likely */
/* Always take */
- ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_B;
+ ctx->hflags |= MIPS_HFLAG_B;
MIPS_DEBUG("balways");
break;
case OPC_BGEZAL: /* 0 >= 0 */
case OPC_BGEZALL: /* 0 >= 0 likely */
/* Always take and link */
blink = 31;
- ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_B;
+ ctx->hflags |= MIPS_HFLAG_B;
MIPS_DEBUG("balways and link");
break;
case OPC_BNE: /* rx != rx */
case OPC_BGTZ: /* 0 > 0 */
case OPC_BLTZ: /* 0 < 0 */
- case OPC_BLTZAL: /* 0 < 0 */
/* Treated as NOP */
MIPS_DEBUG("bnever (NOP)");
return;
+ case OPC_BLTZAL: /* 0 < 0 */
+ gen_op_set_T0(ctx->pc + 8);
+ gen_op_store_T0_gpr(31);
+ return;
+ case OPC_BLTZALL: /* 0 < 0 likely */
+ gen_op_set_T0(ctx->pc + 8);
+ gen_op_store_T0_gpr(31);
+ gen_goto_tb(ctx, 0, ctx->pc + 4);
+ return;
case OPC_BNEL: /* rx != rx likely */
case OPC_BGTZL: /* 0 > 0 likely */
- case OPC_BLTZALL: /* 0 < 0 likely */
case OPC_BLTZL: /* 0 < 0 likely */
/* Skip the instruction in the delay slot */
MIPS_DEBUG("bnever and skip");
- gen_op_branch((long)ctx->tb, ctx->pc + 4);
+ gen_goto_tb(ctx, 0, ctx->pc + 4);
return;
case OPC_J:
- ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_B;
+ ctx->hflags |= MIPS_HFLAG_B;
MIPS_DEBUG("j %08x", btarget);
break;
case OPC_JAL:
blink = 31;
- ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_B;
+ ctx->hflags |= MIPS_HFLAG_B;
MIPS_DEBUG("jal %08x", btarget);
break;
case OPC_JR:
- ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_BR;
+ ctx->hflags |= MIPS_HFLAG_BR;
MIPS_DEBUG("jr %s", regnames[rs]);
break;
case OPC_JALR:
blink = rt;
- ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_BR;
+ ctx->hflags |= MIPS_HFLAG_BR;
MIPS_DEBUG("jalr %s, %s", regnames[rt], regnames[rs]);
break;
default:
blink = 31;
MIPS_DEBUG("bltzal %s, %08x", regnames[rs], btarget);
not_likely:
- ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_BC;
+ ctx->hflags |= MIPS_HFLAG_BC;
break;
case OPC_BLTZALL:
gen_op_ltz();
blink = 31;
MIPS_DEBUG("bltzall %s, %08x", regnames[rs], btarget);
likely:
- ctx->hflags |= MIPS_HFLAG_DS | MIPS_HFLAG_BL;
+ ctx->hflags |= MIPS_HFLAG_BL;
break;
}
gen_op_set_bcond();
{
const unsigned char *opn = "unk";
- if (!(ctx->CP0_Status & (1 << CP0St_CU0))) {
+ if (!(ctx->CP0_Status & (1 << CP0St_CU0)) &&
+ (ctx->hflags & MIPS_HFLAG_UM) &&
+ !(ctx->hflags & MIPS_HFLAG_ERL) &&
+ !(ctx->hflags & MIPS_HFLAG_EXL)) {
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile, "CP0 is not usable\n");
}
- gen_op_raise_exception_err(EXCP_CpU, 0);
+ generate_exception_err (ctx, EXCP_CpU, 0);
return;
}
switch (opc) {
ctx->bstate = BS_EXCP;
}
break;
- /* XXX: TODO: WAIT */
+ case OPC_WAIT:
+ opn = "wait";
+ /* If we get an exception, we want to restart at next instruction */
+ ctx->pc += 4;
+ save_cpu_state(ctx, 1);
+ ctx->pc -= 4;
+ gen_op_wait();
+ ctx->bstate = BS_EXCP;
+ break;
default:
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile, "Invalid CP0 opcode: %08x %03x %03x %03x\n",
#endif
+static void gen_blikely(DisasContext *ctx)
+{
+ int l1;
+ l1 = gen_new_label();
+ gen_op_jnz_T2(l1);
+ gen_op_save_state(ctx->hflags & ~MIPS_HFLAG_BMASK);
+ gen_goto_tb(ctx, 1, ctx->pc + 4);
+ gen_set_label(l1);
+}
+
static void decode_opc (DisasContext *ctx)
{
int32_t offset;
uint16_t op, op1;
int16_t imm;
- if ((ctx->hflags & MIPS_HFLAG_DS) &&
- (ctx->hflags & MIPS_HFLAG_BL)) {
+ if ((ctx->hflags & MIPS_HFLAG_BMASK) == MIPS_HFLAG_BL) {
/* Handle blikely not taken case */
MIPS_DEBUG("blikely condition (%08x)", ctx->pc + 4);
- gen_op_blikely((long)ctx->tb, ctx->pc + 4,
- ctx->hflags & ~(MIPS_HFLAG_BMASK | MIPS_HFLAG_DS));
+ gen_blikely(ctx);
}
op = ctx->opcode >> 26;
rs = ((ctx->opcode >> 21) & 0x1F);
case 0x05: /* Pmon entry point */
gen_op_pmon((ctx->opcode >> 6) & 0x1F);
break;
-#if defined (MIPS_HAS_MOVCI)
+
case 0x01: /* MOVCI */
+#if defined (MIPS_HAS_MOVCI)
+ /* XXX */
+#else
+ /* Not implemented */
+ generate_exception_err (ctx, EXCP_CpU, 1);
#endif
+ break;
+
#if defined (TARGET_MIPS64)
case 0x14: /* MIPS64 specific opcodes */
case 0x16:
gen_cp0(ctx, op1 | EXT_CP0, rt, rd);
break;
default:
- gen_cp0(ctx, (ctx->opcode & 0x1F) | EXT_CP0, rt, rd);
+ gen_cp0(ctx, (ctx->opcode & 0x3F) | EXT_CP0, rt, rd);
break;
}
break;
break;
case 0x3F: /* HACK */
break;
+
+ /* Floating point. */
+ case 0x31: /* LWC1 */
+ case 0x35: /* LDC1 */
+ case 0x39: /* SWC1 */
+ case 0x3D: /* SDC1 */
+ case 0x11: /* CP1 opcode */
#if defined(MIPS_USES_FPU)
- case 0x31 ... 0x32: /* Floating point load/store */
- case 0x35 ... 0x36:
- case 0x3A ... 0x3B:
- case 0x3D ... 0x3E:
- /* Not implemented */
/* XXX: not correct */
+#else
+ generate_exception_err(ctx, EXCP_CpU, 1);
#endif
- case 0x11: /* CP1 opcode */
- /* Not implemented */
- /* XXX: not correct */
+ break;
+
+ /* COP2. */
+ case 0x32: /* LWC2 */
+ case 0x36: /* LDC2 */
+ case 0x3A: /* SWC2 */
+ case 0x3E: /* SDC2 */
case 0x12: /* CP2 opcode */
/* Not implemented */
- /* XXX: not correct */
+ generate_exception_err(ctx, EXCP_CpU, 2);
+ break;
+
case 0x13: /* CP3 opcode */
/* Not implemented */
- /* XXX: not correct */
+ generate_exception_err(ctx, EXCP_CpU, 3);
+ break;
+
#if defined (TARGET_MIPS64)
case 0x18 ... 0x1B:
case 0x27:
#endif
case 0x1E:
/* ASE specific */
-#if defined (MIPS_HAS_LSC)
- case 0x31: /* LWC1 */
- case 0x32: /* LWC2 */
- case 0x35: /* SDC1 */
- case 0x36: /* SDC2 */
-#endif
default: /* Invalid */
MIPS_INVAL("");
generate_exception(ctx, EXCP_RI);
break;
}
- if (ctx->hflags & MIPS_HFLAG_DS) {
+ if (ctx->hflags & MIPS_HFLAG_BMASK) {
int hflags = ctx->hflags;
/* Branches completion */
- ctx->hflags &= ~(MIPS_HFLAG_BMASK | MIPS_HFLAG_DS);
+ ctx->hflags &= ~MIPS_HFLAG_BMASK;
ctx->bstate = BS_BRANCH;
save_cpu_state(ctx, 0);
switch (hflags & MIPS_HFLAG_BMASK) {
case MIPS_HFLAG_B:
/* unconditional branch */
MIPS_DEBUG("unconditional branch");
- gen_op_branch((long)ctx->tb, ctx->btarget);
+ gen_goto_tb(ctx, 0, ctx->btarget);
break;
case MIPS_HFLAG_BL:
/* blikely taken case */
MIPS_DEBUG("blikely branch taken");
- gen_op_branch((long)ctx->tb, ctx->btarget);
+ gen_goto_tb(ctx, 0, ctx->btarget);
break;
case MIPS_HFLAG_BC:
/* Conditional branch */
MIPS_DEBUG("conditional branch");
- gen_op_bcond((long)ctx->tb, ctx->btarget, ctx->pc + 4);
+ {
+ int l1;
+ l1 = gen_new_label();
+ gen_op_jnz_T2(l1);
+ gen_goto_tb(ctx, 1, ctx->pc + 4);
+ gen_set_label(l1);
+ gen_goto_tb(ctx, 0, ctx->btarget);
+ }
break;
case MIPS_HFLAG_BR:
/* unconditional branch to register */
uint16_t *gen_opc_end;
int j, lj = -1;
+ if (search_pc && loglevel)
+ fprintf (logfile, "search pc %d\n", search_pc);
+
pc_start = tb->pc;
gen_opc_ptr = gen_opc_buf;
gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
gen_opparam_ptr = gen_opparam_buf;
+ nb_gen_labels = 0;
ctx.pc = pc_start;
+ ctx.saved_pc = -1;
ctx.tb = tb;
ctx.bstate = BS_NONE;
- /* Restore delay slot state */
- ctx.hflags = env->hflags;
+ /* Restore delay slot state from the tb context. */
+ ctx.hflags = tb->flags;
ctx.saved_hflags = ctx.hflags;
if (ctx.hflags & MIPS_HFLAG_BR) {
gen_op_restore_breg_target();
#ifdef DEBUG_DISAS
if (loglevel & CPU_LOG_TB_CPU) {
fprintf(logfile, "------------------------------------------------\n");
+ /* FIXME: This may print out stale hflags from env... */
cpu_dump_state(env, logfile, fprintf, 0);
}
#endif
#if defined MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM)
- fprintf(logfile, "\ntb %p super %d cond %04x %04x\n",
- tb, ctx.mem_idx, ctx.hflags, env->hflags);
+ fprintf(logfile, "\ntb %p super %d cond %04x\n",
+ tb, ctx.mem_idx, ctx.hflags);
#endif
while (ctx.bstate == BS_NONE && gen_opc_ptr < gen_opc_end) {
+ if (env->nb_breakpoints > 0) {
+ for(j = 0; j < env->nb_breakpoints; j++) {
+ if (env->breakpoints[j] == ctx.pc) {
+ save_cpu_state(ctxp, 1);
+ ctx.bstate = BS_BRANCH;
+ gen_op_debug();
+ goto done_generating;
+ }
+ }
+ }
+
if (search_pc) {
j = gen_opc_ptr - gen_opc_buf;
- save_cpu_state(ctxp, 1);
if (lj < j) {
lj++;
while (lj < j)
gen_opc_instr_start[lj++] = 0;
- gen_opc_pc[lj] = ctx.pc;
- gen_opc_instr_start[lj] = 1;
}
+ gen_opc_pc[lj] = ctx.pc;
+ gen_opc_hflags[lj] = ctx.hflags & MIPS_HFLAG_BMASK;
+ gen_opc_instr_start[lj] = 1;
}
ctx.opcode = ldl_code(ctx.pc);
decode_opc(&ctx);
ctx.pc += 4;
+
+ if (env->singlestep_enabled)
+ break;
+
if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0)
break;
+
#if defined (MIPS_SINGLE_STEP)
break;
#endif
}
- if (ctx.bstate != BS_BRANCH && ctx.bstate != BS_EXCP) {
+ if (env->singlestep_enabled) {
+ save_cpu_state(ctxp, ctx.bstate == BS_NONE);
+ gen_op_debug();
+ goto done_generating;
+ }
+ else if (ctx.bstate != BS_BRANCH && ctx.bstate != BS_EXCP) {
save_cpu_state(ctxp, 0);
- gen_op_branch((long)ctx.tb, ctx.pc);
+ gen_goto_tb(&ctx, 0, ctx.pc);
}
gen_op_reset_T0();
/* Generate the return instruction */
gen_op_exit_tb();
+done_generating:
*gen_opc_ptr = INDEX_op_end;
if (search_pc) {
j = gen_opc_ptr - gen_opc_buf;
int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
int flags)
{
+ uint32_t c0_status;
int i;
cpu_fprintf(f, "pc=0x%08x HI=0x%08x LO=0x%08x ds %04x %08x %d\n",
if ((i & 3) == 3)
cpu_fprintf(f, "\n");
}
+
+ c0_status = env->CP0_Status;
+ if (env->hflags & MIPS_HFLAG_UM)
+ c0_status |= (1 << CP0St_UM);
+ if (env->hflags & MIPS_HFLAG_ERL)
+ c0_status |= (1 << CP0St_ERL);
+ if (env->hflags & MIPS_HFLAG_EXL)
+ c0_status |= (1 << CP0St_EXL);
+
cpu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x%08x\n",
- env->CP0_Status, env->CP0_Cause, env->CP0_EPC);
+ c0_status, env->CP0_Cause, env->CP0_EPC);
cpu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x%08x\n",
env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr);
}
{
CPUMIPSState *env;
- cpu_exec_init();
env = qemu_mallocz(sizeof(CPUMIPSState));
if (!env)
return NULL;
+ cpu_exec_init(env);
tlb_flush(env, 1);
/* Minimal init */
env->PC = 0xBFC00000;
env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER);
env->CP0_PRid = MIPS_CPU;
env->exception_index = EXCP_NONE;
-
- cpu_single_env = env;
-
+#if defined(CONFIG_USER_ONLY)
+ env->hflags |= MIPS_HFLAG_UM;
+#endif
return env;
}
projects / qemu / blobdiff