struct TranslationBlock *tb;
target_ulong pc, saved_pc;
uint32_t opcode;
- uint32_t fp_status;
/* Routine used to access memory */
int mem_idx;
uint32_t hflags, saved_hflags;
tcg_temp_free(t1);
}
-/* CP0 (MMU and control) */
#ifndef CONFIG_USER_ONLY
+/* CP0 (MMU and control) */
static inline void gen_mfc0_load32 (TCGv t, target_ulong off)
{
TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
rn, reg, sel);
}
#endif
- tcg_temp_free(t0);
/* For simplicity assume that all writes can cause interrupts. */
if (use_icount) {
gen_io_end();
return;
die:
- tcg_temp_free(t0);
#if defined MIPS_DEBUG_DISAS
if (loglevel & CPU_LOG_TB_IN_ASM) {
fprintf(logfile, "dmtc0 %s (reg %d sel %d)\n",
TCGCond cond;
TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
TCGv t1 = tcg_temp_local_new(TCG_TYPE_TL);
+ TCGv r_tmp = tcg_temp_local_new(TCG_TYPE_I32);
if (cc)
ccbit = 1 << (24 + cc);
gen_load_gpr(t0, rd);
gen_load_gpr(t1, rs);
- {
- TCGv r_ptr = tcg_temp_new(TCG_TYPE_PTR);
- TCGv r_tmp = tcg_temp_local_new(TCG_TYPE_I32);
+ tcg_gen_ld_i32(r_tmp, current_fpu, offsetof(CPUMIPSFPUContext, fcr31));
+ tcg_gen_andi_i32(r_tmp, r_tmp, ccbit);
+ tcg_gen_brcondi_i32(cond, r_tmp, 0, l1);
+ tcg_temp_free(r_tmp);
- tcg_gen_ld_ptr(r_ptr, cpu_env, offsetof(CPUState, fpu));
- tcg_gen_ld_i32(r_tmp, r_ptr, offsetof(CPUMIPSFPUContext, fcr31));
- tcg_temp_free(r_ptr);
- tcg_gen_andi_i32(r_tmp, r_tmp, ccbit);
- tcg_gen_brcondi_i32(cond, r_tmp, 0, l1);
- tcg_temp_free(r_tmp);
- }
tcg_gen_mov_tl(t0, t1);
tcg_temp_free(t1);
tcg_gen_helper_1_0(do_rdhwr_ccres, t0);
break;
case 29:
-#if defined (CONFIG_USER_ONLY)
- tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, tls_value));
- break;
-#else
- /* XXX: Some CPUs implement this in hardware. Not supported yet. */
-#endif
+ if (env->user_mode_only) {
+ tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, tls_value));
+ break;
+ } else {
+ /* XXX: Some CPUs implement this in hardware.
+ Not supported yet. */
+ }
default: /* Invalid */
MIPS_INVAL("rdhwr");
generate_exception(ctx, EXCP_RI);
case OPC_DMTC0:
#endif
#ifndef CONFIG_USER_ONLY
- gen_cp0(env, ctx, op1, rt, rd);
-#endif
+ if (!env->user_mode_only)
+ gen_cp0(env, ctx, op1, rt, rd);
+#endif /* !CONFIG_USER_ONLY */
break;
case OPC_C0_FIRST ... OPC_C0_LAST:
#ifndef CONFIG_USER_ONLY
- gen_cp0(env, ctx, MASK_C0(ctx->opcode), rt, rd);
-#endif
+ if (!env->user_mode_only)
+ gen_cp0(env, ctx, MASK_C0(ctx->opcode), rt, rd);
+#endif /* !CONFIG_USER_ONLY */
break;
case OPC_MFMC0:
- op2 = MASK_MFMC0(ctx->opcode);
- {
+#ifndef CONFIG_USER_ONLY
+ if (!env->user_mode_only) {
TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
+ op2 = MASK_MFMC0(ctx->opcode);
switch (op2) {
case OPC_DMT:
check_insn(env, ctx, ASE_MT);
gen_store_gpr(t0, rt);
tcg_temp_free(t0);
}
+#endif /* !CONFIG_USER_ONLY */
break;
case OPC_RDPGPR:
check_insn(env, ctx, ISA_MIPS32R2);
/* Restore delay slot state from the tb context. */
ctx.hflags = (uint32_t)tb->flags; /* FIXME: maybe use 64 bits here? */
restore_cpu_state(env, &ctx);
-#if defined(CONFIG_USER_ONLY)
- ctx.mem_idx = MIPS_HFLAG_UM;
-#else
- ctx.mem_idx = ctx.hflags & MIPS_HFLAG_KSU;
-#endif
+ if (env->user_mode_only)
+ ctx.mem_idx = MIPS_HFLAG_UM;
+ else
+ ctx.mem_idx = ctx.hflags & MIPS_HFLAG_KSU;
num_insns = 0;
max_insns = tb->cflags & CF_COUNT_MASK;
if (max_insns == 0)
gen_intermediate_code_internal(env, tb, 1);
}
-void fpu_dump_state(CPUState *env, FILE *f,
- int (*fpu_fprintf)(FILE *f, const char *fmt, ...),
- int flags)
+static void fpu_dump_state(CPUState *env, FILE *f,
+ int (*fpu_fprintf)(FILE *f, const char *fmt, ...),
+ int flags)
{
int i;
int is_fpu64 = !!(env->hflags & MIPS_HFLAG_F64);
#undef printfpr
}
-void dump_fpu (CPUState *env)
-{
- if (loglevel) {
- fprintf(logfile,
- "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx
- " LO=0x" TARGET_FMT_lx " ds %04x " TARGET_FMT_lx
- " %04x\n",
- env->active_tc.PC, env->active_tc.HI[0],
- env->active_tc.LO[0], env->hflags, env->btarget,
- env->bcond);
- fpu_dump_state(env, logfile, fprintf, 0);
- }
-}
-
#if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS)
/* Debug help: The architecture requires 32bit code to maintain proper
sign-extended values on 64bit machines. */
#define SIGN_EXT_P(val) ((((val) & ~0x7fffffff) == 0) || (((val) & ~0x7fffffff) == ~0x7fffffff))
-void cpu_mips_check_sign_extensions (CPUState *env, FILE *f,
- int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
- int flags)
+static void
+cpu_mips_check_sign_extensions (CPUState *env, FILE *f,
+ int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
+ int flags)
{
int i;
int i;
cpu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx " LO=0x" TARGET_FMT_lx " ds %04x " TARGET_FMT_lx " %d\n",
- env->active_tc.PC, env->active_tc.HI, env->active_tc.LO, env->hflags, env->btarget, env->bcond);
+ env->active_tc.PC, env->active_tc.HI[0], env->active_tc.LO[0],
+ env->hflags, env->btarget, env->bcond);
for (i = 0; i < 32; i++) {
if ((i & 3) == 0)
cpu_fprintf(f, "GPR%02d:", i);
tlb_flush(env, 1);
/* Minimal init */
-#if !defined(CONFIG_USER_ONLY)
- if (env->hflags & MIPS_HFLAG_BMASK) {
- /* If the exception was raised from a delay slot,
- * come back to the jump. */
- env->CP0_ErrorEPC = env->active_tc.PC - 4;
+#if defined(CONFIG_USER_ONLY)
+ env->user_mode_only = 1;
+#endif
+ if (env->user_mode_only) {
+ env->hflags = MIPS_HFLAG_UM;
} else {
- env->CP0_ErrorEPC = env->active_tc.PC;
- }
- env->active_tc.PC = (int32_t)0xBFC00000;
- env->CP0_Wired = 0;
- /* SMP not implemented */
- env->CP0_EBase = 0x80000000;
- env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
- /* vectored interrupts not implemented, timer on int 7,
- no performance counters. */
- env->CP0_IntCtl = 0xe0000000;
- {
- int i;
-
- for (i = 0; i < 7; i++) {
- env->CP0_WatchLo[i] = 0;
- env->CP0_WatchHi[i] = 0x80000000;
+ if (env->hflags & MIPS_HFLAG_BMASK) {
+ /* If the exception was raised from a delay slot,
+ come back to the jump. */
+ env->CP0_ErrorEPC = env->active_tc.PC - 4;
+ } else {
+ env->CP0_ErrorEPC = env->active_tc.PC;
+ }
+ env->active_tc.PC = (int32_t)0xBFC00000;
+ env->CP0_Wired = 0;
+ /* SMP not implemented */
+ env->CP0_EBase = 0x80000000;
+ env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
+ /* vectored interrupts not implemented, timer on int 7,
+ no performance counters. */
+ env->CP0_IntCtl = 0xe0000000;
+ {
+ int i;
+
+ for (i = 0; i < 7; i++) {
+ env->CP0_WatchLo[i] = 0;
+ env->CP0_WatchHi[i] = 0x80000000;
+ }
+ env->CP0_WatchLo[7] = 0;
+ env->CP0_WatchHi[7] = 0;
}
- env->CP0_WatchLo[7] = 0;
- env->CP0_WatchHi[7] = 0;
+ /* Count register increments in debug mode, EJTAG version 1 */
+ env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER);
+ env->hflags = MIPS_HFLAG_CP0;
}
- /* Count register increments in debug mode, EJTAG version 1 */
- env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER);
-#endif
env->exception_index = EXCP_NONE;
-#if defined(CONFIG_USER_ONLY)
- env->hflags = MIPS_HFLAG_UM;
- env->user_mode_only = 1;
-#else
- env->hflags = MIPS_HFLAG_CP0;
-#endif
cpu_mips_register(env, env->cpu_model);
}
projects / qemu / blobdiff